CHAPTER 13 OUTPUT STAGES AND POWER AMPLIFIERS

Chapter Outline
13.1 Classification of Output Stages
13.2 Class A Output Stage
13.3 Class B Output Stage
13.4 Class AB Output Stage
13.5 Biasing the Class AB Circuit
13.6 CMOS Class AB Output
p Stages
g

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13.1 CLASSIFICATIONS OF OUTPUT STAGES

Output Stages
Class A output stage:
Bias current is greater than the magnitude of the signal current
Conduction angle is 360
Class B output stage:
Biased at zero dc current
Conduction angle is 180
Another transistor conducts during the alternate half-cycle
Class AB output stage:
An
A iintermediate
t
di t class
l between
b t
A andd B
Biased at a nonzero dc current much smaller than the peak current of the signal
Conduction angle is greater than 180 but much smaller than 360
Two transistors are used and currents are combined at the load
Class C output stage:
Conduction angle is smaller than 180
The current is passed through a parallel LC network to obtain the output signal
Class A, B and AB are used as output stage of op amps
Class AB amplifiers are preferred for audio power amplifier
Class C amplifiers are usually used at higher frequencies

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 Collector current waveforms for the transistors operating in different classes

The classification also applies for output stages with MOSFETs

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13.2 CLASS A OUTPUT STAGE

Transfer Characteristics
Q1 biased with a constant current I supplied by Q2
vO vI vBE1
vO max VCC VCE1sat
vO min IRL or vO min VCC VCE 2 sat

| VCC VCE 2 sat |

RL

Si
Signal
l Waveforms
W f
The output swing from VCC to VCC for I = VCC/RL
The instantaneous power dissipation in Q1: PD1 = vCE1iC1

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Power Dissipation
Power dissipation for RL = VCC/I:
The maximum instantaneous power dissipation in Q1 is VCCI
This is equal to the power dissipation in Q1 with no input signal
applied (quiescent power dissipation)
The transistor Q1 much be able to withstand a continuous power
dissipation of VCCI
Power dissipation for unloaded case:
Maximum power dissipation occurs when vO = VCC
The maximum power dissipation in Q1 is 2VCCI
Power dissipation for an output short circuit:
A positive input may lead to an infinite load current
The output stages are usually equipped with short-circuit protection to guard against such a situation
Power dissipation in Q2:
Q2 conducts a constant current I
Maximum voltage across the collector and the emitter is 2VCC
Maximum instantaneous power dissipation in Q2 is 2VCCI
A more significant quantity for design purposes is the average power dissipation of VCCI

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Power Conversion Efficiency

The power conversion efficiency is defined as PL(load power) /PS(supply power)

The load power (PL) with an sinusoid output with a peak value of Vo is

(Vo / 2 ) 2 1 Vo2

PL
RL
2 RL

The total average supply power is PS = 2VCCI

The conversion efficiency is given by

1 Vo2
1 Vo Vo

4 IRLVCC 4 IRL VCC

Maximum efficiency (25%) is obtained when Vo VCC IRL

Class A output stage is rarely used in high-power applications
The efficiency achieved in practice is usually in the range of 10% to 20%

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13.3 CLASS B OUTPUT STAGE

Circuit Operation

Both transistors are cut off when vI is zero vO is zero

One of the transistor turns on as vI exceeds 0.5 V vO follows vI
The circuit operates in a push-pull fashion
The class B stage is biased at zero current and conducts only when
the input signal is present

Transfer Characteristic
There exists a range of input centered around zero
where both QN and QP are off
The transfer characteristic shows a dead band
which results in the crossover distortion at the output

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Power Conversion Efficiency

The average
load power by neglecting the cross-over distortion is

PL

1 Vo2
2 RL

The current drawn from each supply consists of half-sine waves of peak amplitude Vo / RL
The average power
drawn from each of the two power supply is

PS PS

1 Vo
VCC
RL

The total
supply power is
PS

2 Vo
VCC
RL

The
Th efficiency
ffi i
is
i given
i
by
b

Vo

4 VCC

Maximum efficiency is obtained when the output swing is maximized ( VCC):

78.5%

The maximum
average power available from a class B stage is

PL

1 Vo2
2 RL

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Power Dissipation
The quiescent power dissipation of the class B stage is zero (unlike class A)
The average power dissipation of the class B stage is given by PD = PS PL

2 Vo
1 Vo2
VCC
PD
RL
2 RL

QN and QP must be capable of safely dissipating half of PD

PD depends on the output swing and the worst-case power dissipation is given by

Vo

PD max

VCC PD max

2
2 VCC

RL

The maximum power dissipation of QN and QP occurs at = 50%:

PDN max PDP max

2
1 VCC

RL

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Reducing Crossover Distortion

The distortion can be reduced by employing a high-gain op amp and overall negative feedback
The 0.7V dead band is reduced by a factor of the dc gain of the op amp
The slew rate limitation of the op amp may cause the alternate turning on and off to be noticable

Single-Supply Operation
The class B stage can be operated from a single supply
The load is capacitivelu coupled
The derivations are directly applicable with supply of 2VCC

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13.4 CLASS AB OUTPUT STAGE

Circuit Operation
Cross-over distortion can be eliminated by biasing QN and QP at a small nonzero current
The bias current iN = iP = IQ = Isexp(VBB/2VT)
When vI goes positive by a certain amount:
vO vI VBB / 2 vBEN
vBEN vBEP VBB

VT ln

I
i
iN
VT ln P 2VT ln Q iN iP I Q2 iN2 iN iL I Q2 0
IS
IS
IS

The load current is supplied by QN which acts as the output emitter follower
QP will be conducting a current that decreases as vO increases (negligible for large vO)
QP acts as the output emitter follower when vI goes negative
The power properties are almost identical to those derived for the class B stage

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Output Resistance
The output resistance is estimated by assuming the source supply vI ideal
Rout reN || reP

VT VT
V
||
T
i N iP i N i P

The output resistance remains approximately constant in the region around vI = 0

The output resistance decreases at larger load currents

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13.5 BIASING THE CLASS AB CIRCUIT

Biasing Using Diodes
The bias voltage VBB is generated by passing a constant current IBIAS through a pair of diodes
The diodes need not to be large devices
Quiescent current IQ in QN and QP will be IQ = nIBIAS where n is the ratio of the areas of the emitter
junction of the BJT and the junction area of the diodes
IBN increases from IQ/N to IL/N for a positive vO
IBIAS has to be greater than the IBN for maximum IL case
The ratio n cannot be a large number as n = IQ/IBIAS
This biasing arrangement provides thermal stabilization of the quiescent current in the output stage
Collect current increases with temperature
p
for a fixed VBE
Heat from power dissipation increases with current
Positive feedback may cause thermal runaway
VBB decreases at the same rate of VBEN + VEBP
Thermal runaway is alleviated with close thermal contact

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Biasing Using the Voltage Multiplier

The class AB stage can be biased by VBE multiplier
I R VBE1 / R1
VBB VBE1 (1 R2 / R1 )

The value of VBE1 is determined by the portion of IBIAS that flows through the collector of Q1
I C1 I BIAS I R
I C1
I
VBE1 VT ln C1 VT ln
I BIAS I R
IS

The quiescent current can be adjusted by the resistance value

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13.6 CMOS CLASS AB OUTPUT STAGES

The Classical Configuration
Circuit operation

1
1

VGG VGS1 VSG 2 Vtn | Vtp | 2 I BIAS

k n (W / L)1

k p (W / L) 2

1
1

VGG VGSN VSGP Vtn | Vtp | 2 I Q

k n (W / L) n
p (W / L) p
k

1 / k (W / L) 1 / k p (W / L) 2
1
n
I Q I BIAS

1 / kn (W / L) n 1 / k p (W / L) p

For the case Q1 and Q2 are matched and QP and QN are matched:
I Q I BIAS

(W / L) n
(W / L)1

A drawback of the CMOS class AB circuit is the restricted range of output voltage swing
vO max VDD VOV |BIAS Vtn vOVN
vO min VSS VOV | I | Vtp | | vOVP |

where
vOVN is the overdrive voltage of QN when it is supplying iLmax
and
|vOVP| is the overdrive voltage of QP when sinking the maximum negative value of iL
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An Alternative Circuit Using Common-Source Transistors

The allowable output range can be increased by replacing the source followers with a pair of
complementary transistors in the common-source configuration
QP supplies the load current when vO is positive, allowing an output as high as VDD |vOVP|
QN sinks the load current when vO is negative, allowing an output as low as VSS + vOVN
The disadvantage is its high output resistance Rout = ron||rop
Negative feedback (error amplifiers) is employed to reduce the output resistance

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Output Resistance
The output resistance is derived by two half circuits: Rout Routn || Routp
The analysis techniques for feedback (shunt-series feedback) is utilized:
1 and A

vo
g mp ( rop || RL )
vi

The open-loop output resistance: Ro RL || rop

The output resistance with feedback: Rof Ro /(1 A) ( RL || rop ) /[1 g m ( RL || rop )]
The output resistance excluding RL: Routp 1 /(1 / Rof 1 / RL ) rop ||
Overall output resistance: Rout 1 / ( g mp g mn )

1
1

g mp g mp

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The Voltage Transfer Characteristics

1
2

2
For the case where QN and QP are matched: I Q kVOV

Drain currents: iDN

v v
I Q 1 O I
VOV

and

iDP

v v
I Q 1 O I
VOV

Load current: iL iDP iDN

Output voltage: vO vI /1

Gain error: vO vI

VOV
VOV
v I 1
4I R
4I Q RL
Q L

VOV
VOV

4I Q RL
2g m RL

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