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Atmel 2549 8 Bit AVR Microcontroller ATmega640 1280 1281 2560 2561 Datasheet
Atmel 2549 8 Bit AVR Microcontroller ATmega640 1280 1281 2560 2561 Datasheet
DATASHEET
Features
Peripheral Features
Temperature Range:
Speed Grade:
ATmega640V/ATmega1280V/ATmega1281V:
0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
ATmega2560V/ATmega2561V:
0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
ATmega640/ATmega1280/ATmega1281:
0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V
ATmega2560/ATmega2561:
0 - 16MHz @ 4.5V - 5.5V
2549QAVR02/2014
1. Pin Configurations
81
80
PA1 (AD1)
82
PA2 (AD2)
83
PJ7
84
PA0 (AD0)
85
GND
86
VCC
87
PK7 (ADC15/PCINT23)
88
PK5 (ADC13/PCINT21)
89
PK6 (ADC14/PCINT22)
90
PK3 (ADC11/PCINT19)
91
PK4 (ADC12/PCINT20)
92
PK1 (ADC9/PCINT17)
93
PK2 (ADC10/PCINT18)
PK0 (ADC8/PCINT16)
94
PF7 (ADC7/TDI)
95
PF6 (ADC6/TDO)
96
PF4 (ADC4/TCK)
97
PF5 (ADC5/TMS)
PF1 (ADC1)
98
PF2 (ADC2)
PF0 (ADC0)
100 99
PF3 (ADC3)
GND
AREF
TQFP-pinout ATmega640/1280/2560
AVCC
Figure 1-1.
79
78
77
76
(OC0B) PG5
75
PA3 (AD3)
(RXD0/PCINT8) PE0
74
PA4 (AD4)
INDEX CORNER
(TXD0) PE1
73
PA5 (AD5)
(XCK0/AIN0) PE2
72
PA6 (AD6)
(OC3A/AIN1) PE3
71
PA7 (AD7)
(OC3B/INT4) PE4
70
PG2 (ALE)
(OC3C/INT5) PE5
69
PJ6 (PCINT15)
(T3/INT6) PE6
68
PJ5 (PCINT14)
(CLKO/ICP3/INT7) PE7
67
PJ4 (PCINT13)
VCC
10
66
PJ3 (PCINT12)
GND
11
65
PJ2 (XCK3/PCINT11)
(RXD2) PH0
12
64
PJ1 (TXD3/PCINT10)
(TXD2) PH1
13
63
PJ0 (RXD3/PCINT9)
(XCK2) PH2
14
62
GND
(OC4A) PH3
15
61
VCC
(OC4B) PH4
16
60
PC7 (A15)
(OC4C) PH5
17
59
PC6 (A14)
(OC2B) PH6
18
58
PC5 (A13)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
(T1) PD6
31
(T0) PD7
30
(ICP1) PD4
29
(XCK1) PD5
28
(TXD1/INT3) PD3
27
(RXD1/INT2) PD2
26
(SDA/INT1) PD1
PG0 (WR)
PL7
51
(SCL/INT0) PD0
25
PL6
(OC1B/PCINT6) PB6
(OC5C) PL5
PG1 (RD)
(OC5A) PL3
PC0 (A8)
52
(OC5B) PL4
53
24
(T5) PL2
23
(OC1A/PCINT5) PB5
(ICP5) PL1
(OC2A/PCINT4) PB4
(ICP4) PL0
PC1 (A9)
XTAL2
PC2 (A10)
54
XTAL1
55
22
VCC
21
(MISO/PCINT3) PB3
GND
(MOSI/PCINT2) PB2
RESET
PC3 (A11)
(TOSC1) PG4
PC4 (A12)
56
(T4) PH7
57
20
(TOSC2) PG3
19
(OC0A/OC1C/PCINT7) PB7
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
Figure 1-2.
CBGA-pinout ATmega640/1280/2560
Top view
1
Bottom view
8
10
10
Table 1-1.
CBGA-pinout ATmega640/1280/2560
1
10
GND
AREF
PF0
PF2
PF5
PK0
PK3
PK6
GND
VCC
AVCC
PG5
PF1
PF3
PF6
PK1
PK4
PK7
PA0
PA2
PE2
PE0
PE1
PF4
PF7
PK2
PK5
PJ7
PA1
PA3
PE3
PE4
PE5
PE6
PH2
PA4
PA5
PA6
PA7
PG2
PE7
PH0
PH1
PH3
PH5
PJ6
PJ5
PJ4
PJ3
PJ2
VCC
PH4
PH6
PB0
PL4
PD1
PJ1
PJ0
PC7
GND
GND
PB1
PB2
PB5
PL2
PD0
PD5
PC5
PC6
VCC
PB3
PB4
RESET
PL1
PL3
PL7
PD4
PC4
PC3
PC2
PH7
PG3
PB6
PL0
XTAL2
PL6
PD3
PC1
PC0
PG1
PB7
PG4
VCC
GND
XTAL1
PL5
PD2
PD6
PD7
PG0
Note:
The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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(OC0B) PG5
(RXD0/PCINT8/PDI) PE0
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinout ATmega1281/2561
64
Figure 1-3.
INDEX CORNER
48
PA3 (AD3)
47
PA4 (AD4)
46
PA5 (AD5)
38
PC3 (A11)
12
37
PC2 (A10)
13
36
PC1 (A9)
14
35
PC0 (A8)
(OC1A/PCINT5) PB5
15
34
PG1 (RD)
(OC1B/PCINT6) PB6
16
33
PG0 (WR)
Note:
32
11
(T0) PD7
31
PC4 (A12)
(T1) PD6
39
30
10
(XCK1) PD5
(SS/PCINT0) PB0
29
PC5 (A13)
(ICP1) PD4
40
28
(TXD1/INT3) PD3
(ICP3/CLKO/INT7) PE7
27
PC6 (A14)
(RXD1/INT2) PD2
41
26
(SDA/INT1) PD1
(T3/INT6) PE6
25
PC7 (A15)
(SCL/INT0) PD0
42
24
XTAL1
(OC3C/INT5) PE5
23
PG2 (ALE)
XTAL2
43
22
GND
(OC3B/INT4) PE4
21
PA7 (AD7)
VCC
44
20
RESET
(OC3A/AIN1) PE3
19
PA6 (AD6)
(TOSC1) PG4
45
18
(TOSC2) PG3
(XCK0/AIN0) PE2
17
(OC0A/OC1C/PCINT7) PB7
(TXD0/PDO) PE1
The large center pad underneath the QFN/MLF package is made of metal and internally connected to GND. It should
be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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2. Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PF7..0
PK7..0
PORT F (8)
PORT K (8)
PJ7..0
PE7..0
VCC
Power
Supervision
POR/ BOD &
RESET
RESET
PORT J (8)
PORT E (8)
Watchdog
Timer
GND
Watchdog
Oscillator
Analog
Comparator
JTAG
A/D
Converter
EEPROM
Internal
Bandgap reference
USART 0
XTAL1
Oscillator
Circuits /
Clock
Generation
16 bit T/C 3
USART 3
16 bit T/C 5
XTAL2
CPU
PORT A (8)
PA7..0
16 bit T/C 4
USART 1
PG5..0
PORT G (6)
XRAM
PC7..0
PORT C (8)
TWI
FLASH
SPI
SRAM
16 bit T/C 1
8 bit T/C 0
USART 2
8 bit T/C 2
NOTE:
Shaded parts only available
in the 100-pin version.
Complete functionality for
the ADC, T/C4, and T/C5 only
available in the 100-pin version.
PORT D (8)
PORT B (8)
PORT H (8)
PORT L (8)
PD7..0
PB7..0
PH7..0
PL7..0
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in
one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
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The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8Kbytes SRAM, 54/86 general purpose
I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, four USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with
optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug
system and programming and six software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down
mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt
or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the
Asynchronous Timer continue to run.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression (AKS) technology for unambiguous
detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your
own touch applications.
The device is manufactured using the Atmel high-density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use
any interface to download the application program in the application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective
solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation
kits.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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2.2
2.3
2.3.1
Configuration Summary
Device
Flash
EEPROM
RAM
General
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
ATmega640
64KB
4KB
8KB
86
12
16
ATmega1280
128KB
4KB
8KB
86
12
16
ATmega1281
128KB
4KB
8KB
54
ATmega2560
256KB
4KB
8KB
86
12
16
ATmega2561
256KB
4KB
8KB
54
Pin Descriptions
VCC
Digital supply voltage.
2.3.2
GND
Ground.
2.3.3
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 75.
2.3.4
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 76.
2.3.5
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 79.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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2.3.6
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 80.
2.3.7
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 82.
2.3.8
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not
running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be
activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9
Port G (PG5..PG0)
Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on
page 86.
2.3.10
Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 88.
2.3.11
Port J (PJ7..PJ0)
Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a
reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special
features of the ATmega640/1280/2560 as listed on page 90.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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2.3.12
Port K (PK7..PK0)
Port K serves as analog inputs to the A/D Converter.
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port K also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92.
2.3.13
Port L (PL7..PL0)
Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 94.
2.3.14
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in System and Reset Characteristics on page 360. Shorter
pulses are not guaranteed to generate a reset.
2.3.15
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.16
XTAL2
Output from the inverting Oscillator amplifier.
2.3.17
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.3.18
AREF
This is the analog reference pin for the A/D Converter.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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3. Resources
A comprehensive set of development tools and application notes, and datasheets are available for download on
http://www.atmel.com/avr.
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20
years at 85C or 100 years at 25C.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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10
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Architectural Overview
Figure 7-1.
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registers
Instruction
Register
Control Lines
Indirect Addressing
Instruction
Decoder
Direct Addressing
7.2
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper-
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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11
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.3
7.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Summary on page 404. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact
code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
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7.4.1
0x3F (0x5F)
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SREG
7.5
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Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2.
Addr.
R0
0x00
R1
0x01
R2
0x02
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
R26
0x1A
R27
0x1B
R28
0x1C
R29
0x1D
R30
0x1E
R31
0x1F
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
7.5.1
X-register
XH
XL
0
R27 (0x1B)
15
Y-register
YH
YL
0
R28 (0x1C)
15
ZH
R31 (0x1F)
R26 (0x1A)
R29 (0x1D)
Z-register
ZL
7
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Summary on page 404 for details).
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7.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the
Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This
Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is the
last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two for ATmega640/1280/1281 and three for
ATmega2560/2561 when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack
Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented
by two for ATmega640/1280/1281 and three for ATmega2560/2561 when data is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
Bit
15
14
13
12
11
10
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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7.6.1
0x3B (0x5B)
RAMPZ7
RAMPZ6
RAMPZ5
RAMPZ4
RAMPZ3
RAMPZ2
RAMPZ1
RAMPZ0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note
that LPM is not affected by the RAMPZ setting.
Figure 7-4.
Bit
(Individually)
Bit (Z-pointer)
23
16
15
RAMPZ
ZH
ZL
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.
For compatibility with future devices, be sure to write these bits to zero.
7.6.2
EIND7
EIND6
EIND5
EIND4
EIND3
EIND2
EIND1
EIND0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x3C (0x5C)
EIND
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and
ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting.
Figure 7-5.
Bit
(Individually)
Bit (Indirectpointer)
23
16
15
EIND
ZH
0
ZL
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.
For compatibility with future devices, be sure to write these bits to zero.
7.7
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Figure 7-6.
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-7.
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
7.8
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flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
cli
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
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7.8.1
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8. AVR Memories
This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has
two main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All three memory spaces are
linear and regular.
8.1
8.2
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When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal
data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM.
This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If
the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra
because the three-byte program counter is pushed and popped, and external memory access does not take
advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, onebyte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the
instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the
indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y-register
or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of internal data SRAM in the
ATmega640/1280/1281/2560/2561 are all accessible through all these addressing modes. The Register File is
described in General Purpose Register File on page 13.
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Figure 8-2.
32 Registers
20 - 5F
64 I/O Registers
60 - 1FF
200
Internal SRAM
(8192 8)
21FF
2200
External SRAM
(0 - 64K 8)
FFFF
8.2.1
T2
T3
clkCPU
Address
Compute Address
Address valid
Write
Data
WR
Read
Data
RD
8.3
Next Instruction
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8.3.1
Symbol
EEPROM write (from CPU)
26,368
3.3ms
The following code examples show one assembly and one C function for writing to the EEPROM. The examples
assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur
during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
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C Code Example(1)
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
Note:
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that
interrupts are controlled so that no interrupts will occur during execution of these functions.
Assembly Code Example(1)
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjcmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in
r16,EEDR
ret
C Code Example(1)
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
Note:
8.3.2
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8.4
I/O Memory
The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in Register Summary on page 399.
All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose
working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS
and SBIC instructions. Refer to the Instruction Set Summary on page 404 for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as
data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
8.4.1
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9.1
Overview
When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available
using the dedicated External Memory pins (see Figure 1-3 on page 4, Table 13-3 on page 75, Table 13-9 on page
79, and Table 13-21 on page 86). The memory configuration is shown in Figure 9-1.
Figure 9-1.
Internal memory
0x21FF
0x2200
Lower sector
SRW01
SRW00
SRL[2..0]
External Memory
(0 - 60K x 8)
Upper sector
SRW11
SRW10
0xFFFF
9.1.1
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The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A XMCRA, and the External Memory Control Register B XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers
that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section I/O-Ports on page 67. The XMEM interface will auto-detect whether an access is internal
or external. If the access is external, the XMEM interface will output address, data, and the control signals on the
ports according to Figure 9-3 on page 29 (this figure shows the wave forms without wait-states). When ALE goes
from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is
enabled, also an internal access will cause activity on address, data and ALE ports, but the RD and WR strobes
will not toggle during internal access. When the External Memory Interface is disabled, the normal pin and data
direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal
SRAM boundary is not mapped into the internal SRAM. Figure 9-2 illustrates how to connect an external SRAM to
the AVR using an octal latch (typically 74 573 or equivalent) which is transparent when G is high.
9.1.2
The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of th =
5ns. Refer to tLAXX_LD/tLLAXX_ST in External Data Memory Timing Tables 31-11 through Tables 31-18 on pages 367
- 370. The D-to-Q propagation delay (tPD) must be taken into consideration when calculating the access time
requirement of the external component. The data setup time before G low (tSU) must not exceed address valid to
ALE low (tAVLLC) minus PCB wiring delay (dependent on the capacitive load).
Figure 9-2.
AVR
SRAM
D[7:0]
AD7:0
ALE
A15:8
RD
WR
A[7:0]
A[15:8]
RD
WR
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9.1.3
T2
T3
T4
ALE
A15:8
Prev. addr.
DA7:0
Prev. data
Address
DA7:0 (XMBK = 0)
Prev. data
Address
DA7:0 (XMBK = 1)
Prev. data
Address
Address
Data
Write
XX
WR
Data
XXXXX
Data
XXXXXXXX
Read
9.1.4
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).
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Figure 9-4.
T2
T3
T4
T5
ALE
A15:8
Prev. addr.
DA7:0
Prev. data
Address
DA7:0 (XMBK = 0)
Prev. data
Address
DA7:0 (XMBK = 1)
Prev. data
Address
Data
Write
XX
WR
Address
Read
Data
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).
Figure 9-5.
T2
T3
T4
T5
T6
ALE
A15:8
Prev. addr.
DA7:0
Prev. data
Address
DA7:0 (XMBK = 0)
Prev. data
Address
DA7:0 (XMBK = 1)
Prev. data
XX
Data
Write
Address
WR
Data
Read
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).
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Figure 9-6.
T2
T3
T4
T5
T6
T7
ALE
A15:8
Prev. addr.
DA7:0
Prev. data
Address
DA7:0 (XMBK = 0)
Prev. data
Address
DA7:0 (XMBK = 1)
Prev. data
XX
Write
Address
Data
WR
Address
Read
Data
Data
RD
Note:
9.1.5
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).
0x0000
0x0000
Internal Memory
0x21FF
0x2200
0x7FFF
0x8000
External
0x7FFF
Memory
0x90FF
0x9100
(Do Not Use)
0xFFFF
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9.1.6
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C Code Example(1)
#define OFFSET 0x4000
void XRAM_example(void)
{
unsigned char *p = (unsigned char *) (OFFSET + 1);
DDRC = 0xFF;
PORTC = 0x00;
XMCRB = (1<<XMM1);
*p = 0xaa;
XMCRB = 0x00;
*p = 0x55;
}
Note:
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9.2
9.2.1
Register Description
EEPROM registers
9.2.1.1
15
14
13
12
11
10
0x22 (0x42)
EEAR11
EEAR10
EEAR9
EEAR8
EEARH
0x21 (0x41)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x20 (0x40)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
EEDR
0x1F (0x3F)
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
EECR
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Table 9-1.
EEPM1
EEPM0
Programming Time
Operation
3.4ms
1.8ms
Erase only
1.8ms
Write only
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The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
9.3
9.3.1
9.3.2
9.4.1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
LSB
GPIOR2
0x2A (0x4A)
MSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
LSB
GPIOR1
Bit
9.4
MSB
Bit
9.3.3
0x2B (0x4B)
0x1E (0x3E)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
GPIOR0
(0x74)
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XMCRA
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Table 9-2.
SRL2
SRL1
SRL0
Sector Limits
Bit 3:2 SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory
address space, see Table 9-3.
Bit 1:0 SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the external memory address
space, see Table 9-3.
Table 9-3.
Wait States(1)
SRWn1
SRWn0
Wait States
No wait-states
Wait two cycles during read/write and wait one cycle before driving out new address
Note:
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figure 9-3 on page 29
through Figure 9-6 on page 31 for how the setting of the SRW bits affects the timing.
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9.4.2
XMBK
XMM2
XMM1
XMM0
Read/Write
R/W
R/W
R/W
R/W
Initial Value
(0x75)
XMCRB
Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMM2
XMM1
XMM0
None
PC7
PC7 - PC6
PC7 - PC5
PC7 - PC4
PC7 - PC3
PC7 - PC2
Full Port C
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10.1
Overview
Figure 10-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted
by using different sleep modes, as described in Power Management and Sleep Modes on page 50. The clock
systems are detailed below.
Figure 10-1. Clock Distribution.
Asynchronous
Timer/Counter
General I/O
Modules
ADC
CPU Core
RAM
Flash and
EEPROM
clkADC
clkI/O
AVR Clock
Control Unit
clkASY
clkCPU
clkFLASH
Reset Logic
Source clock
System Clock
Prescaler
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Clock
Multiplexer
Timer/Counter
Oscillator
10.2
10.2.1
Crystal
Oscillator
External Clock
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
10.2.2
39
10.2.3
10.2.4
10.2.5
10.3
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from
the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Table 10-1.
Note:
10.3.1
CKSEL3:0
1111 - 1000
0111 - 0110
0101 - 0100
0011
0010
External Clock
0000
Reserved
0001
10.3.2
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Table 10-2.
Number of Cycles
0ms
0ms
4.1ms
4.3ms
512
65ms
69ms
8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an
internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient VCC before it
releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a BrownOut Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An
internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of
clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up
time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low
frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts
up from reset. When starting up from Power-save or Power-down mode, VCC is assumed to be at a sufficient level
and only the start-up time is included.
10.4
C2
C1
XTAL2
XTAL1
GND
The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The
operating mode is selected by the fuses CKSEL3:1 as shown in Table 10-3 on page 42.
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Table 10-3.
CKSEL3:1(1)
0.4 - 0.9
100
0.9 - 3.0
101
12 - 22
3.0 - 8.0
110
12 - 22
111
12 - 22
(4)
8.0 - 16.0
Notes:
(2)
1. This is the recommended CKSEL settings for the different frequency ranges.
2. This option should not be used with crystals, only with ceramic resonators.
3. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets
the frequency specification of the device.
4. Maximum frequency when using ceramic oscillator is 10MHz.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in Table 10-4.
Table 10-4.
Start-up Times for the Low Power Crystal Oscillator Clock Selection
258CK
258CK
Additional Delay
from Reset
(VCC = 5.0V)
CKSEL0
SUT1:0
(1)
00
(1)
01
10
14CK + 4.1ms
14CK + 65ms
14CK
(2)
1KCK
1KCK
14CK + 4.1ms(2)
11
1KCK
(2)
00
16KCK
14CK
01
16KCK
14CK + 4.1ms
10
16KCK
14CK + 65ms
11
Notes:
10.5
14CK + 65ms
1. These options should only be used when not operating close to the maximum frequency of the device, and only if
frequency stability at start-up is not important for the application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can
also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
42
Table 10-5.
CKSEL3:1
0.4 - 16
011
12 - 22
Note:
1. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets
the frequency specification of the device.
Table 10-6.
Start-up Times for the Full Swing Crystal Oscillator Clock Selection
CKSEL0
SUT1:0
Ceramic resonator,
fast rising power
258 CK
14CK + 4.1ms(1)
00
Ceramic resonator,
slowly rising power
258 CK
14CK + 65ms(1)
01
Ceramic resonator,
BOD enabled
1K CK
14CK(2)
10
Ceramic resonator,
fast rising power
1K CK
14CK + 4.1ms(2)
11
Ceramic resonator,
slowly rising power
1K CK
14CK + 65ms(2)
00
Crystal Oscillator,
BOD enabled
16K CK
14CK
01
Crystal Oscillator,
fast rising power
16K CK
14CK + 4.1ms
10
Crystal Oscillator,
slowly rising power
16K CK
14CK + 65ms
11
Notes:
10.6
1. These options should only be used when not operating close to the maximum frequency of the device, and only if
frequency stability at start-up is not important for the application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can
also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
Device
32kHz oscillator
Cap (Xtal1/Tosc1)
Cap (Xtal2/Tosc2)
ATmega640/1280/1281/2560/2561
System Osc.
18pF
8pF
Timer Osc.
6pF
6pF
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The capacitance (Ce + Ci) needed at each XTAL/TOSC pin can be calculated by using:
Ce + Ci = 2 * CL - Cs
where:
Ce - is optional external capacitors as described in Figure 10-3.
Ci - is the pin capacitance in Table 10-7 on page 43.
CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor.
CS - is the total stray capacitance for one XTAL/TOSC pin.
Crystals specifying load capacitance (CL) higher than the ones given in the Table 10-7 on page 43, require external capacitors applied as described in Figure 10-3.
Figure 10-3. Crystal Oscillator Connections
TOSC2
Ce
Cs
Ci
X1
TOSC1
Ce
Cs
Ci
To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet.
When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in Table
10-8.
Table 10-8.
Start-up times for the low frequency crystal oscillator clock selection
Power Conditions
CKSEL0
SUT1:0
BOD enabled
1K CK
14CK(1)
1K CK
00
(1)
01
(1)
10
11
14CK + 4.1ms
1K CK
14CK + 65ms
Reserved
BOD enabled
32K CK
14CK
00
32K CK
14CK + 4.1ms
01
32K CK
14CK + 65ms
10
11
Reserved
Note:
1. These options should only be used if frequency stability at start-up is not important for the application.
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10.7
Notes:
CKSEL3:0
7.3 - 8.1
0010
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10-10.
Table 10-10. Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions
SUT1:0
BOD enabled
6CK
14CK
00
6CK
14CK + 4.1ms
6CK
14CK + 65ms
01
(1)
10
Reserved
Note:
10.8
11
Note:
Nominal Frequency
CKSEL3:0
128kHz
0011
1. Note that the 128kHz oscillator is a very low power clock source, and is not designed for high accuracy.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-12 on
page 46.
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SUT1:0
BOD enabled
6CK
14CK
00
6CK
14CK + 4ms
01
6CK
14CK + 64ms
10
Reserved
10.9
11
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 10-4. To run the
device on an external clock, the CKSEL Fuses must be programmed to 0000.
Figure 10-4. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
CLOCK
SIGNAL
XTAL1
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10-15 on
page 49.
Table 10-13. Crystal Oscillator Clock Frequency
Nominal Frequency
CKSEL3:0
0 - 16MHz
0000
SUT1:0
BOD enabled
6CK
14CK
00
6CK
14CK + 4.1ms
01
6CK
14CK + 65ms
10
Reserved
11
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the
changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation. Refer to System Clock Prescaler on page 47 for details.
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CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OSCCAL
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x61)
CLKPR
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CLKPS2
CLKPS1
CLKPS0
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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11.1
Sleep Modes
Figure 10-1 on page 39 presents the different clock systems in the ATmega640/1280/1281/2560/2561, and their
distribution. The figure is helpful in selecting an appropriate sleep mode. Table 11-1 shows the different sleep
modes and their wake-up sources.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Idle
ADCNRM
X
X
X
X
Power-down
Power-save
Standby
(1)
Extended Standby
Note:
X(2)
X
X
X
(2)
(3)
X(3)
(3)
(3)
X
(2)
X
(2)
Other I/O
(3)
WDT Interrupt
(2)
ADC
X(2)
Sleep Mode
SPM/
EEPROM Ready
TWI Address
Match
Timer2
INT7:0 and
Pin Change
Wake-up Sources
Timer Osc
Enabled
Oscillators
clkASY
clkADC
clkIO
clkFLASH
clkCPU
Main Clock
Source
Enabled
Table 11-1.
X
X
X
X
To enter any of the sleep modes, the SE bit in SMCR Sleep Mode Control Register on page 54 must be written
to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode will be activated by the SLEEP instruction. See Table 11-2 on page 54 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
11.2
Idle Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU
but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and
the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the
other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control
and Status Register ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
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11.3
11.4
Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial
Interface address match, an external level interrupt on INT7:4, an external interrupt on INT3:0, or a pin change
interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
for some time to wake up the MCU. Refer to External Interrupts on page 109 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in Clock
Sources on page 40.
11.5
Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow
or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the Global Interrupt Enable bit in SREG is set. If Timer/Counter2 is not running, Power-down mode is
recommended instead of Power-save mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If the
Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the
Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the
synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2.
11.6
Standby Mode
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is
kept running. From Standby mode, the device wakes up in six clock cycles.
11.7
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11.8
Resources used by the peripherals (for example I/O pin, etc.) will remain occupied
The peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by
cleaning the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in
Idle mode or Active mode to significantly reduce the overall power consumption. See Power-down Supply Current on page 380 for examples. In all other sleep modes, the clock is already stopped.
11.9
11.9.1
11.9.2
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is
automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will
be enabled, independent of sleep mode. Refer to AC Analog Comparator on page 265 for details on how to
configure the Analog Comparator.
11.9.3
Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out
Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to
Brown-out Detection on page 59 for details on how to configure the Brown-out Detector.
11.9.4
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11.9.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to Interrupts on page 101 for details on how to
configure the Watchdog Timer.
11.9.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock
(clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it
will then be enabled. Refer to the section Digital Input Enable and Sleep Modes on page 71 for details on which
pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level
close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Registers (DIDR2, DIDR1 and DIDR0). Refer to DIDR2 Digital Input Disable Register 2
on page 288, DIDR1 Digital Input Disable Register 1 on page 267, and DIDR0 Digital Input Disable Register
0 on page 287 for details.
11.9.7
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0x33 (0x53)
SM2
SM1
SM0
SE
Read/Write
R/W
R/W
R/W
R/W
Initial Value
SMCR
Note:
SM2
SM1
SM0
Sleep Mode
Idle
Power-down
Power-save
Reserved
Reserved
Standby(1)
Extended Standby(1)
1. Standby modes are only recommended for use with external crystals or resonators.
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11.10.2
PRTWI
PRTIM2
PRTIM0
PRTIM1
PRSPI
PRUSART0
PRADC
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x64)
PRR0
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11.10.3
(0x65)
PRTIM5
PRTIM4
PRTIM3
PRUSART3
PRUSART2
PRUSART1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PRR1
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12.2
Reset Sources
The ATmega640/1280/1281/2560/2561 has five sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT)
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled
Brown-out Reset. The MCU is reset when the supply voltage AVCC is below the Brown-out Reset threshold
(VBOT) and the Brown-out Detector is enabled
JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan
chains of the JTAG system. Refer to the section IEEE 1149.1 (JTAG) Boundary-scan on page 295 for details
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AVCC
PORF
BORF
EXTRF
WDRF
JTRF
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Power-on Reset
Circuit
Pull-up Resistor
SPIKE
FILTER
JTAG Reset
Register
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
12.2.1
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in System and Reset Characteristics on page 360. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise.
The RESET signal is activated again, without any delay, when VCC decreases below the detection level.
Figure 12-2. MCU Start-up, RESET Tied to VCC
VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
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VPOT
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
12.2.2
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse
width (see System and Reset Characteristics on page 360) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage VRST on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired.
Figure 12-4. External Reset During Operation
CC
12.2.3
Brown-out Detection
ATmega640/1280/1281/2560/2561 has an On-chip Brown-out Detection (BOD) circuit for monitoring the AVCC level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the
detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
When the BOD is enabled, and AVCC decreases to a value below the trigger level (VBOT- in Figure 12-5 on page
60), the Brown-out Reset is immediately activated. When AVCC increases above the trigger level (VBOT+ in Figure
12-5 on page 60), the delay counter starts the MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in AVCC if the voltage stays below the trigger level for longer than tBOD given
in System and Reset Characteristics on page 360.
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VBOT-
VBOT+
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
12.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of
this pulse, the delay timer starts counting the Time-out period tTOUT. See Watchdog Timer on page 53. for details
on operation of the Watchdog Timer.
Figure 12-6. Watchdog Reset During Operation
CC
CK
12.3
12.3.1
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12.4
12.4.1
Watchdog Timer
Features
Clocked from separate On-chip Oscillator
Three Operating modes
Interrupt
System Reset
Interrupt and System Reset
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
128kHz
OSCILLATOR
WATCHDOG
RESET
WDE
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WDP1
WDP2
WDP3
MCU RESET
WDIF
WDIE
12.4.2
INTERRUPT
Overview
ATmega640/1280/1281/2560/2561 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles
of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer
Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the
counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the
device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed
for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode,
the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway
code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt
and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode.
With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0
respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences.
The sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one
must be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with
the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The
example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts
will occur during the execution of these functions.
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r16, MCUSR
andi
out
MCUSR, r16
r16, (0<<WDE)
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out
*/
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note:
1. The example code assumes that the part specific header file is included.
2. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be
reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to
an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in
use.
The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
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r16, WDTCSR
ori
out
WDTCSR, r16
; --
out
WDTCSR, r16
; --
C Code Example(2)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed
equence */
__enable_interrupt();
}
Notes:
1. The example code assumes that the part specific header file is included.
2. The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can
result in a time-out when switching to a shorter time-out period.
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12.5
12.5.1
Register Description
MCUSR MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
0x35 (0x55)
JTRF
WDRF
BORF
EXTRF
PORF
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUSR
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12.5.2
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x60)
WDTCSR
WDTON
Note:
WDIE
Mode
Action on Time-out
Stopped
None
Interrupt Mode
Interrupt
Reset
Reset
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Table 12-2.
WDP3
WDP2
WDP1
WDP0
2K (2048) cycles
16ms
4K (4096) cycles
32ms
8K (8192) cycles
64ms
0.125s
0.25s
0.5s
1.0s
2.0s
4.0s
8.0s
Reserved
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13. I/O-Ports
13.1
Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with
both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection
diodes to both VCC and Ground as indicated in Figure 13-1. Refer to Electrical Characteristics on page 355 for a
complete list of parameters.
Figure 13-1. I/O Pin Equivalent Schematic
Rpu
Logic
Pxn
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case x represents the numbering letter for the port, and a lower case n represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in Table 13-34 and Table 1335 relates the alternate functions of Port L to the overriding signals shown in Figure 13-5 on page 73. on page 95.
Three I/O memory address locations are allocated for each port, one each for the Data Register PORTx, Data
Direction Register DDRx, and the Port Input Pins PINx. The Port Input Pins I/O location is read only, while the
Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable PUD bit
in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in Ports as General Digital I/O on page 68. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Alternate Port Functions on page 72. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
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13.2
PUD
DDxn
Q CLR
WDx
RESET
DATA BUS
RDx
1
Q
Pxn
PORTxn
Q CLR
RESET
WRx
SLEEP
WPx
RRx
SYNCHRONIZER
D
RPx
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
13.2.1
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports.
13.2.2
68
13.2.3
PUD
(in MCUCR)
DDxn
13.2.4
Table 13-1.
I/O
Pull-up
Comment
Input
No
Tri-state (Hi-Z)
Input
Yes
Input
No
Tri-state (Hi-Z)
Output
No
Output
No
SYSTEM CLK
INSTRUCTIONS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd, max
t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the SYNC
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LATCH signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4.
The out instruction sets the SYNC LATCH signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is one system clock period.
Figure 13-4. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd
The following code example shows how to set port B pins 0 and 1 high, pins 2 and 3 low, and define the port pins
from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as
previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of
the pins.
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r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Note:
13.2.5
1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0,
1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong
high drivers.
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13.2.6
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle
mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the
pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use
an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this
may cause excessive currents if the pin is accidentally configured as an output.
13.3
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PUD
DDOExn
DDOVxn
1
D
Q
DDxn
Q CLR
WDx
PVOExn
RESET
RDx
DATA BUS
PVOVxn
Pxn
Q
PORTxn
PTOExn
Q CLR
DIEOExn
WPx
DIEOVxn
RESET
WRx
1
0
RRx
SLEEP
SYNCHRONIZER
D SET Q
RPx
PINxn
L CLR Q
CLR
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Note:
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports. All other signals are unique for each pin.
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Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 13-5 on page
73 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having
the alternate function.
Table 13-2.
Signal Name
Full Name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the PUOV signal. If this
signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} =
0b010.
PUOV
DDOE
If this signal is set, the Output Driver Enable is controlled by the DDOV
signal. If this signal is cleared, the Output driver is enabled by the DDxn
Register bit.
DDOV
PVOE
If this signal is set and the Output Driver is enabled, the port value is
controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is
enabled, the port Value is controlled by the PORTxn Register bit.
PVOV
If PVOE is set, the port value is set to PVOV, regardless of the setting of the
PORTxn Register bit.
PTOE
DIEOE
If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If
this signal is cleared, the Digital Input Enable is determined by MCU state
(Normal mode, sleep mode).
DIEOV
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the signal is
connected to the output of the schmitt trigger but before the synchronizer.
Unless the Digital Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
AIO
Analog Input/Output
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to
the alternate function. Refer to the alternate function description for further details.
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13.3.1
Port Pin
Alternate Function
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Table 13-4 and Table 13-5 on page 76 relates the alternate functions of Port A to the overriding signals shown in
Figure 13-5 on page 73.
Table 13-4.
Signal Name
PA7/AD7
PA6/AD6
PA5/AD5
PA4/AD4
PUOE
SRE
SRE
SRE
SRE
(1)
PUOV
~(WR | ADA )
PORTA7 PUD
DDOE
SRE
SRE
SRE
SRE
DDOV
WR | ADA
WR | ADA
WR | ADA
WR | ADA
PVOE
SRE
SRE
SRE
SRE
PVOV
A7 ADA | D7 OUTPUT
WR
A6 ADA | D6 OUTPUT
WR
A5 ADA | D5 OUTPUT
WR
A4 ADA | D4 OUTPUT
WR
DIEOE
DIEOV
DI
D7 INPUT
D6 INPUT
D5 INPUT
D4 INPUT
AIO
Note:
1. ADA is short for ADdress Active and represents the time when address is output. See External Memory Interface
on page 27 for details.
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Table 13-5.
13.3.2
Signal Name
PA3/AD3
PA2/AD2
PA1/AD1
PA0/AD0
PUOE
SRE
SRE
SRE
SRE
PUOV
DDOE
SRE
SRE
SRE
SRE
DDOV
WR | ADA
WR | ADA
WR | ADA
WR | ADA
PVOE
SRE
SRE
SRE
SRE
PVOV
A3 ADA | D3 OUTPUT
WR
A2 ADA | D2 OUTPUT
WR
A1 ADA | D1 OUTPUT
WR
A0 ADA | D0 OUTPUT
WR
DIEOE
DIEOV
DI
D3 INPUT
D2 INPUT
D1 INPUT
D0 INPUT
AIO
Port Pin
Alternate Functions
PB7
OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and
PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)
PB6
OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6)
PB5
OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt 5)
PB4
OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt 4)
PB3
PB2
PB1
PB0
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OC1B/PCINT6, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is
also the output pin for the PWM mode timer function.
PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.
OC1A/PCINT5, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is
also the output pin for the PWM mode timer function.
PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt source.
OC2A/PCINT4, Bit 4
OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter2 Output
Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC2A pin is also
the output pin for the PWM mode timer function.
PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source.
MISO/PCINT3 Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is
configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of
this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source.
MOSI/PCINT2 Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is
configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction
of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source.
SCK/PCINT1 Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is
configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction
of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.
SS/PCINT0 Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the
setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master,
the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be
controlled by the PORTB0 bit.
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Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on
page 73. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI
MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 13-7.
Signal Name
PB7/OC0A/OC1C
PB6/OC1B
PB5/OC1A
PB4/OC2A
PUOE
PUOV
DDOE
DDOV
PVOE
OC0/OC1C ENABLE
OC1B ENABLE
OC1A ENABLE
OC2A ENABLE
PVOV
OC0/OC1C
OC1B
OC1A
OC2A
DIEOE
PCINT7 PCIE0
PCINT6 PCIE0
PCINT5 PCIE0
PCINT4 PCIE0
DIEOV
DI
PCINT7 INPUT
PCINT6 INPUT
PCINT5 INPUT
PCINT4 INPUT
AIO
Table 13-8.
Signal Name
PB3/MISO
PB2/MOSI
PB1/SCK
PB0/SS
PUOE
SPE MSTR
SPE MSTR
SPE MSTR
SPE MSTR
PUOV
PORTB3 PUD
PORTB2 PUD
PORTB1 PUD
PORTB0 PUD
DDOE
SPE MSTR
SPE MSTR
SPE MSTR
SPE MSTR
DDOV
PVOE
SPE MSTR
SPE MSTR
SPE MSTR
PVOV
SCK OUTPUT
DIEOE
PCINT3 PCIE0
PCINT2 PCIE0
PCINT1 PCIE0
PCINT0 PCIE0
DIEOV
DI
SCK INPUT
PCINT1 INPUT
SPI SS
PCINT0 INPUT
AIO
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13.3.3
Port Pin
Alternate Function
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Table 13-10 and Table 13-11 on page 80 relate the alternate functions of Port C to the overriding signals shown in
Figure 13-5 on page 73.
Table 13-10. Overriding Signals for Alternate Functions in PC7:PC4
Signal Name
PC7/A15
PC6/A14
PC5/A13
PC4/A12
PUOE
SRE (XMM<1)
SRE (XMM<2)
SRE (XMM<3)
SRE (XMM<4)
PUOV
DDOE
SRE (XMM<1)
SRE (XMM<2)
SRE (XMM<3)
SRE (XMM<4)
DDOV
PVOE
SRE (XMM<1)
SRE (XMM<2)
SRE (XMM<3)
SRE (XMM<4)
PVOV
A15
A14
A13
A12
DIEOE
DIEOV
DI
AIO
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13.3.4
Signal
Name
PC3/A11
PC2/A10
PC1/A9
PC0/A8
PUOE
SRE (XMM<5)
SRE (XMM<6)
SRE (XMM<7)
SRE (XMM<7)
PUOV
DDOE
SRE (XMM<5)
SRE (XMM<6)
SRE (XMM<7)
SRE (XMM<7)
DDOV
PVOE
SRE (XMM<5)
SRE (XMM<6)
SRE (XMM<7)
SRE (XMM<7)
PVOV
A11
A10
A9
A8
DIEOE
DIEOV
DI
AIO
Alternate Function
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
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PD7/T0
PD6/T1
PD5/XCK1
PD4/ICP1
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
XCK1 OUTPUT
DIEOE
DIEOV
DI
T0 INPUT
T1 INPUT
XCK1 INPUT
ICP1 INPUT
AIO
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PD3/INT3/TXD1
PD2/INT2/RXD1
PD1/INT1/SDA
PD0/INT0/SCL
PUOE
TXEN1
RXEN1
TWEN
TWEN
PUOV
PORTD2 PUD
PORTD1 PUD
PORTD0 PUD
DDOE
TXEN1
RXEN1
TWEN
TWEN
DDOV
SDA_OUT
SCL_OUT
PVOE
TXEN1
TWEN
TWEN
PVOV
TXD1
DIEOE
INT3 ENABLE
INT2 ENABLE
INT1 ENABLE
INT0 ENABLE
DIEOV
DI
INT3 INPUT
INT2 INPUT/RXD1
INT1 INPUT
INT0 INPUT
AIO
SDA INPUT
SCL INPUT
Note:
13.3.5
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not
shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and
the digital logic of the TWI module.
Alternate Function
PE7
INT7/ICP3/CLK0
(External Interrupt 7 Input, Timer/Counter3 Input Capture Trigger or Divided System Clock)
PE6
INT6/ T3
(External Interrupt 6 Input or Timer/Counter3 Clock Input)
PE5
INT5/OC3C
(External Interrupt 5 Input or Output Compare and PWM Output C for Timer/Counter3)
PE4
INT4/OC3B
(External Interrupt4 Input or Output Compare and PWM Output B for Timer/Counter3)
PE3
AIN1/OC3A
(Analog Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3)
PE2
AIN0/XCK0
(Analog Comparator Positive Input or USART0 external clock input/output)
PE1
PDO(1)/TXD0
(Programming Data Output or USART0 Transmit Pin)
PE0
PDI(1)/RXD0/PCINT8
(Programming Data Input, USART0 Receive Pin or Pin Change Interrupt 8)
Note:
1. Only for ATmega1281/2561. For ATmega640/1280/2560 these functions are placed on MISO/MOSI pins.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
82
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
83
PE7/INT7/ICP3
PE6/INT6/T3
PE5/INT5/OC3C
PE4/INT4/OC3B
PUOE
PUOV
DDOE
DDOV
PVOE
OC3C ENABLE
OC3B ENABLE
PVOV
OC3C
OC3B
DIEOE
INT7 ENABLE
INT6 ENABLE
INT5 ENABLE
INT4 ENABLE
DIEOV
DI
INT7 INPUT/ICP3
INPUT
INT5 INPUT
INT4 INPUT
AIO
PE3/AIN1/OC3A
PE2/AIN0/XCK0
PE1/PDO(1)/TXD0
PE0/PDI(1)/RXD0/PCINT8
PUOE
TXEN0
RXEN0
PUOV
PORTE0 PUD
DDOE
XCK0 OUTPUT
ENABLE
TXEN0
RXEN0
DDOV
PVOE
OC3B ENABLE
XCK0 OUTPUT
ENABLE
TXEN0
PVOV
OC3B
XCK0 OUTPUT
TXD0
DIEOE
PCINT8 PCIE1
DIEOV
DI
XCK0 INPUT
RXD0
PE0
PCINT8 INPUT
Note:
AIO
AIN1 INPUT
AIN0 INPUT
1. PDO/PDI only available at PE1/PE0 for ATmega1281/2561.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
84
13.3.6
Alternate Function
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
85
PF7/ADC7/TDI
PF6/ADC6/TDO
PF5/ADC5/TMS
PF4/ADC4/TCK
PUOE
JTAGEN
JTAGEN
JTAGEN
JTAGEN
PUOV
DDOE
JTAGEN
JTAGEN
JTAGEN
JTAGEN
DDOV
SHIFT_IR + SHIFT_DR
PVOE
JTAGEN
PVOV
TDO
DIEOE
JTAGEN
JTAGEN
JTAGEN
JTAGEN
DIEOV
DI
AIO
TDI/ADC7 INPUT
ADC6 INPUT
TMS/ADC5 INPUT
TCK/ADC4 INPUT
13.3.7
Signal Name
PF3/ADC3
PF2/ADC2
PF1/ADC1
PF0/ADC0
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
Alternate Function
PG5
PG4
PG3
PG2
PG1
PG0
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
86
PG5/OC0B
PG4/TOSC1
PUOE
AS2
PUOV
DDOE
AS2
DDOV
PVOE
OC0B Enable
PVOV
OC0B
PTOE
DIEOE
AS2
DIEOV
EXCLK
DI
AIO
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
87
13.3.8
Signal Name
PG3/TOSC2
PG2/ALE/A7
PG1/RD
PG0/WR
PUOE
AS2 EXCLK
SRE
SRE
SRE
PUOV
DDOE
AS2 EXCLK
SRE
SRE
SRE
DDOV
PVOE
SRE
SRE
SRE
PVOV
ALE
RD
WR
PTOE
DIEOE
AS2 EXCLK
DIEOV
DI
AIO
Alternate Function
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
T4 Port H, Bit 7
T4, Timer/Counter4 counter source.
OC2B Port H, Bit 6
OC2B, Output Compare Match B output: The PH6 pin can serve as an external output for the Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDH6 set) to serve this function. The OC2B pin is also
the output pin for the PWM mode timer function.
OC4C Port H, Bit 5
OC4C, Output Compare Match C output: The PH5 pin can serve as an external output for the Timer/Counter4 Output Compare C. The pin has to be configured as an output (DDH5 set) to serve this function. The OC4C pin is also
the output pin for the PWM mode timer function.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
88
PH7/T4
PH6/OC2B
PH5/OC4C
PH4/OC4B
PUOE
PUOV
DDOE
DDOV
PVOE
OC2B ENABLE
OC4C ENABLE
OC4B ENABLE
PVOV
OC2B
OC4C
OC4B
PTOE
DIEOE
DIEOV
DI
T4 INPUT
AIO
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
89
13.3.9
Signal Name
PH3/OC4A
PH2/XCK2
PH1/TXD2
PH0/RXD2
PUOE
TXEN2
RXEN2
PUOV
PORTH0 PUD
DDOE
XCK2 OUTPUT
ENABLE
TXEN2
RXEN2
DDOV
PVOE
OC4A ENABLE
XCK2 OUTPUT
ENABLE
TXEN2
PVOV
OC4A
XCK2
TXD2
PTOE
DIEOE
DIEOV
DI
XC2K INPUT
RXD2
AIO
Alternate Function
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
90
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
91
PJ7
PJ6/ PCINT15
PJ5/ PCINT14
PJ4/ PCINT13
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
PCINT15PCIE1
PCINT14PCIE1
PCINT13PCIE1
DIEOV
DI
PCINT15 INPUT
PCINT14 INPUT
PCINT13 INPUT
AIO
13.3.10
Signal Name
PJ3/PCINT12
PJ2/XCK3/PCINT11
PJ1/TXD3/PCINT10
PJ0/RXD3/PCINT9
PUOE
TXEN3
RXEN3
PUOV
PORTJ0PUD
DDOE
XCK3 OUTPUT
ENABLE
TXEN3
RXEN3
DDOV
PVOE
XCK3 OUTPUT
ENABLE
TXEN3
PVOV
XCK3
TXD3
PTOE
DIEOE
PCINT12PCIE1
PCINT11PCIE1
PCINT10PCIE1
PCINT9PCIE1
DIEOV
DI
PCINT12 INPUT
PCINT11 INPUT
XCK3 INPUT
PCINT10 INPUT
AIO
Alternate Function
PK7
PK6
PK5
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
92
Alternate Function
PK4
PK3
PK2
PK1
PK0
PK7/ADC15/PCINT23
PK6/ADC14/PCINT22
PK5/ADC13/PCINT21
PK4/ADC12/PCINT20
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
PCINT23 PCIE2
PCINT22 PCIE2
PCINT21 PCIE2
PCINT20 PCIE2
DIEOV
DI
PCINT23 INPUT
PCINT22 INPUT
PCINT21 INPUT
PCINT20 INPUT
AIO
ADC15 INPUT
ADC14 INPUT
ADC13 INPUT
ADC12 INPUT
PK3/ADC11/PCINT19
PK2/ADC10/PCINT18
PK1/ADC9/PCINT17
PK0/ADC8/PCINT16
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
PCINT19 PCIE2
PCINT18 PCIE2
PCINT17 PCIE2
PCINT16 PCIE2
DIEOV
DI
PCINT19 INPUT
PCINT18 INPUT
PCINT17 INPUT
PCINT16 INPUT
AIO
ADC11 INPUT
ADC10INPUT
ADC9 INPUT
ADC8 INPUT
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
93
13.3.11
Alternate Function
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
94
Table 13-34 and Table 13-35 relates the alternate functions of Port L to the overriding signals shown in Figure 135 on page 73.
Table 13-34. Overriding Signals for Alternate Functions in PL7:PL4
Signal Name
PL7
PL6
PL5/OC5C
PL4/OC5B
PUOE
PUOV
DDOE
DDOV
PVOE
OC5C ENABLE
OC5B ENABLE
PVOV
OC5C
OC5B
PTOE
DIEOE
DIEOV
DI
AIO
PL3/OC5A
PL2/T5
PL1/ICP5
PL0/ICP4
PUOE
PUOV
DDOE
DDOV
PVOE
OC5A ENABLE
PVOV
OC5A
PTOE
DIEOE
DIEOV
DI
T5 INPUT
ICP5 INPUT
ICP4 INPUT
AIO
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
95
13.4
13.4.1
0x35 (0x55)
JTD
PUD
IVSEL
IVCE
Read/Write
R/W
R/W
R/W
R/W
Initial Value
MCUCR
13.4.3
0x02 (0x22)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
13.4.4
0x01 (0x21)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x00 (0x20)
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x05 (0x25)
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTB
13.4.7
PINA
13.4.6
DDRA
13.4.5
PORTA
0x04 (0x24)
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
DDRB
0x03 (0x23)
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
PINB
96
13.4.8
13.4.9
0x08 (0x28)
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
13.4.10
0x07 (0x27)
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x06 (0x26)
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0B (0x2B)
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x0A (0x2A)
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x09 (0x29)
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PIND
13.4.15
DDRD
13.4.14
PORTD
13.4.13
PINC
13.4.12
DDRC
13.4.11
PORTC
0x0E (0x2E)
PORTE7
PORTE6
PORTE5
PORTE4
PORTE3
PORTE2
PORTE1
PORTE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTE
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x0D (0x2D)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
DDRE
97
13.4.16
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0C (0x2C)
13.4.17
0x11 (0x31)
PORTF7
PORTF6
PORTF5
PORTF4
PORTF3
PORTF2
PORTF1
PORTF0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
13.4.18
0x10 (0x30)
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
13.4.19
0x0F (0x2F)
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
13.4.20
13.4.23
DDRF
13.4.22
PORTF
13.4.21
PINE
PINF
0x14 (0x34)
PORTG5
PORTG4
PORTG3
PORTG2
PORTG1
PORTG0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTG
0x13 (0x33)
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
DDRG
0x12 (0x32)
PING5
PING4
PING3
PING2
PING1
PING0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
PING
PORTH7
PORTH6
PORTH5
PORTH4
PORTH3
PORTH2
PORTH1
PORTH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x102)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
PORTH
98
13.4.24
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x101)
13.4.25
PINH5
PINH5
PINH5
PINH4
PINH3
PINGH
PINH1
PINH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(0x100)
13.4.26
PORTJ7
PORTJ6
PORTJ5
PORTJ4
PORTJ3
PORTJ2
PORTJ1
PORTJ0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x105)
DDJ7
DDJ6
DDJ5
DDJ4
DDJ3
DDJ2
DDJ1
DDJ0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x104)
PINJ5
PINJ5
PINJ5
PINJ4
PINJ3
PINGJ
PINJ1
PINJ0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(0x103)
PORTK7
PORTK6
PORTK5
PORTK4
PORTK3
PORTK2
PORTK1
PORTK0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x108)
PORTK
DDK7
DDK6
DDK5
DDK4
DDK3
DDK2
DDK1
DDK0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x107)
13.4.31
PINJ
13.4.30
DDRJ
13.4.29
PORTJ
13.4.28
PINH
13.4.27
DDRH
DDRK
PINK5
PINK5
PINK5
PINK4
PINK3
PINGK
PINK1
PINK0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(0x106)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
PINK
99
13.4.32
PORTL7
PORTL6
PORTL5
PORTL4
PORTL3
PORTL2
PORTL1
PORTL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x10B)
13.4.33
DDL7
DDL6
DDL5
DDL4
DDL3
DDL2
DDL1
DDL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x10A)
13.4.34
PORTL
DDRL
PINL5
PINL5
PINL5
PINL4
PINL3
PINGL
PINL1
PINL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(0x109)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
PINL
100
14. Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega640/1280/1281/2560/2561.
For a general explanation of the AVR interrupt handling, refer to Reset and Interrupt Handling on page 17.
14.1
Vector No.
Program Address(2)
Source
Interrupt Definition
$0000(1)
RESET
$0002
INT0
$0004
INT1
$0006
INT2
$0008
INT3
$000A
INT4
$000C
INT5
$000E
INT6
$0010
INT7
10
$0012
PCINT0
11
$0014
PCINT1
12
$0016(3)
PCINT2
13
$0018
WDT
14
$001A
TIMER2 COMPA
15
$001C
TIMER2 COMPB
16
$001E
TIMER2 OVF
Timer/Counter2 Overflow
17
$0020
TIMER1 CAPT
18
$0022
TIMER1 COMPA
19
$0024
TIMER1 COMPB
20
$0026
TIMER1 COMPC
21
$0028
TIMER1 OVF
Timer/Counter1 Overflow
22
$002A
TIMER0 COMPA
23
$002C
TIMER0 COMPB
24
$002E
TIMER0 OVF
Timer/Counter0 Overflow
25
$0030
SPI, STC
26
$0032
USART0 RX
USART0 Rx Complete
27
$0034
USART0 UDRE
28
$0036
USART0 TX
USART0 Tx Complete
29
$0038
ANALOG COMP
Analog Comparator
30
$003A
ADC
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Table 14-1.
Vector No.
Program Address(2)
Source
Interrupt Definition
31
$003C
EE READY
EEPROM Ready
32
$003E
TIMER3 CAPT
33
$0040
TIMER3 COMPA
34
$0042
TIMER3 COMPB
35
$0044
TIMER3 COMPC
36
$0046
TIMER3 OVF
Timer/Counter3 Overflow
37
$0048
USART1 RX
USART1 Rx Complete
38
$004A
USART1 UDRE
39
$004C
USART1 TX
USART1 Tx Complete
40
$004E
TWI
41
$0050
SPM READY
42
$0052(3)
TIMER4 CAPT
43
$0054
TIMER4 COMPA
44
$0056
TIMER4 COMPB
45
$0058
TIMER4 COMPC
46
$005A
TIMER4 OVF
Timer/Counter4 Overflow
(3)
47
$005C
TIMER5 CAPT
48
$005E
TIMER5 COMPA
49
$0060
TIMER5 COMPB
50
$0062
TIMER5 COMPC
51
$0064
TIMER5 OVF
Timer/Counter5 Overflow
$0066
(3)
USART2 RX
USART2 Rx Complete
53
$0068
(3)
USART2 UDRE
54
$006A(3)
USART2 TX
USART2 Tx Complete
55
(3)
USART3 RX
USART3 Rx Complete
(3)
USART3 UDRE
(3)
USART3 TX
USART3 Tx Complete
52
56
57
Notes:
14.2
$006C
$006E
$0070
1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see Memory
Programming on page 325.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The
address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash
Section.
3. Only available in ATmega640/1280/2560.
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Table 14-2.
BOOTRST
IVSEL
Reset Address
0x0000
0x0002
0x0000
0x0002
Note:
1. The Boot Reset Address is shown in Table 29-7 on page 320 through Table 29-15 on page 322. For the BOOTRST
Fuse 1 means unprogrammed while 0 means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega640/1280/1281/2560/2561 is:
Addre
ss
Label
s
Code
Comments
0x000
0
jmp
RESET
; Reset Handler
0x000
2
jmp
INT0
; IRQ0 Handler
0x000
4
jmp
INT1
; IRQ1 Handler
0x000
6
jmp
INT2
; IRQ2 Handler
0x000
8
jmp
INT3
; IRQ3 Handler
0x000
A
jmp
INT4
; IRQ4 Handler
0x000
C
jmp
INT5
; IRQ5 Handler
0x000
E
jmp
INT6
; IRQ6 Handler
0x001
0
jmp
INT7
; IRQ7 Handler
0x001
2
jmp
PCINT0
; PCINT0 Handler
0x001
4
jmp
PCINT1
; PCINT1 Handler
0x001
6
jmp
PCINT2
; PCINT2 Handler
0X001
8
jmp
WDT
0x001
A
jmp
TIM2_COMPA
0x001
C
jmp
TIM2_COMPB
0x001
E
jmp
TIM2_OVF
0x002
0
jmp
TIM1_CAPT
0x002
2
jmp
TIM1_COMPA
0x002
4
jmp
TIM1_COMPB
0x002
6
jmp
TIM1_COMPC
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0x002
8
jmp
TIM1_OVF
0x002
A
jmp
TIM0_COMPA
0x002
C
jmp
TIM0_COMPB
0x002
E
jmp
TIM0_OVF
0x003
0
jmp
SPI_STC
0x003
2
jmp
USART0_RXC
0x003
4
jmp
USART0_UDRE
0x003
6
jmp
USART0_TXC
0x003
8
jmp
ANA_COMP
0x003
A
jmp
ADC
0x003
C
jmp
EE_RDY
0x003
E
jmp
TIM3_CAPT
0x004
0
jmp
TIM3_COMPA
0x004
2
jmp
TIM3_COMPB
0x004
4
jmp
TIM3_COMPC
0x004
6
jmp
TIM3_OVF
0x004
8
jmp
USART1_RXC
0x004
A
jmp
USART1_UDRE
0x004
C
jmp
USART1_TXC
0x004
E
jmp
TWI
0x005
0
jmp
SPM_RDY
0x005
2
jmp
TIM4_CAPT
0x005
4
jmp
TIM4_COMPA
0x005
6
jmp
TIM4_COMPB
0x005
8
jmp
TIM4_COMPC
0x005
A
jmp
TIM4_OVF
0x005
C
jmp
TIM5_CAPT
0x005
E
jmp
TIM5_COMPA
0x006
0
jmp
TIM5_COMPB
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0x006
2
jmp
TIM5_COMPC
0x006
4
jmp
TIM5_OVF
0x006
6
jmp
USART2_RXC
0x006
8
jmp
USART2_UDRE
0x006
A
jmp
USART2_TXC
0x006
C
jmp
USART3_RXC
0x006
E
jmp
USART3_UDRE
0x007
0
jmp
USART3_TXC
ldi
r16,
high(RAMEND)
0x007
3
out
SPH,r16
0x007
4
ldi
r16,
low(RAMEND)
0x007
5
out
SPL,r16
0x007
6
sei
0x007
7
<ins
tr
>
;
0x007
2
...
RESET
:
...
; Enable interrupts
xxx
..
.
...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8Kbytes and the IVSEL bit in the
MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses is:
Address Labels Code
Comments
0x00001
out
SPH,r16
0x00002
ldi
r16,low(RAMEND)
0x00003
0x00004
out
sei
SPL,r16
0x00005
<instr>
; Enable interrupts
xxx
;
.org 0x1F002
0x1F002
jmp
EXT_INT0
; IRQ0 Handler
0x1F004
jmp
EXT_INT1
; IRQ1 Handler
...
...
...
0x1FO70
jmp
USART3_TXC
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When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code
Comments
.org 0x0002
0x00002
jmp
EXT_INT0
; IRQ0 Handler
0x00004
jmp
EXT_INT1
; IRQ1 Handler
...
...
...
0x00070
jmp
USART3_TXC
;
.org 0x1F000
0x1F000 RESET: ldi
0x1F001
out
SPH,r16
0x1F002
ldi
r16,low(RAMEND)
0x1F003
0x1F004
out
sei
SPL,r16
0x1F005
<instr>
; Enable interrupts
xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
Address
Labels Code
Comments
;
.org 0x1F000
0x1F000
0x1F002
jmp
jmp
RESET
EXT_INT0
; Reset handler
; IRQ0 Handler
0x1F004
jmp
EXT_INT1
; IRQ1 Handler
...
...
...
0x1F070
jmp
USART3_TXC
;
0x1F072
RESET: ldi
0x1F073
out
0x1F074
ldi
r16,low(RAMEND)
0x1F075
0x1F076
out
sei
SPL,r16
0x1FO77
<instr>
; Enable interrupts
xxx
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14.3
r16, MCUCR
C Code Example
void Move_interrupts(void)
{
uchar temp;
/* Get MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL);
}
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14.4
14.4.1
Register Description
MCUCR MCU Control Register
Bit
0x35 (0x55)
JTD
PUD
IVSEL
IVCE
Read/Write
R/W
R/W
R/W
R/W
Initial Value
MCUCR
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot
Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Memory Programming on page 325 for details on Boot Lock bits.
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15.1
pin_lat
PCINT(0)
D
LE
pcint_syn
pcint_setflag
PCIF
pin_sync
clk
PCINT(0) in PCMSK(x)
clk
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
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15.2
15.2.1
Register Description
EICRA External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x69)
EICRA
Bits 7:0 ISC31, ISC30 ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding
interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined
in Table 15-1. Edges on INT3:0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum
pulse width given in Table 15-2 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long
as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first
disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally,
the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.
Table 15-1.
ISCn1
ISCn0
Description
Note:
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Table 15-2.
Symbol
Parameter
tINT
Condition
Min.
Typ.
Max.
50
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ns
110
15.2.2
ISC71
ISC70
ISC61
ISC60
ISC51
ISC50
ISC41
ISC40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x6A)
EICRB
Bits 7:0 ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding
interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined
in Table 15-3. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is
selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed
to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt
request as long as the pin is held low.
Table 15-3.
ISCn1
ISCn0
Description
The falling edge between two samples of INTn generates an interrupt request
The rising edge between two samples of INTn generates an interrupt request
Note:
15.2.3
1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the
EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
0x1D (0x3D)
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
EIMSK
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15.2.4
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
IINTF0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0x1C (0x3C)
EIFR
(0x68)
PCIE2
PCIE1
PCIE0
Read/Write
R/W
R/W
R/W
Initial Value
PCICR
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15.2.6
0x1B (0x3B)
PCIF2
PCIF1
PCIF0
Read/Write
R/W
R/W
R/W
Initial Value
PCIFR
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x6D)
PCMSK2
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x6C)
PCMSK1
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15.2.9
(0x6B)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PCMSK0
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16.2
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units,
and with PWM support. It allows accurate program execution timing (event management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual placement of I/O pins,
refer to TQFP-pinout ATmega640/1280/2560 on page 2. CPU accessible I/O Registers, including I/O bits and I/O
pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description on
page 126.
Figure 16-1. 8-bit Timer/Counter Block Diagram
Count
Clear
Direction
TOVn
(Int.Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=0
OCnA
(Int.Req.)
Waveform
Generation
OCnA
OCRnA
DATA BUS
16.1
Fixed
TOP
Value
OCnB
(Int.Req.)
Waveform
Generation
OCnB
OCRnB
TCCRnA
TCCRnB
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16.2.1
Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not
shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See Output Compare Unit on page 117. for
details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request.
16.2.2
Definitions
Many register and bit references in this section are written in general form. A lower case n replaces the
Timer/Counter number, in this case 0. A lower case x replaces the Output Compare Unit, in this case Compare
Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 16-1 are also used extensively throughout the document.
Table 16-1.
16.3
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored
in the OCR0A Register. The assignment is dependent on the mode of operation.
16.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 16-2 on page 117
shows a block diagram of the counter and its surroundings.
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DATA BUS
Clock Select
count
clear
TCNTn
Control Logic
Edge
Detector
clkTn
Tn
direction
( From Prescaler )
bottom
top
direction
clear
clkTn
top
bottom
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clk T0 ). clk T0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform
generation, see Modes of Operation on page 120.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits.
TOV0 can be used for generating a CPU interrupt.
16.5
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DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnX1:0
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the
output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly.
16.5.1
16.5.2
16.5.3
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal
mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the
COM0x1:0 bits will take effect immediately.
16.6
COMnx1
COMnx0
FOCn
Waveform
Generator
Q
1
OCnx
DATA BUS
OCnx
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either
of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as
output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled.
Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See Register Description on
page 126.
16.6.1
119
16.7
Modes of Operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a
Compare Match. See Compare Match Output Unit on page 143.
For detailed timing information see Timer/Counter Timing Diagrams on page 124.
16.7.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
16.7.2
TCNTn
OCn
(Toggle)
Period
(COMnx1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
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For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each
Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnx = ------------------------------------------------2 N 1 + OCRnx
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
16.7.3
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if
the WGM02 bit is set. This option is not available for the OC0B pin (see Table 16-3 on page 126). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and
clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------N 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle
its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
16.7.4
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OCRnx Update
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting
the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the
WGM02 bit is set. This option is not available for the OC0B pin (see Table 16-4 on page 127). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the
counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = ----------------N 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 16-7 OCnx has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
OCR0A changes its value from MAX, like in Figure 16-7. When the OCR0A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
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16.8
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 16-9 shows the same timing data, but with the prescaler enabled.
Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 16-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 16-11 on page 125 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM
mode where OCR0A is TOP.
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Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
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16.9
16.9.1
Register Description
TCCR0A Timer/Counter Control Register A
Bit
0x24 (0x44)
COM0A1
COM0A0
COM0B1
COM0B0
WGM01
WGM00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TCCR0A
COM0A1
COM0A0
Description
Table 16-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Table 16-3.
COM0A1
COM0A0
Description
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See Fast PWM Mode on page 121 for more details.
Table 16-4 on page 127 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
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Table 16-4.
COM0A1
COM0A0
Description
Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when
down-counting
Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when
down-counting
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 122 for more details.
COM0B1
COM0B0
Description
Table 16-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.
Table 16-6.
COM0B1
COM0B0
Description
Reserved
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See Fast PWM Mode on page 121 for more details.
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Table 16-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.
Compare Output Mode, Phase Correct PWM Mode(1)
Table 16-7.
COM0B1
COM0B0
Description
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when
down-counting
Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when
down-counting
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 122 for more details.
Mode
WGM2
WGM1
WGM0
Timer/Counter Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Normal
0xFF
Immediate
MAX
0xFF
TOP
BOTTOM
CTC
OCRA
Immediate
MAX
Fast PWM
0xFF
TOP
MAX
Reserved
OCRA
TOP
BOTTOM
Reserved
Fast PWM
OCRA
BOTTOM
TOP
Note:
1. MAX
= 0xFF
2. BOTTOM = 0x00
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16.9.2
0x25 (0x45)
FOC0A
FOC0B
WGM02
CS02
CS01
CS00
Read/Write
R/W
R/W
R/W
R/W
Initial Value
TCCR0B
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Table 16-9.
CS02
CS01
CS00
Description
clkI/O/(No prescaling)
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
16.9.3
0x26 (0x46)
TCNT0[7:0]
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between
TCNT0 and the OCR0x Registers.
16.9.4
0x27 (0x47)
OCR0A[7:0]
OCR0A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0A pin.
16.9.5
0x28 (0x48)
OCR0B[7:0]
OCR0B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0B pin.
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16.9.6
(0x6E)
OCIE0B
OCIE0A
TOIE0
Read/Write
R/W
R/W
R/W
Initial Value
TIMSK0
0x15 (0x35)
OCF0B
OCF0A
TOV0
Read/Write
R/W
R/W
R/W
Initial Value
TIFR0
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SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow
interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 16-8, Waveform Generation Mode
Bit Description on page 128.
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Features
17.2
Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case n replaces the
Timer/Counter number, and a lower case x replaces the Output Compare unit channel. However, when using the
register or bit defines in a program, the precise form must be used, that is, TCNT1 for accessing Timer/Counter1
counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 17-1 on page 134. For the actual placement of I/O pins, see TQFP-pinout ATmega640/1280/2560 on page 2 and Pinout ATmega1281/2561 on page
4. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description on page 154.
The Power Reduction Timer/Counter1 bit, PRTIM1, in PRR0 Power Reduction Register 0 on page 55 must be
written to zero to enable Timer/Counter1 module.
The Power Reduction Timer/Counter3 bit, PRTIM3, in PRR1 Power Reduction Register 1 on page 56 must be
written to zero to enable Timer/Counter3 module.
The Power Reduction Timer/Counter4 bit, PRTIM4, in PRR1 Power Reduction Register 1 on page 56 must be
written to zero to enable Timer/Counter4 module.
The Power Reduction Timer/Counter5 bit, PRTIM5, in PRR1 Power Reduction Register 1 on page 56 must be
written to zero to enable Timer/Counter5 module.
Timer/Counter4 and Timer/Counter5 only have full functionality in the ATmega640/1280/2560. Input capture and
output compare are not available in the ATmega1281/2561.
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TOVn
(Int.Req.)
Control Logic
TCLK
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=0
OCFnA
(Int.Req.)
Waveform
Generation
OCnA
OCRnA
OCFnB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
DATABUS
OCnB
OCRnB
OCFnC
(Int.Req.)
Waveform
Generation
OCnC
OCRnC
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
ICRn
Noise
Canceler
ICPn
TCCRnA
Note:
17.2.1
TCCRnB
TCCRnC
1. Refer to Figure 1-1 on page 2, Table 13-5 on page 76, and Table 13-11 on page 80 for Timer/Counter1 and 3 and
3 pin placement and description.
Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section Accessing 16-bit Registers on page 135. The Timer/Counter Control Registers
(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as Int.Req.)
signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the
Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers are
shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
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its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is
referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the Timer/Counter value at all
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency
output on the Output Compare pin (OCnA/B/C). See Output Compare Units on page 141. The compare match
event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICPn) or on the Analog Comparator pins (see AC Analog Comparator on page
265). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing
noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM
mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output.
17.2.2
Definitions
The following definitions are used extensively throughout the document:
Table 17-1.
17.3
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or
0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of
the mode of operation.
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C Code Examples(1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...
Note:
The assembly code example returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two
instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the
same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted.
Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the
OCRnA/B/C or ICRn Registers can be done by using the same principle.
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C Code Example(1)
unsigned int TIM16_ReadTCNTn( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNTn into i */
i = TCNTn;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
The assembly code example returns the TCNTn value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the
OCRnA/B/C or ICRn Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNTn( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNTn to i */
TCNTn = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn.
17.3.1
17.4
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17.5
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows
a block diagram of the counter and its surroundings.
Figure 17-2. Counter Unit Block Diagram
DATA BUS
(8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)
TCNTnL (8-bit)
Clear
Direction
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
TOP
BOTTOM
Direction
Clear
clkTn
Timer/Counter clock.
TOP
BOTTOM
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper
eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can
only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value
when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that
will give unpredictable results. The special cases are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits
(CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in
the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how
the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more
details about advanced counting sequences and waveform generation, see Modes of Operation on page 144.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits.
TOVn can be used for generating a CPU interrupt.
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17.6
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit)
WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
ACO*
Analog
Comparator
ACIC*
TCNTnL (8-bit)
ICNC
ICES
Noise
Canceler
Edge
Detector
ICFn (Int.Req.)
ICPn
Note:
The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP not Timer/Counter3, 4 or 5.
When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively on the analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.
When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register
(ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn
Register. If enabled (TICIEn = 1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a
logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and
then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for
defining the counters TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set
before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be
written to the ICRnH I/O location before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers on page 135.
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17.6.1
17.6.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control
Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
17.6.3
17.7
141
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is, counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the
Waveform Generator.
Figure 17-4 shows a block diagram of the Output Compare unit. The small n in the register and bit names indicates the device number (n = n for Timer/Counter n), and the x indicates Output Compare unit (A/B/C). The
elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
Figure 17-4. Output Compare Unit, Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
TCNTnH (8-bit)
OCRnxH (8-bit)
TCNTnL (8-bit)
OCRnxL (8-bit)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM
Waveform Generator
WGMn3:0
OCnx
COMnx1:0
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx
directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the
Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is
not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the
compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O
location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx
buffer or OCRnx Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers on page 135.
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17.7.1
17.7.2
17.7.3
17.8
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COMnx1
COMnx0
FOCnx
Waveform
Generator
Q
1
OCnx
DATA BUS
OCnx
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either
of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as
output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 17-3 on page 155, Table 17-4 on page 155
and Table 17-5 on page 155 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled.
Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See Register Description on
page 154.
The COMnx1:0 bits have no effect on the Input Capture unit.
17.8.1
17.9
Modes of Operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a
compare match. See Compare Match Output Unit on page 143.
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Table 17-2.
Mode
WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter
Mode of Operation
TOP
Update of
OCRnx at
TOVn Flag
Set on
Normal
0xFFFF
Immediate
MAX
0x00FF
TOP
BOTTOM
0x01FF
TOP
BOTTOM
0x03FF
TOP
BOTTOM
CTC
OCRnA
Immediate
MAX
0x00FF
BOTTOM
TOP
0x01FF
BOTTOM
TOP
0x03FF
BOTTOM
TOP
ICRn
BOTTOM
BOTTOM
OCRnA
BOTTOM
BOTTOM
10
ICRn
TOP
BOTTOM
11
OCRnA
TOP
BOTTOM
12
CTC
ICRn
Immediate
MAX
13
(Reserved)
14
Fast PWM
ICRn
BOTTOM
TOP
15
Fast PWM
OCRnA
BOTTOM
TOP
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.
For detailed timing information refer to Timer/Counter Timing Diagrams on page 152.
17.9.1
Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in
this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
17.9.2
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counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 17-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared.
Figure 17-6. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
Period
(COMnA1:0 = 1)
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or
ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is
not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 =
15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform
generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform
frequency is defined by the following equation:
f clk_I/O
f OCnA = -------------------------------------------------2 N 1 + OCRnA
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
17.9.3
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mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICRn or OCRnA. The
minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or
OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log TOP + 1
R FPWM = ---------------------------------log 2
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA
(WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 17-7 on page 147. The figure shows fast PWM mode when OCRnA or ICRn is used
to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the
TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when
a compare match occurs.
Figure 17-7. Fast PWM Mode, Timing Diagram
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn
Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP
value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn
Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with
none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of
TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will
then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written
anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The
OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle
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the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the
TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA
Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively
changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the
COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COMnx1:0 to three (see Table on page 155). The actual OCnx value will only be visible on the port pin if the
data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx
Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ---------------------------------N 1 + TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COMnx1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle
its logical level on each compare match (COMnA1:0 = 1). This applies only if OCR1A is used to define the TOP
value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA
is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of
the Output Compare unit is enabled in the fast PWM mode.
17.9.4
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on Figure 17-8 on page 149. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define
TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes
represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a compare
match occurs.
Figure 17-8. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or
ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as
the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 17-8 illustrates,
changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx
update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is
determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.
When these two values differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no
differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting
the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table 17-5 on page 155). The actual OCnx value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting
(or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments,
and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter dec-
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rements. The PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
f clk_I/O
f OCnxPCPWM = --------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the
OC1A output will toggle with a 50% duty cycle.
17.9.5
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Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated
with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the
OCnA or ICFn Flag set when TCNTn has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNTn and the OCRnx.
As Figure 17-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods.
Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA
Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx
pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table 17-5 on page 155). The actual OCnx value will only be visible
on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter
increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = --------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A
output will toggle with a 50% duty cycle.
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(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 17-11 shows the same timing data, but with the prescaler enabled.
Figure 17-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
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Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct
PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should
be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the
TOVn Flag at BOTTOM.
Figure 17-12. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Figure 17-13 shows the same timing data, but with the prescaler enabled.
Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
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Bit
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x80)
17.11.2
Bit
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x90)
17.11.3
TCCR3A
Bit
COM4A1
COM4A0
COM4B1
COM4B0
COM4C1
COM4C0
WGM41
WGM40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xA0)
17.11.4
TCCR1A
TCCR4A
Bit
COM5A1
COM5A0
COM5B1
COM5B0
COM5C1
COM5C0
WGM51
WGM50
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x120)
TCCR5A
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COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
Table 17-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode.
Table 17-4.
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal
port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C
disconnected
Note:
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. In this
case the compare match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode on page 146. for
more details.
Table 17-5 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct and frequency correct PWM mode.
Table 17-5.
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port
operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected
Note:
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1//COMnC1 is set. See
Phase Correct PWM Mode on page 148. for more details.
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17.11.5
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x81)
17.11.6
ICNC3
ICES3
WGM33
WGM32
CS32
CS31
CS30
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x91)
17.11.7
TCCR3B
ICNC4
ICES4
WGM43
WGM42
CS42
CS41
CS40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xA1)
17.11.8
TCCR1B
TCCR4B
ICNC5
ICES5
WGM53
WGM52
CS52
CS51
CS50
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x121)
TCCR5B
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CSn2
CSn1
CSn0
Description
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
17.11.9
FOC1A
FOC1B
FOC1C
Read/Write
Initial Value
(0x82)
TCCR1C
FOC3A
FOC3B
FOC3C
Read/Write
Initial Value
(0x92)
TCCR3C
FOC4A
FOC4B
FOC4C
Read/Write
Initial Value
(0xA2)
TCCR4C
FOC5A
FOC5B
FOC3C
Read/Write
Initial Value
(0x122)
TCCR5C
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FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits
that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
Bit 4:0 Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to
zero when TCCRnC is written.
17.11.13 TCNT1H and TCNT1L Timer/Counter 1
Bit
(0x85)
TCNT1[15:8]
(0x84)
TCNT1[7:0]
0
TCNT1H
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x95)
TCNT3[15:8]
(0x94)
TCNT3[7:0]
TCNT3H
TCNT3L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xA5)
TCNT4[15:8]
(0xA4)
TCNT4[7:0]
TCNT4H
TCNT4L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x125)
TCNT5[15:8]
(0x124)
TCNT5[7:0]
TCNT5H
TCNT5L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
Accessing 16-bit Registers on page 135.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare match between
TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare
units.
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(0x89)
OCR1A[15:8]
(0x88)
OCR1A[7:0]
0
OCR1AH
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x8B)
OCR1B[15:8]
(0x8A)
OCR1B[7:0]
OCR1BH
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x8D)
OCR1C[15:8]
(0x8C)
OCR1C[7:0]
OCR1CH
OCR1CL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x99)
OCR3A[15:8]
(0x98)
OCR3A[7:0]
OCR3AH
OCR3AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x9B)
OCR3B[15:8]
(0x9A)
OCR3B[7:0]
OCR3BH
OCR3BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x9D)
OCR3C[15:8]
(0x9C)
OCR3C[7:0]
OCR3CH
OCR3CL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xA9)
OCR4A[15:8]
(0xA8)
OCR4A[7:0]
OCR4AH
OCR4AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
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(0xAA)
OCR4B[15:8]
(0xAB)
OCR4B[7:0]
0
OCR4BH
OCR4BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xAD)
OCR4C[15:8]
(0xAC)
OCR4C[7:0]
OCR4CH
OCR4CL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x129)
OCR5A[15:8]
(0x128)
OCR5A[7:0]
OCR5AH
OCR5AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x12B)
OCR5B[15:8]
(0x12A)
OCR5B[7:0]
OCR5BH
OCR5BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x12D)
OCR5C[15:8]
(0x12C)
OCR5C[7:0]
OCR5CH
OCR5CL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See Accessing 16-bit Registers on
page 135.
17.11.29 ICR1H and ICR1L Input Capture Register 1
Bit
(0x87)
ICR1[15:8]
(0x86)
ICR1[7:0]
0
ICR1H
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
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(0x97)
ICR3[15:8]
(0x96)
ICR3[7:0]
0
ICR3H
ICR3L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xA7)
ICR4[15:8]
(0xA6)
ICR4[7:0]
ICR4H
ICR4L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x127)
ICR5[15:8]
(0x126)
ICR5[7:0]
ICR5H
ICR5L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or
optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See Accessing 16-bit Registers on
page 135.
17.11.33 TIMSK1 Timer/Counter 1 Interrupt Mask Register
Bit
(0x6F)
ICIE1
OCIE1C
OCIE1B
OCIE1A
TOIE1
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK1
Bit
(0x71)
ICIE3
OCIE3C
OCIE3B
OCIE3A
TOIE3
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK3
Bit
(0x72)
ICIE4
OCIE4C
OCIE4B
OCIE4A
TOIE4
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK4
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Bit
(0x73)
ICIE5
OCIE5C
OCIE5B
OCIE5A
TOIE5
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK5
0x16 (0x36)
ICF1
OCF1C
OCF1B
OCF1A
TOV1
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR1
0x18 (0x38)
ICF3
OCF3C
OCF3B
OCF3A
TOV3
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR3
0x19 (0x39)
ICF4
OCF4C
OCF4B
OCF4A
TOV4
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR4
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0x1A (0x3A)
ICF5
OCF5C
OCF5B
OCF5A
TOV5
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR5
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18.1
18.2
Prescaler Reset
The prescaler is free running, that is, operates independently of the Clock Select logic of the Timer/Counter, and it
is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counters clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of
system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care
must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset
will affect the prescaler period for all Timer/Counters it is connected to.
18.3
Tn
Tn_sync
(To Clock
Select Logic)
LE
clk I/O
Synchronization
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock
cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2)
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 18-2. Prescaler for synchronous Timer/Counters
clk I/O
Clear
PSR10
Tn
Synchronization
Tn
Synchronization
CSn0
CSn0
CSn1
CSn1
CSn2
CSn2
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18.4
Register Description
18.4.1
0x23 (0x43)
TSM
PSRASY
PSRSYNC
Read/Write
R/W
R/W
R/W
Initial Value
GTCCR
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Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The
modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare
Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see Timer/Counter 0, 1, 3, 4, and 5
Prescaler on page 164 and 8-bit Timer/Counter2 with PWM and Asynchronous Operation on page 169.
Figure 19-1. Output Compare Modulator, Block Diagram
Timer/Counter 1
OC1C
Pin
Timer/Counter 0
OC1C /
OC0A / PB7
OC0A
When the modulator is enabled, the two output compare channels are modulated together as shown in the block
diagram (see Figure 19-1).
19.2
Description
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The outputs of the
Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register when one of them is enabled
(that is, when COMnx1:0 is not equal to zero). When both OC1C and OC0A are enabled at the same time, the
modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 19-2. The schematic includes part of the
Timer/Counter units and the port B pin 7 output driver circuit.
Figure 19-2. Output Compare Modulator, Schematic
COMA01
COMA00
Vcc
COM1C1
COM1C0
Modulator
OC1C
( From Waveform Generator )
Pin
0
OC1C /
OC0A/ PB7
OC0A
D
PORTB7
DATABUS
DDRB7
When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting.
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19.2.1
Timing example
Figure 19-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate in fast PWM
mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode
(COMnx1:0 = 1).
Figure 19-3. Output Compare Modulator, Timing Diagram
clk I/O
OC1C
(FPWM Mode)
OC0A
(CTC Mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1)
(Period)
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor
of two. The reason for the reduction is illustrated in Figure 19-3 at the second and third period of the PB7 output
when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on
the PB7 output is equal in both periods.
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Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-12 on page 153 For the actual placement of I/O pins, see Pin Configurations on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins,
are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description on
page 182.
The Power Reduction Timer/Counter2 bit, PRTIM2, in PRR0 Power Reduction Register 0 on page 55 must be
written to zero to enable Timer/Counter2 module.
Figure 20-1. 8-bit Timer/Counter Block Diagram
Count
TOVn
(Int.Req.)
Clear
Direction
Control Logic
clkTn
TOSC1
T/C
Oscillator
TOP
BOTTOM
TOSC2
Prescaler
clkI/O
Timer/Counter
TCNTn
=0
OCnA
(Int.Req.)
Waveform
Generation
OCnA
OCRnA
Fixed
TOP
Value
DATA BUS
20.1
Waveform
Generation
=
OCRnB
OCnB
(Int.Req.)
Synchronization Unit
OCnB
clkI/O
clkASY
Status flags
ASSRn
TCCRnA
asynchronous mode
select (ASn)
TCCRnB
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20.1.1
Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt
request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts
are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value
at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See Output Compare Unit on page 175 for
details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request.
20.1.2
Definitions
Many register and bit references in this document are written in general form. A lower case n replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on.
The definitions in Table 20-1 are also used extensively throughout the section.
Table 20-1.
20.2
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored
in the OCR2A Register. The assignment is dependent on the mode of operation
20.3
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 20-2 on page 171
shows a block diagram of the counter and its surrounding environment.
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DATA BUS
TOSC1
count
clear
TCNTn
clk Tn
Control Logic
Prescaler
T/C
Oscillator
direction
TOSC2
bottom
top
clkI/O
direction
clear
clkTn
top
bottom
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be
accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter
Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform
generation, see Modes of Operation .
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits.
TOV2 can be used for generating a CPU interrupt.
20.4
Modes of Operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted
PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a
compare match. See Compare Match Output Unit on page 176.
For detailed timing information refer to Timer/Counter Timing Diagrams on page 177.
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20.4.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
20.4.2
TCNTn
OCnx
(Toggle)
Period
(COMnx1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower
than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by
the following equation:
f clk_I/O
f OCnx = ------------------------------------------------2 N 1 + OCRnx
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
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20.4.3
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (see Table
20-3 on page 182). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match
between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------N 256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM2A1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle
its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency
of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the
double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
20.4.4
173
frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes,
these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 20-5. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between
OCR2x and TCNT2.
Figure 20-5. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 20-4
on page 183). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between
OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match
between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase
correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = ----------------N 510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
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At the very start of period 2 in Figure 20-5 on page 174 OCnx has a transition from high to low even though there is
no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases
that give a transition without Compare Match.
20.5
OCR2A changes its value from MAX, like in Figure 20-5 on page 174. When the OCR2A value is MAX the OCn
pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM
the OCn value at MAX must correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
Waveform Generator
OCnx
FOCn
WGMn1:0
COMnX1:0
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x
directly.
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20.5.1
20.5.2
20.5.3
20.6
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COMnx1
COMnx0
FOCnx
Waveform
Generator
Q
1
OCnx
DATA BUS
OCnx
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either
of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as
output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled.
Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See Register Description on
page 182.
20.6.1
20.7
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(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 20-9 shows the same timing data, but with the prescaler enabled.
Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 20-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
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Figure 20-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCRnx
OCFnx
20.8
Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2x, and TCCR2x.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
The CPU main clock frequency must be more than four times the Oscillator frequency.
When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the five mentioned registers
have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an
OCR2x write in progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register ASSR has been implemented.
When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x,
the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device.
Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any
of the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled
during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the
corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the
MCU will not wake up.
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions
must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to
be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt
will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering
Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one
TOSC1 cycle has elapsed:
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When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running,
except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby
mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize.
The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up
from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost
after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter
whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter
value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes
execution from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since
TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When
waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the
previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after
waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2x or TCCR2x.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
Timer/Counter Prescaler
Figure 20-12. Prescaler for Timer/Counter2
PSRASY
clkT2S/1024
clkT2S/256
AS2
clkT2S/128
Clear
clkT2S/64
TOSC1
clkT2S
clkT2S/32
clkI/O
clkT2S/8
20.9
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the
processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is
changed on the timer clock and is not synchronized to the processor clock.
CS20
CS21
CS22
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The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock
clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This
enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an
independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. By setting the EXCLK bit in the ASSR, a 32kHz external clock can be applied. See ASSR Asynchronous Status
Register on page 187 for details.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and
clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the
prescaler. This allows the user to operate with a predictable prescaler.
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COM2A1
COM2A0
COM2B1
COM2B0
WGM21
WGM20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xB0)
TCCR2A
COM2A1
COM2A0
Description
Table 20-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Table 20-3.
COM2A1
COM2A0
Description
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See Fast PWM Mode on page 173 for more details.
Table 20-4 on page 183 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
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Table 20-4.
COM2A1
COM2A0
Description
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 173 for more details.
COM2B1
COM2B0
Description
Table 20-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode.
Table 20-6.
COM2B1
COM2B0
Description
Reserved
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at BOTTOM. See Fast PWM Mode on page 173 for more details.
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Table 20-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
Table 20-7.
COM2B1
COM2B0
Description
Reserved
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 173 for more details.
Mode
WGM2
WGM1
WGM0
Timer/Counter Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
Normal
0xFF
Immediate
MAX
0xFF
TOP
BOTTOM
CTC
OCRA
Immediate
MAX
Fast PWM
0xFF
BOTTOM
MAX
Reserved
OCRA
TOP
BOTTOM
Reserved
Fast PWM
OCRA
BOTTOM
TOP
Notes:
1. MAX = 0xFF.
2. BOTTOM= 0x00.
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20.10.2
FOC2A
FOC2B
WGM22
CS22
CS21
CS20
Read/Write
R/W
R/W
R/W
R/W
Initial Value
(0xB1)
TCCR2B
CS22
CS21
CS20
Description
clkT2S/(No prescaling)
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Table 20-9.
CS22
CS21
CS20
Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
20.10.3
(0xB2)
TCNT2[7:0]
TCNT2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between
TCNT2 and the OCR2x Registers.
20.10.4
(0xB3)
OCR2A[7:0]
OCR2A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2A pin.
20.10.5
(0xB4)
OCR2B[7:0]
OCR2B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC2B pin.
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20.10.6
(0xB6)
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
Read/Write
R/W
R/W
Initial Value
ASSR
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20.10.7
(0x70)
OCIE2B
OCIE2A
TOIE2
Read/Write
R/W
R/W
R/W
Initial Value
TIMSK2
0x17 (0x37)
OCF2B
OCF2A
TOV2
Read/Write
R/W
R/W
R/W
Initial Value
TIFR2
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20.10.9
0x23 (0x43)
TSM
PSRASY
PSRSYNC
Read/Write
R/W
R/W
R/W
Initial Value
GTCCR
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USART can also be used in Master SPI mode, see USART in SPI Mode on page 227.
The Power Reduction SPI bit, PRSPI, in PRR0 Power Reduction Register 0 on page 55 on page 50 must be
written to zero to enable SPI module.
Figure 21-1. SPI Block Diagram(1)
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
Note:
1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 76 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 21-2. The system consists of two
shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low
the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always
shifted from Master to Slave on the Master Out Slave In, MOSI, line, and from Slave to Master on the Master In
Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave
Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by
user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the
SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 21-2. SPI Master-slave Interconnection
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that
bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When
receiving data, however, a received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of
the clock signal, the minimum low and high periods should be:
Low period: Longer than two CPU clock cycles.
High period: Longer than two CPU clock cycles.
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 21-1. For more details on automatic port overrides, refer to Alternate Port Functions on page 72.
Table 21-1.
Pin
Note:
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
1. See Alternate Functions of Port B on page 76 for a detailed description of how to define the direction of the user
defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins.
DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example,
if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
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r17,(1<<DD_MOSI)|(1<<DD_SCK)
out
DDR_SPI,r17
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out
SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out
SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
Note:
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi
r17,(1<<DD_MISO)
out
DDR_SPI,r17
; Enable SPI
ldi
r17,(1<<SPE)
out
SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
Note:
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21.1
21.1.1
SS Pin Functionality
Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is
activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven
high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the
SPI logic will be reset once the SS pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master
clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic,
and drop any partially received data in the Shift Register.
21.1.2
Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the
pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by
peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system
interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a
Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt
routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is
driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a
slave select, it must be set by the user to re-enable SPI Master mode.
21.1.3
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 21-3 on page 196 and Figure 21-4 on
page 196. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for
data signals to stabilize. This is clearly seen by summarizing Table 21-3 on page 197 and Table 21-4 on page 197
in Table 21-2.
Table 21-2.
CPOL Functionality
Leading Edge
Trailing Edge
SPI Mode
CPOL=0, CPHA=0
Sample (Rising)
Setup (Falling)
CPOL=0, CPHA=1
Setup (Rising)
Sample (Falling)
CPOL=1, CPHA=0
Sample (Falling)
Setup (Rising)
CPOL=1, CPHA=1
Setup (Falling)
Sample (Rising)
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Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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21.2
21.2.1
Register Description
SPCR SPI Control Register
Bit
0x2C (0x4C)
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SPCR
CPOL Functionality
CPOL
Leading Edge
Trailing Edge
Rising
Falling
Falling
Rising
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
Sample
Setup
Setup
Sample
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21.2.2
SPI2X
SPR1
SPR0
SCK Frequency
fosc/4
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
SPIF
WCOL
SPI2X
Read/Write
R/W
Initial Value
0x2D (0x4D)
SPSR
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21.2.3
0x2E (0x4E)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SPDR
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift
Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive
buffer to be read.
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22. USART
22.1
Features
22.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial
communication device.
The ATmega640/1280/2560 has four USARTs, USART0, USART1, USART2, and USART3. The functionality for
all four USARTs is described below. USART0, USART1, USART2, and USART3 have different I/O registers as
shown in Register Summary on page 399.
A simplified block diagram of the USART Transmitter is shown in Figure 22-1 on page 201. CPU accessible I/O
Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in PRR0 Power Reduction Register 0 on page 55 must be disabled by writing a logical zero to it.
The Power Reducion USART1 bit, PRUSART1, in PRR1 Power Reduction Register 1 on page 56 must be disabled by writing a logical zero to it.
The Power Reducion USART2 bit, PRUSART2, in PRR1 Power Reduction Register 1 on page 56 must be disabled by writing a logical zero to it.
The Power Reducion USART3 bit, PRUSART3, in PRR1 Power Reduction Register 1 on page 56 must be disabled by writing a logical zero to it.
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Clock Generator
UBRR[H:L]
OSC
SYNC LOGIC
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
UDR (Transmit)
DATA BUS
PARITY
GENERATOR
TxD
Receiver
UCSRA
Note:
PIN
CONTROL
CLOCK
RECOVERY
RX
CONTROL
DATA
RECOVERY
PIN
CONTROL
UDR (Receive)
PARITY
CHECKER
UCSRB
RxD
UCSRC
1. See Figure 1-1 on page 2, Figure 1-3 on page 4, Table 13-12 on page 80, Table 13-15 on page 82, Table 13-24 on
page 88 and Table 13-27 on page 90 for USART pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock
Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate
generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of
a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame
formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is
the most complex part of the USART module due to its clock and data recovery units. The recovery units are used
for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control
logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the
Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
22.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four
modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave
synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in
the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn
pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn
pin is only active when using synchronous mode.
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U2X
fosc
Prescaling
Down-Counter
UBRR+1
/2
/4
/2
0
1
0
OSC
DDR_XCK
xcki
XCK
Pin
Sync
Register
Edge
Detector
UCPOL
txclk
UMSEL
xcko
DDR_XCK
rxclk
Signal description:
22.3.1
txclk
rxclk
xcki
Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko
Clock output to XCK pin (Internal Signal). Used for synchronous master operation.
fOSC
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Table 22-1.
f OSC
BAUD = ----------------------------------------16 UBRRn + 1
f OSC
-1
UBRRn = ----------------------16BAUD
f OSC
BAUD = -------------------------------------8 UBRRn + 1
f OSC
UBRRn = -------------------1
8BAUD
f OSC
BAUD = -------------------------------------2 UBRRn + 1
f OSC
UBRRn = -------------------1
2BAUD
Operating Mode
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD
fOSC
UBRRn
Some examples of UBRRn values for some system clock frequencies are found in Table 22-9 on page 223.
22.3.2
22.3.3
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section refers to
Figure 22-2 on page 202 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of metastability. The output from the synchronization register must then pass through an edge detector before it can be
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCKn clock frequency is limited by the following equation:
f OSC
f XCK ----------4
Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin
to avoid possible loss of data due to frequency variations.
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22.3.4
XCK
RxD / TxD
Sample
XCK
UCPOL = 0
RxD / TxD
Sample
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data
change. As Figure 22-3 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled
at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn
edge.
22.4
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
1 start bit
5, 6, 7, 8, or 9 data bits
1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 22-4 illustrates the possible combinations of the frame
formats. Bits inside brackets are optional.
Figure 22-4. Frame Formats
FRAME
(IDLE)
St
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St
(n)
Sp
IDLE
No transfers on the communication line (RxDn or TxDn). An IDLE line must be high.
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The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will
corrupt all ongoing communication for both the Receiver and Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode
(UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the
USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore
only be detected in the cases where the first stop bit is zero.
22.4.1
22.5
Peven
Podd
dn
USART Initialization
The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the
usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally
disabled) when doing the initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has
completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer.
Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this
purpose.
The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed
frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is
assumed to be stored in the r17:r16 Registers.
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UBRRnH, r17
sts
UBRRnL, r16
ldi
r16, (1<<U2Xn)
sts
UCRnA, r16
r16, (1<<RXENn)|(1<<TXENn)
sts UCSRnB,r16
; Set frame format: 8data, 1stop bit
ldi
r16, (2<<UMSELn)|(3<<UCSZn0)
sts
UCSRnC,r16
ret
C Code Example(1)
#define FOSC 1843200// Clock Speed
#define BAUD 9600
#define (MYUBRR FOSC/16/BAUD-1)
void main( void )
{...
USART_Init ( MYUBRR );
...} // main
void USART_Init( unsigned int ubrr){
/* Set baud rate */
UBRRH = (unsigned char)(ubrr>>8);
UBRRL = (unsigned char)ubrr;
/* Enable receiver and transmitter */
UCSRB = (1<<RXEN)|(1<<TXEN);
/* Set frame format: 8data, 2stop bit */
UCSRC = (1<<USBS)|(3<<UCSZ0);
} // USART_Init
Note:
More advanced initialization routines can be made that include frame format as parameters, disable interrupts and
so on. However, many applications use a fixed setting of the baud and control registers, and for these types of
applications the initialization code can be placed directly in the main routine, or be combined with initialization code
for other I/O modules.
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22.6
22.6.1
r17, UCSRnA
UDRn,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
;
/* Put data into buffer, sends the data */
UDRn = data;
}
Note:
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with
new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into
the buffer.
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22.6.2
UCSRnB,TXB8
sbrc r17,0
sbi
UCSRnB,TXB8
C Code Example(1)(2)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn))) )
;
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRnB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDRn = data;
}
Notes:
1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRnB
is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization.
2. See About Code Examples on page 10.
The ninth bit can be used for indicating an address frame when using multi processor communication mode or for
other protocol handling as for example synchronization.
22.6.3
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UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty
interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty
interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been
shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically
cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The
TXCn Flag is useful in half-duplex communication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART Transmit Complete
Interrupt will be executed when the TXCn Flag becomes set (provided that global interrupts are enabled). When
the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXCn Flag, this is
done automatically when the interrupt is executed.
22.6.4
Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the
transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.
22.6.5
22.7
22.7.1
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r17, UCSRnA
r16, UDRn
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
Note:
The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading
the buffer and returning the value.
22.7.2
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r17, UCSRnA
r18, UCSRnA
lds
r17, UCSRnB
lds
r16, UDRn
; If error, return -1
andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq USART_ReceiveNoError
ldi
r17, HIGH(-1)
ldi
r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr
r17
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRnA;
resh = UCSRnB;
resl = UDRn;
/* If error, return -1 */
if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
Note:
The receive function example reads all the I/O Registers into the Register File before any computation is done.
This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early
as possible.
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22.7.3
22.7.4
22.7.5
Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the
data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can
then be read by software to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is
read.
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22.7.6
22.7.7
r16, UDRn
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
Note:
22.8
22.8.1
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IDLE
START
BIT 0
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic
then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with
sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three
samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver
starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
22.8.2
BIT n
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the sample
number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels,
the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin.
The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the
Receiver only uses the first stop bit of a frame.
Figure 22-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame.
Figure 22-7. Stop Bit Sampling and Next Start Bit Sampling
RxD
STOP 1
(A)
(B)
(C)
Sample
(U2X = 0)
10
0/1
0/1
0/1
Sample
(U2X = 1)
0/1
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The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to
have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 22-7 on
page 214. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The
early start bit detection influences the operational range of the Receiver.
22.8.3
D + 2 S
R fast = ---------------------------------- D + 1 S + S M
D + 1 S
R slow = -----------------------------------------S 1 + D S + SF
D
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.
SF
mode.
First sample number used for majority voting. SF = 8 for normal speed and SF = 4 for Double Speed
SM
Middle sample number used for majority voting. SM = 9 for normal speed and SM = 5 for Double
Speed mode.
Rslow
is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud
rate. Rfast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate.
Table 22-2 and Table 22-3 on page 216 list the maximum receiver baud rate error that can be tolerated. Note that
Normal Speed mode has higher toleration of baud rate variations.
Table 22-2.
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0)
D
# (Data+Parity Bit)
Rslow (%)
Rfast (%)
Recommended max.
receiver error (%)
93.20
106.67
+6.67/-6.8
3.0
94.12
105.79
+5.79/-5.88
2.5
94.81
105.11
+5.11/-5.19
2.0
95.36
104.58
+4.58/-4.54
2.0
95.81
104.14
+4.14/-4.19
1.5
10
96.17
103.78
+3.78/-3.83
1.5
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Table 22-3.
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1)
D
# (Data+Parity Bit)
Rslow (%)
Rfast (%)
94.12
105.66
+5.66/-5.88
2.5
94.92
104.92
+4.92/-5.08
2.0
95.52
104.35
+4.35/-4.48
1.5
96.00
103.90
+3.90/-4.00
1.5
96.39
103.53
+3.53/-3.61
1.5
10
96.70
103.23
+3.23/-3.30
1.0
The recommendations of the maximum receiver baud rate error was made under the assumption that the Receiver
and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receivers system clock (XTAL) will always
have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2%
depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an
UBRR value that gives an acceptable low error can be used if possible.
22.9
22.9.1
Using MPCMn
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n)
must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXB = 0) is being transmitted. The
slave MCUs must in this case be set to use a 9-bit character frame format.
The following procedure should be used to exchange data in Multi-processor Communication mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is set).
2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs,
the RXCn Flag in UCSRnA will be set as normal.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the
MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting.
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4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave
MCUs, which still have the MPCMn bit set, will ignore the data frames.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and
waits for a new address frame from master. The process then repeats from 2.
Using any of the 5-bit to 8-bit character frame formats is possible, but impractical since the Receiver must change
between using n and n+1 character frame formats. This makes full-duplex operation difficult since the Transmitter
and Receiver uses the same character size setting. If 5-bit to 8-bit character frames are used, the Transmitter must
be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the
same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions.
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RXB[7:0]
UDRn (Read)
TXB[7:0]
UDRn (Write)
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address
referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for
data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the
Receive Data Buffer Register (RXB).
For 5-bit, 6-bit, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the
Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. Data written to UDRn
when the UDREn Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit
buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on
this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of
the FIFO.
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22.10.2
RXCn
TXCn
UDREn
FEn
DORn
UPEn
U2Xn
MPCMn
Read/Write
R/W
R/W
R/W
Initial Value
UCSRnA
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22.10.3
RXCIEn
TXCIEn
UDRIEn
RXENn
TXENn
UCSZn2
RXB8n
TXB8n
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRnB
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22.10.4
UMSELn1
UMSELn0
UPMn1
UPMn0
USBSn
UCSZn1
UCSZn0
UCPOLn
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRnC
UMSELn1
UMSELn0
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Note:
1. See USART in SPI Mode on page 227 for full description of the Master SPI Mode (MSPIM) operation.
UPMn1
UPMn0
Parity Mode
Disabled
Reserved
Stop Bit(s)
1-bit
2-bit
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Table 22-7.
UCSZn2
UCSZn1
UCSZn0
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
22.10.5
UCPOLn
15
14
13
12
11
10
UBRR[11:8]
UBRRHn
UBRR[7:0]
7
Read/Write
Initial Value
UBRRLn
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 22-9.
fosc = 1.8432MHz
fosc = 2.0000MHz
Baud
Rate
[bps]
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
25
0.2%
51
0.2%
47
0.0%
95
0.0%
51
0.2%
103
0.2%
4800
12
0.2%
25
0.2%
23
0.0%
47
0.0%
25
0.2%
51
0.2%
9600
-7.0%
12
0.2%
11
0.0%
23
0.0%
12
0.2%
25
0.2%
14.4K
8.5%
-3.5%
0.0%
15
0.0%
-3.5%
16
2.1%
19.2K
8.5%
-7.0%
0.0%
11
0.0%
-7.0%
12
0.2%
28.8K
8.5%
8.5%
0.0%
0.0%
8.5%
-3.5%
38.4K
-18.6%
8.5%
0.0%
0.0%
8.5%
-7.0%
57.6K
8.5%
8.5%
0.0%
0.0%
8.5%
8.5%
76.8K
-18.6%
-25.0%
0.0%
-18.6%
8.5%
115.2K
8.5%
0.0%
0.0%
8.5%
8.5%
230.4K
0.0%
250K
0.0%
Max.
U2Xn = 0
(1)
62.5Kbps
Note:
U2Xn = 1
125Kbps
U2Xn = 0
115.2Kbps
U2Xn = 1
230.4Kbps
U2Xn = 0
125Kbps
U2Xn = 1
250Kbps
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Table 22-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fosc = 3.6864MHz
fosc = 4.0000MHz
fosc = 7.3728MHz
Baud
Rate
[bps]
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
95
0.0%
191
0.0%
103
0.2%
207
0.2%
191
0.0%
383
0.0%
4800
47
0.0%
95
0.0%
51
0.2%
103
0.2%
95
0.0%
191
0.0%
9600
23
0.0%
47
0.0%
25
0.2%
51
0.2%
47
0.0%
95
0.0%
14.4K
15
0.0%
31
0.0%
16
2.1%
34
-0.8%
31
0.0%
63
0.0%
19.2K
11
0.0%
23
0.0%
12
0.2%
25
0.2%
23
0.0%
47
0.0%
28.8K
0.0%
15
0.0%
-3.5%
16
2.1%
15
0.0%
31
0.0%
38.4K
0.0%
11
0.0%
-7.0%
12
0.2%
11
0.0%
23
0.0%
57.6K
0.0%
0.0%
8.5%
-3.5%
0.0%
15
0.0%
76.8K
0.0%
0.0%
8.5%
-7.0%
0.0%
11
0.0%
115.2K
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
230.4K
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
250K
-7.8%
-7.8%
0.0%
0.0%
-7.8%
-7.8%
0.5M
-7.8%
0.0%
-7.8%
-7.8%
1M
-7.8%
Max.
U2Xn = 0
(1)
230.4Kbps
Note:
U2Xn = 1
460.8Kbps
U2Xn = 0
250Kbps
U2Xn = 1
0.5Mbps
U2Xn = 0
460.8Kbps
U2Xn = 1
921.6Kbps
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Table 22-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fosc = 11.0592MHz
fosc = 8.0000MHz
fosc = 14.7456MHz
Baud
Rate
[bps]
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
207
0.2%
416
-0.1%
287
0.0%
575
0.0%
383
0.0%
767
0.0%
4800
103
0.2%
207
0.2%
143
0.0%
287
0.0%
191
0.0%
383
0.0%
9600
51
0.2%
103
0.2%
71
0.0%
143
0.0%
95
0.0%
191
0.0%
14.4K
34
-0.8%
68
0.6%
47
0.0%
95
0.0%
63
0.0%
127
0.0%
19.2K
25
0.2%
51
0.2%
35
0.0%
71
0.0%
47
0.0%
95
0.0%
28.8K
16
2.1%
34
-0.8%
23
0.0%
47
0.0%
31
0.0%
63
0.0%
38.4K
12
0.2%
25
0.2%
17
0.0%
35
0.0%
23
0.0%
47
0.0%
57.6K
-3.5%
16
2.1%
11
0.0%
23
0.0%
15
0.0%
31
0.0%
76.8K
-7.0%
12
0.2%
0.0%
17
0.0%
11
0.0%
23
0.0%
115.2K
8.5%
-3.5%
0.0%
11
0.0%
0.0%
15
0.0%
230.4K
8.5%
8.5%
0.0%
0.0%
0.0%
0.0%
250K
0.0%
0.0%
-7.8%
-7.8%
-7.8%
5.3%
0.5M
0.0%
0.0%
-7.8%
-7.8%
-7.8%
1M
0.0%
-7.8%
-7.8%
Max.
U2Xn = 0
(1)
0.5Mbps
Note:
U2Xn = 1
1Mbps
U2Xn = 0
691.2Kbps
U2Xn = 1
1.3824Mbps
U2Xn = 0
921.6Kbps
U2Xn = 1
1.8432Mbps
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Table 22-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fosc = 16.0000MHz
fosc = 18.4320MHz
fosc = 20.0000MHz
Baud
Rate
[bps]
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
416
-0.1%
832
0.0%
479
0.0%
959
0.0%
520
0.0%
1041
0.0%
4800
207
0.2%
416
-0.1%
239
0.0%
479
0.0%
259
0.2%
520
0.0%
9600
103
0.2%
207
0.2%
119
0.0%
239
0.0%
129
0.2%
259
0.2%
14.4K
68
0.6%
138
-0.1%
79
0.0%
159
0.0%
86
-0.2%
173
-0.2%
19.2K
51
0.2%
103
0.2%
59
0.0%
119
0.0%
64
0.2%
129
0.2%
28.8K
34
-0.8%
68
0.6%
39
0.0%
79
0.0%
42
0.9%
86
-0.2%
38.4K
25
0.2%
51
0.2%
29
0.0%
59
0.0%
32
-1.4%
64
0.2%
57.6K
16
2.1%
34
-0.8%
19
0.0%
39
0.0%
21
-1.4%
42
0.9%
76.8K
12
0.2%
25
0.2%
14
0.0%
29
0.0%
15
1.7%
32
-1.4%
115.2K
-3.5%
16
2.1%
0.0%
19
0.0%
10
-1.4%
21
-1.4%
230.4K
8.5%
-3.5%
0.0%
0.0%
8.5%
10
-1.4%
250K
0.0%
0.0%
-7.8%
2.4%
0.0%
0.0%
0.5M
0.0%
0.0%
-7.8%
0.0%
1M
0.0%
0.0%
Max.
U2Xn = 0
(1)
1Mbps
Note:
U2Xn = 1
2Mbps
U2Xn = 0
1.152Mbps
U2Xn = 1
2.304Mbps
U2Xn = 0
1.25Mbps
U2Xn = 1
2.5Mbps
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23.1
Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master
control logic takes direct control over the USART resources. These resources include the transmitter and receiver
shift register and buffers, and the baud rate generator. The parity generator and checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a
common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both
modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers
changes when using MSPIM.
23.2
However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode
is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation is supported by the USART in MSPIM mode, the following features differ between the two modules:
The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer
The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode
The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting
UBRRn accordingly
Pin control differs due to the master only operation of the USART in MSPIM mode
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 23-4 on page 235.
23.2.1
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode
of operation only internal clock generation (that is, master operation) is supported. The Data Direction Register for
the XCKn pin (DDR_XCKn) must therefore be set to one (that is, as output) for the USART in MSPIM to operate
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correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (that is, TXENn and
RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The
baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 23-1.
Table 23-1.
Operating Mode
f OSC
BAUD = -------------------------------------2 UBRRn + 1
f OSC
UBRRn = -------------------1
2BAUD
Note:
BAUD
fOSC
UBRRn
UCPOLn
UCPHAn
SPI Mode
Leading Edge
Trailing Edge
Sample (Rising)
Setup (Falling)
Setup (Rising)
Sample (Falling)
Sample (Falling)
Setup (Rising)
Setup (Falling)
Sample (Rising)
UCPHA=1
UCPOL=0
UCPHA=0
23.3
1. The baud rate is defined to be the transfer rate in bit per second (bps).
UCPOL=1
XCK
XCK
XCK
XCK
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23.4
Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two
valid frame formats:
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame
can directly follow it, or the communication line can be set to an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing
communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will
then signal that the 16-bit value has been shifted out.
23.4.1
To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the
transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired
value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before
enabling the transmitter is not necessary if the initialization is done immediately after a reset since UBRRn is reset to
zero.
Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the
Transmitter has completed all transfers, and the RXCn Flag can be used to check that there are no unread data in
the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it
is used for this purpose.
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The following simple USART initialization code examples show one assembly and one C function that are equal in
functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers.
Assembly Code Example(1)
USART_Init:
clr r18
out UBRRnH,r18
out UBRRnL,r18
; Setting the XCKn port pin as output, enables master mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18
; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18
; Set baud rate.
; IMPORTANT: The Baud Rate must be set after the transmitter is
enabled!
out UBRRnH, r17
out UBRRnL, r18
ret
C Code Example(1)
void USART_Init( unsigned int baud )
{
UBRRn = 0;
/* Setting the XCKn port pin as output, enables master mode. */
XCKn_DDR |= (1<<XCKn);
/* Set MSPI mode of operation and SPI data mode 0. */
UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);
/* Enable receiver and transmitter. */
UCSRnB = (1<<RXENn)|(1<<TXENn);
/* Set baud rate. */
/* IMPORTANT: The Baud Rate must be set after the transmitter is
enabled */
UBRRn = baud;
}
Note:
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23.5
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, that is, the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and
given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the
RXENn bit in the UCSRnB register to one. When the receiver is enabled, the normal pin operation of the RxDn pin
is overridden and given the function as the Receiver's serial input. The XCKn will in both cases be used as the
transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O
location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The
data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send
a new frame.
Note:
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for
each byte transmitted. The input buffer operation is identical to normal USART mode, that is, if an overflow occurs the
character last received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1
first, then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will
be lost, and not byte 1.
The following code examples show a simple USART in MSPIM mode transfer function based on polling of the Data
Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The USART has to be initialized before the
function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16 and the
data received will be available in the same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with
new data to be transmitted. The function then waits for data to be present in the receive buffer by checking the
RXCn Flag, before reading the buffer and returning the value.
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C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) );
/* Put data into buffer, sends the data */
UDRn = data;
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) );
/* Get and return received data from buffer */
return UDRn;
}
Note:
23.5.1
23.5.2
23.6
23.6.1
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23.6.2
Bit
RXCn
TXCn
UDREn
0
-
Read/Write
R/W
R/W
R/W
Initial Value
UCSRnA
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23.6.3
Bit
RXCIEn
TXCIEn
UDRIE
RXENn
TXENn
0
-
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRnB
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23.6.4
Bit
UMSELn1
UMSELn0
UDORDn
UCPHAn
UCPOLn
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRnC
UMSELn1
UMSELn0
Mode
Asynchronous USART
Synchronous USART
(Reserved)
USART_MSPIM
SPI
Comment
TxDn
MOSI
RxDn
MISO
Master In only
XCKn
SCK
(Functionally identical)
(N/A)
SS
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Features
24.2
Simple yet Powerful and Flexible Communication Interface, only two Bus Lines needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
24.2.1
TWI Terminology
The following definitions are frequently encountered in this section.
Table 24-1.
TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission. The Master also generates the SCL clock
Slave
Transmitter
Receiver
The Power Reduction TWI bit, PRTWI bit in PRR0 Power Reduction Register 0 on page 55 must be written to
zero to enable the 2-wire Serial Interface.
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24.2.2
Electrical Interconnection
As depicted in Figure 24-1 on page 236, both bus lines are connected to the positive supply voltage through pull-up
resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wiredAND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when
one or more TWI devices output a zero. A high level is output when all TWI devices trim-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and
the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in SPI
Timing Characteristics on page 363. Two different sets of specifications are presented there, one relevant for bus
speeds below 100kHz, and one valid for bus speeds up to 400kHz.
24.3
24.3.1
SDA
SCL
Data Stable
Data Stable
Data Change
24.3.2
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SDA
SCL
START
24.3.3
STOP
REPEATED START
START
STOP
Addr LSB
R/W
ACK
SDA
SCL
1
START
24.3.4
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Data LSB
ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
SLA+R/W
24.3.5
STOP, REPEATED
START or Next
Data Byte
Data Byte
Addr MSB
Addr LSB
R/W
ACK
Data MSB
Data LSB
ACK
SDA
SCL
1
START
24.4
SLA+R/W
7
Data Byte
STOP
An algorithm must be implemented allowing only one of the masters to complete the transmission. All other
masters should cease transmission when they discover that they have lost the selection process. This
selection process is called arbitration. When a contending master discovers that it has lost the arbitration
process, it should immediately switch to Slave mode to check whether it is being addressed by the winning
master. The fact that multiple masters have started transmission at the same time should not be detectable to
the slaves, that is, the data being transferred on the bus must not be corrupted.
Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial
clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the
arbitration process.
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The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be
wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high
period. The low period of the combined clock is equal to the low period of the Master with the longest low period.
Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods
when the combined SCL line goes high or low, respectively.
Figure 24-7. SCL Synchronization Between Multiple Masters
TA low
TA high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow
Masters Start
Counting Low Period
TBhigh
Masters Start
Counting High Period
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read
from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master
can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing
Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA
line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several
masters are trying to address the same Slave, arbitration will continue into the data packet.
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Master A Loses
Arbitration, SDAA SDA
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
It is the user softwares responsibility to ensure that these illegal arbitration conditions never occur. This implies
that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In
other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
24.5
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SCL
Spike
Filter
Slew-rate
Control
Spike
Filter
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Address Comparator
24.5.1
Ack
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
TWI Unit
Slew-rate
Control
SDA
24.5.2
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Note:
24.5.3
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See 2-wire
Serial Interface Characteristics on page 361 for value of pull-up resistor.
24.5.4
24.5.5
Control Unit
The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt
Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code
identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted.
At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its
tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
After the TWI has been addressed by own slave address or general call
After a STOP or REPEATED START has been received while still addressed as a Slave
When a bus error has occurred due to an illegal START or STOP condition
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24.6
Application
Action
TWI
Hardware
Action
TWI bus
START
2. TWINT set.
Status code indicates
START condition sent
SLA+W
4. TWINT set.
Status code indicates
SLA+W sent, ACK
received
Data
6. TWINT set.
Status code indicates
data sent, ACK received
STOP
Indicates
TWINT set
1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value
into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described
later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT
clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately
after the application has cleared TWINT, the TWI will initiate transmission of the START condition.
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated
with a status code indicating that the START condition has successfully been sent.
3. The application software should now examine the value of TWSR, to make sure that the START condition
was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must
load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been
loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to
transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start
any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared
TWINT, the TWI will initiate transmission of the address packet.
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4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated
with a status code indicating that the address packet has successfully been sent. The status code will also
reflect whether a Slave acknowledged the packet or not.
5. The application software should now examine the value of TWSR, to make sure that the address packet
was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that
the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in
TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the
value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the
TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a
status code indicating that the data packet has successfully been sent. The status code will also reflect
whether a Slave acknowledged the packet or not.
7. The application software should now examine the value of TWSR, to make sure that the data packet was
successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise,
the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware
to transmit a STOP condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the
TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition
has been sent.
Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows:
When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL
line is pulled low until TWINT is cleared.
When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI
bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle.
After all TWI Register updates and other pending application software tasks have been completed, TWCR is
written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will
then commence executing whatever operation was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code below assumes that
several definitions have been made, for example by using include-files.
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ldi r16,
(1<<TWINT)|(1<<TWSTA)|
C Example
TWCR = (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
(1<<TWEN)
2
r16,TWCR
out
TWDR, r16
r16, START
brne ERROR
ldi r16, SLA_W
r16,TWCR
r16, MT_SLA_ACK
brne ERROR
ldi r16, DATA
out
TWDR, r16
r16,TWCR
TWCR = (1<<TWINT) |
(1<<TWEN);
r16, MT_DATA_ACK
brne ERROR
ldi r16,
(1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out
TWDR = DATA;
TWCR = (1<<TWINT) |
(1<<TWEN);
sbrs r16,TWINT
rjmp wait3
in
r16,TWSR
TWDR = SLA_W;
sbrs r16,TWINT
rjmp wait2
in
r16,TWSR
sbrs r16,TWINT
rjmp wait1
in
r16,TWSR
Comments
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO);
TWCR, r16
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24.7
Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver
(MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back
from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and
then SR mode would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described along with figures
detailing data transmission in each of the modes. These figures contain the following abbreviations:
S:
START condition
Rs:
R:
W:
A:
A:
STOP condition
Device 1
Device 2
MASTER
TRANSMITTER
SLAVE
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
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TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and
generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the
TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 24-2 on page 249). In order
to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT
bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following
value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a
number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The
appropriate action to be taken for each of these status codes is detailed in Table 24-2 on page 249.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the
data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the
Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a
new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves,
Master Transmitter mode and Master Receiver mode without losing control of the bus.
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Table 24-2.
Status Code
(TWSR)
Prescaler Bits
are 0
To/from TWDR
0x08
0x10
0x18
0x20
0x28
0x30
0x38
To TWCR
STA
STO
TWIN
T
TWE
A
Load SLA+W
Load SLA+W or
Load SLA+R
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action
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Successfull
transmission
to a slave
receiver
SLA
$08
DATA
$18
$28
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$20
MR
Not acknowledge
received after a data
byte
$30
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
$68
24.7.2
A or A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
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Device 1
Device 2
MASTER
RECEIVER
SLAVE
TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a
START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the 2-wire Serial Bus and
generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the
TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 24-2 on page 249). In order
to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value
to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a
number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The
appropriate action to be taken for each of these status codes is detailed in Table 24-3 on page 252. Received data
can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until
the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a
new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves,
Master Transmitter mode and Master Receiver mode without losing control over the bus.
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Table 24-3.
Status Code
(TWSR)
Prescaler Bits
are 0
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
0x08
Load SLA+R
0x10
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
0
0
1
1
1
X
X
0x38
0x40
0x48
0x50
0x58
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Successfull
reception
from a slave
receiver
SLA
DATA
$40
$08
DATA
$50
$58
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$48
MT
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
$68
24.7.3
$38
Other master
continues
$78
To corresponding
states in slave mode
$B0
DATA
Other master
continues
Device 1
Device 2
SLAVE
RECEIVER
MASTER
TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
value
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
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The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call
address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the devices own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the
general call address if enabled) followed by the data direction bit. If the direction bit is 0 (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received,
the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the
appropriate software action. The appropriate action to be taken for each status code is detailed in Table 24-4 on
page 255. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode
(see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a Not Acknowledge (1) to SDA after the next
received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA
is zero, the TWI does not acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored and
address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as
a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up
and until the TWINT Flag is cleared (by writing it to one). Further data reception will be carried out as normal, with
the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be
held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus when
waking up from these Sleep modes.
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Table 24-4.
Status Code
(TWSR)
Prescaler Bits
are 0
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
No TWDR action or
0x60
No TWDR action
0x68
No TWDR action or
No TWDR action
0x70
No TWDR action or
No TWDR action
0x78
No TWDR action or
No TWDR action
0x80
0x88
0x90
0x98
No action
0xA0
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SLA
DATA
$60
DATA
$80
P or S
$80
$A0
P or S
$88
Arbitration lost as master
and addressed as slave
$68
Reception of the general call
address and one or more data
bytes
General Call
DATA
$70
DATA
$90
P or S
$90
$A0
P or S
$98
Arbitration lost as master and
addressed as slave by general call
$78
DATA
24.7.4
Device 1
Device 2
SLAVE
TRANSMITTER
MASTER
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
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To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
TWA4
value
TWA3
TWA2
TWA1
TWA0
TWGCE
The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call
address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the devices own slave address or the general call address. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the
general call address if enabled) followed by the data direction bit. If the direction bit is 1 (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received,
the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the
appropriate software action. The appropriate action to be taken for each status code is detailed in Table 24-5. The
Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state
0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or
state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final
byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer.
Thus the Master Receiver receives all 1 as serial data. State 0xC8 is entered if the Master demands additional
data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting
NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still
monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may
be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as
a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake
up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out as normal,
with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line
may be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus when
waking up from these sleep modes.
Table 24-5.
Status Code
(TWSR)
Prescaler
Bits
are 0
0xA8
0xB0
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
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Table 24-5.
0xB8
0xC0
0xC8
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
SLA
DATA
$A8
Arbitration lost as master
and addressed as slave
DATA
$B8
P or S
$C0
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
All 1's
P or S
$C8
24.7.5
DATA
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 24-6 on page 259.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs
between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus error occurs when a
START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are
during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT
is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to
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it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
Table 24-6.
Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
No TWDR action
0x00
No TWDR action
24.7.6
STA
STO
TWIN
T
TWE
A
No TWCR action
0
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
SLA+W
ADDRESS
S = START
Rs
SLA+R
Rs = REPEATED START
24.8
Master Receiver
DATA
P = STOP
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Device 1
Device 2
Device 3
MASTER
TRANSMITTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device n
R1
R2
SDA
SCL
Two or more masters are performing identical communication with the same Slave. In this case, neither the
Slave nor any of the masters will know about the bus contention.
Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration
will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while
another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode
or wait until the bus is free and transmit a new START condition, depending on application software action.
Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing
arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not
being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new
START condition, depending on application software action.
This is summarized in Figure 24-21. Possible status values are given in circles.
Figure 24-21. Possible Status Codes Caused by Arbitration
START
SLA
Data
Own
Address / General Call
received
No
STOP
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Yes
Direction
Write
68/78
Read
B0
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
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24.9
24.9.1
Register Description
TWBR TWI Bit Rate Register
Bit
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xB8)
TWBR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xBC)
TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by
applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to
control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write
collision if data is attempted written to TWDR while the register is inaccessible.
Bit 7 TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response. If
the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag
is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it.
Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that
clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status
Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
Bit 6 TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is
generated on the TWI bus if the following conditions are met:
1. The devices own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily.
Address recognition can then be resumed by writing the TWEA bit to one again.
Bit 5 TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI
hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the
bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to
claim the bus Master status. TWSTA must be cleared by software when the START condition has been
transmitted.
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TWS7
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
Read/Write
R/W
R/W
Initial Value
(0xB9)
TWSR
TWPS1
TWPS0
Prescaler Value
16
64
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To calculate bit rates, see Bit Rate Generator Unit on page 242. The value of TWPS1:0 is used in the equation.
24.9.4
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xBB)
TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last
byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt
Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus
is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a
sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the
TWI logic, the CPU cannot access the ACK bit directly.
Bits 7:0 TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial
Bus.
24.9.5
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0xBA)
TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the
TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In
multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address
comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a
match is found, an interrupt request is generated.
Bits 7:1 TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
Bit 0 TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
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24.9.6
(0xBD)
TWAM[6:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TWAMR
TWAR0
Address
Match
Address
Bit 0
TWAMR0
Address Bit Comparator 0
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ACME
ADEN
ADC MULTIPLEXER
OUTPUT (1)
Note:
25.1
ACME
ADEN
MUX5
MUX2:0
xxx
AIN1
xxx
AIN1
000
ADC0
001
ADC1
010
ADC2
011
ADC3
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Table 25-1.
25.2
25.2.1
ACME
ADEN
MUX5
MUX2:0
100
ADC4
101
ADC5
110
ADC6
111
ADC7
000
ADC8
001
ADC9
010
ADC10
011
ADC11
100
ADC12
101
ADC13
110
ADC14
111
ADC15
Register Description
ADCSRB ADC Control and Status Register B
Bit
(0x7B)
ACME
MUX5
ADTS2
ADTS1
ADTS0
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
ADCSRB
0x30 (0x50)
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
ACSR
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ACIS1/ACIS0 Settings
Interrupt Mode
ACIS1
ACIS0
Reserved
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
25.2.3
(0x7F)
AIN1D
AIN0D
Read/Write
R/W
R/W
Initial Value
DIDR1
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Features
10-bit Resolution
1 LSB Integral Non-linearity
2 LSB Absolute Accuracy
13s - 260s Conversion Time
Up to 76.9kSPS (Up to 15kSPS at Maximum Resolution)
16 Multiplexed Single Ended Input Channels
14 Differential input channels
4 Differential Input Channels with Optional Gain of 10 and 200
Optional Left Adjustment for ADC Result Readout
0V - VCC ADC Input Voltage Range
2.7V - VCC Differential ADC Voltage Range
Selectable 2.56V or 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
The ATmega640/1280/1281/2560/2561 features a 10-bit successive approximation ADC. The ADC is connected to
an 8/16-channel Analog Multiplexer which allows eight/sixteen single-ended voltage inputs constructed from the
pins of Port F and Port K. The single-ended voltage inputs refer to 0V (GND).
The device also supports 16/32 differential voltage input combinations. Four of the differential inputs (ADC1 &
ADC0, ADC3 & ADC2, ADC9 & ADC8 and ADC11 & ADC10) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1), 20 dB (10) or 46 dB (200) on the differential input voltage before the ADC
conversion. The 16 channels are split in two sections of 8 channels where in each section seven differential analog
input channels share a common negative terminal (ADC1/ADC9), while any other ADC input in that section can be
selected as the positive input terminal. If 1 or 10 gain is used, 8 bit resolution can be expected. If 200 gain is
used, 7 bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant
level during conversion. A block diagram of the ADC is shown in Figure 26-1 on page 269.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See
the paragraph ADC Noise Canceler on page 275 on how to connect this pin.
Internal reference voltages of nominally 1.1V, 2.56V or AVCC are provided On-chip. The voltage reference may be
externally decoupled at the AREF pin by a capacitor for better noise performance.
The Power Reduction ADC bit, PRADC, in PRR0 Power Reduction Register 0 on page 55 must be disabled by
writing a logical zero to enable the ADC.
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ADFR
ADSC
ADC[9:0]
ADIF
ADPS[2:0]
ADEN
MUX[5]
DIFF / GAIN SELECT
CHANNEL SELECTION
INTERNAL
REFERENCE
(1.1V/2.56V)
TRIGGER
SELECT
START
PRESCALER
MUX DECODER
AVCC
15
ADLAR
MUX[4:0]
REFS[1:0]
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
8-BIT DATABUS
CONVERSION LOGIC
10-bit DAC
AREF
GAIN
AMPLIFIER
ADC[15:0]
BANDGAP (1.1V)
REFERENCE
ADC
MULTIPLEXER
OUTPUT
GND
26.2
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB.
Optionally, AVCC or an internal 1.1V or 2.56V reference voltage may be connected to the AREF pin by writing to
the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX and ADCSRB. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A
selection of ADC input pins can be selected as positive and negative inputs to the differential amplifier.
If differential channels are selected, the voltage difference between the selected input channel pair then becomes
the analog input to the ADC. If single ended channels are used, the amplifier is bypassed altogether.
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The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and
a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
26.3
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive
edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a
new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge
will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt
Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event.
Figure 26-2. ADC Auto Trigger Logic
ADTS[2:0]
PRESCALER
START
ADIF
CLKADC
ADATE
SOURCE 1
.
.
.
.
SOURCE n
CONVERSION
LOGIC
EDGE
DETECTOR
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
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this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is
cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
Reset
7-BIT ADC PRESCALER
CK/64
CK/128
CK/32
CK/8
CK/16
CK/4
CK
CK/2
26.4
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz. If
a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be as high as 1000kHz to get a
higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as
the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage to stabilize. If not stabilized, the first value read after the first conversion may be wrong.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC
clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC
Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may
then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from
the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles
after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization
logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC
remains high. For a summary of conversion times, see Table 26-1 on page 273.
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Figure 26-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
Conversion
First Conversion
Cycle Number
12
13
14
16
15
17
18
19
20
21
22
23
24
25
ADC Clock
ADEN
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
Conversion
Complete
Cycle Number
Next Conversion
10
11
12
13
ADC Clock
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
Sample & Hold
Conversion
Complete
Cycle Number
Next Conversion
10
11
12
13
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
LSB of Result
Prescaler
Reset
Sample &
Hold
Conversion
Complete
Prescaler
Reset
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Cycle Number
11
12
Next Conversion
13
ADC Clock
ADSC
ADIF
ADCH
ADCL
LSB of Result
Conversion
Complete
Table 26-1.
Conversion Time
(Cycles)
First conversion
13.5
25
1.5
13
13.5
1.5/2.5
13/14
Condition
26.4.1
Differential Channels
When using differential channels, certain aspects of the conversion need to be taken into consideration.
Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific
phase of CKADC2. A conversion initiated by the user (that is, all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles
from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock
cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initiated immediately
after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (that is, all
but the first) Free Running conversions will take 14 ADC clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off
between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started.
Since the stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to 0 then to 1), only
extended conversions are performed. The result from the extended conversions will be valid. See Prescaling and
Conversion Timing on page 271 for timing details.
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26.5
26.5.1
26.5.2
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AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly
connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor
between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
Note that VREF is a high impedant source, and only a capacitive load should be connected in a system. The Internal
2.56V reference is generated from the 1.1V reference.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage
options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the
AREF pin, the user may switch between AVCC, 1.1V and 2.56V as reference selection. The first ADC conversion
result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
If differential channels are used, the selected reference should not be closer to AVCC than indicated in ADC Characteristics Preliminary Data on page 365.
26.6
26.6.1
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IIH
ADCn
1..100k
CS/H= 14pF
IIL
VCC/2
Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques:
1. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and
keep them well away from high-speed switching digital tracks.
2. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network
as shown in Figure 26-9.
3. Use the ADC noise canceler function to reduce induced noise from the CPU.
4. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress.
Figure 26-9. ADC Power Connections, ATmega1281/2561.
PA0
VCC
10
53
(ADC7) PF7
54
(ADC6) PF6
55
(ADC5) PF5
56
(ADC4) PF4
57
(ADC3) PF3
58
(ADC2) PF2
59
(ADC1) PF1
60
(ADC0) PF0
61
AREF
62
AVCC
Ground Plane
52
GND
GND
100nF
100nF
51
63
64
1
PG5
26.6.2
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79
VCC
80
GND
81
(ADC15/PCINT23) PK7
82
(ADC14/PCINT22) PK6
83
(ADC13/PCINT21) PK5
84
(ADC12/PCINT20) PK4
85
(ADC11/PCINT19) PK3
86
(ADC10/PCINT18) PK2
87
(ADC9/PCINT17) PK1
88
(ADC8/PCINT16) PK0
89
(ADC7/TDI) PF7
90
(ADC6/TDO) PF6
91
(ADC5/TMS) PF5
92
(ADC4/TCK) PF4
93
(ADC3) PF3
94
(ADC2) PF2
95
(ADC1) PF1
96
(ADC0) PF0
97
AREF
98
10
GND
99
AVCC
100
Ground Plane
26.6.3
(OC0B) PG5
100nF
26.6.4
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal
value: 0 LSB.
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Ideal ADC
Actual ADC
Offset
Error
Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to
0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB.
Gain
Error
Ideal ADC
Actual ADC
Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an
actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
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INL
Ideal ADC
Actual ADC
VREF
Input Voltage
Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two
adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
1 LSB
DNL
0x000
0
Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.
Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization
error. Ideal value: 0.5 LSB.
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26.7
0x000
- VREF
0x3FF
VREF
Differential Input
Voltage (Volts)
0x200
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Table 26-2.
VADCn
Read Code
0x1FF
511
0x1FF
511
0x1FE
510
...
...
...
0x001
VADCm
0x000
0x3FF
-1
...
...
...
0x201
-511
0x200
-512
Example:
ADMUX = 0xFB (ADC3 - ADC2, 10 gain, 2.56V reference, left adjusted result).
Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV.
ADCR = 512 10 (300 - 500) / 2560 = -400 = 0x270.
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70,
ADCH = 0x02.
26.8
26.8.1
Register Description
ADMUX ADC Multiplexer Selection Register
Bit
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x7C)
ADMUX
REFS1
REFS0
Note:
1. If 10x or 200x gain is selected, only 2.56V should be used as Internal Voltage Reference. For differential conversion, only 1.1V cannot be used as internal voltage reference.
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(0x7B)
ACME
MUX5
ADTS2
ADTS1
ADTS0
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
ADCSRB
MUX5:0
000000
ADC0
000001
ADC1
000010
ADC2
000011
ADC3
000100
ADC4
000101
ADC5
000110
ADC6
000111
ADC7
Gain
N/A
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Table 26-4.
MUX5:0
Gain
(1)
ADC0
ADC0
10
(1)
ADC1
ADC0
10
(1)
001010
ADC0
ADC0
200
001011(1)
ADC1
ADC0
200
(1)
ADC2
ADC2
10
(1)
ADC3
ADC2
10
(1)
001110
ADC2
ADC2
200
001111(1)
ADC3
ADC2
200
ADC0
ADC1
010001
ADC1
ADC1
010010
ADC2
ADC1
010011
ADC3
ADC1
010100
ADC4
ADC1
010101
ADC5
ADC1
010110
ADC6
ADC1
010111
ADC7
ADC1
011000
ADC0
ADC2
011001
ADC1
ADC2
011010
ADC2
ADC2
ADC3
ADC2
011100
ADC4
ADC2
011101
ADC5
ADC2
001000
001001
001100
001101
010000
N/A
011011
N/A
011110
1.1V (VBG)
011111
0V (GND)
100000
ADC8
100001
ADC9
100010
ADC10
100011
ADC11
100100
ADC12
100101
ADC13
100110
ADC14
100111
ADC15
N/A
N/A
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Table 26-4.
MUX5:0
Gain
(1)
ADC8
ADC8
10
(1)
ADC9
ADC8
10
(1)
101010
ADC8
ADC8
200
101011(1)
101000
101001
ADC9
ADC8
200
(1)
ADC10
ADC10
10
(1)
ADC11
ADC10
10
(1)
101110
ADC10
ADC10
200
101111(1)
ADC11
ADC10
200
110000
ADC8
ADC9
110001
ADC9
ADC9
ADC10
ADC9
110011
ADC11
ADC9
110100
ADC12
ADC9
110101
ADC13
ADC9
110110
ADC14
ADC9
110111
ADC15
ADC9
111000
ADC8
ADC10
111001
ADC9
ADC10
111010
ADC10
ADC10
111011
ADC11
ADC10
111100
ADC12
ADC10
ADC13
ADC10
101100
101101
110010
N/A
111101
N/A
111110
Reserved
N/A
111111
Reserved
N/A
Note:
1. To reach the given accuracy, 10 or 200 Gain should not be used for operating voltage below 2.7V.
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26.8.3
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x7A)
ADCSRA
ADPS2
ADPS1
ADPS0
Division Factor
16
32
64
128
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26.8.4
26.8.4.1
ADLAR = 0
Bit
15
14
13
12
11
10
(0x79)
ADC9
ADC8
ADCH
(0x78)
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
Read/Write
Initial Value
26.8.4.2
ADLAR = 1
Bit
15
14
13
12
11
10
(0x79)
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
(0x78)
ADC1
ADC0
ADCL
Read/Write
Initial Value
When an ADC conversion is complete, the result is found in these two registers. If differential channels are used,
the result is presented in twos complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ADC Conversion Result on page 280.
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26.8.5
(0x7B)
ACME
MUX5
ADTS2
ADTS1
ADTS0
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
ADCSRB
ADTS1
ADTS0
Analog Comparator
Timer/Counter0 Overflow
Timer/Counter1 Overflow
Note:
26.8.6
Free running mode cannot be used for differential channels (see chapter Differential Channels on page 273).
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x7E)
DIDR0
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26.8.7
ADC15D
ADC14D
ADC13D
ADC12D
ADC11D
ADC10D
ADC9D
ADC8D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
(0x7D)
DIDR2
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Features
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
All Internal Peripheral Units
Internal and External RAM
The Internal Register File
Program Counter
EEPROM and Flash Memories
Extensive On-chip Debug Support for Break Conditions, Including
AVR Break Instruction
Break on Change of Program Memory Flow
Single Step Break
Program Memory Break Points on Single Address or Address Range
Data Memory Break Points on Single Address or Address Range
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
27.2
Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
On-chip debugging
A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface,
and using the Boundary-scan Chain can be found in the sections Programming via the JTAG Interface on page
342 and IEEE 1149.1 (JTAG) Boundary-scan on page 295, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within Atmel and to selected third party vendors only.
Figure 27-1 on page 290 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP
Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG
Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI input
and TDO output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used for board-level testing. The JTAG Programming Interface (actually consisting of several physical and virtual Data Registers) is used
for serial programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for
On-chip debugging only.
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DEVICE BOUNDARY
TDI
TDO
TCK
TMS
JTAG PROGRAMMING
INTERFACE
TAP
CONTROLLER
AVR CPU
INSTRUCTION
REGISTER
ID
REGISTER
M
U
X
FLASH
MEMORY
Address
Data
BREAKPOINT
UNIT
BYPASS
REGISTER
INTERNAL
SCAN
CHAIN
PC
Instruction
FLOW CONTROL
UNIT
DIGITAL
PERIPHERAL
UNITS
ANALOG
PERIPHERIAL
UNITS
Analog inputs
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
OCD STATUS
AND CONTROL
I/O PORT n
27.3
TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains)
TDO: Test Data Out. Serial output data from Instruction Register or Data Register
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST Test ReSeT which is not provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in
reset. When programmed, the input TAP signals are internally pulled high and the JTAG is enabled for Boundaryscan and programming. The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the whole
system, assuming only open collectors on the reset line are used in the application.
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Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
0
0
Pause-DR
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
27.3.1
Exit1-IR
Shift-IR
Update-IR
0
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry,
JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 27-2 depend on
the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register
Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction Register
from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in
order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting
TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the
TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls
the circuitry surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel
output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only
used for navigating the state machine.
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At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register ShiftDR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the
JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR
state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in
when this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel
inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched
parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states
are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction
and using Data Registers, and some JTAG instructions may select certain functions to be performed in the RunTest/Idle, making it unsuitable as an Idle state.
Note:
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS
high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in Bibliography on page 294.
27.4
27.5
A scan chain on the interface between the internal AVR CPU and the internal peripheral units
All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions
via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part
of the communication interface between the CPU and the JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two Program Memory
Break Points, and two combined Break Points. Together, the four Break Points can be configured as either:
3 Single Program Memory Break Point + 1 single Data Memory Break Point
2 single Program Memory Break Points + 2 single Data Memory Break Points
2 single Program Memory Break Points + 1 Program Memory Break Point with mask (range Break Point)
2 single Program Memory Break Points + 1 Data Memory Break Point with mask (range Break Point)
A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving
less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in On-chip Debug Specific JTAG Instructions on
page 293.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must
be programmed and no Lock bits must be set for the On-chip debug system to work. As a security feature, the Onchip debug system is disabled when either of the LB1 or LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug
capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio supports source level
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execution of Assembly programs assembled with Atmel Corporations AVR Assembler and C programs compiled
with third party vendors compilers.
AVR Studio runs under Microsoft Windows 95/98/2000 and Microsoft Windows NT.
For a full description of the AVR Studio, refer to the AVR Studio User Guide. Only highlights are presented in this
document.
All necessary execution commands are available in AVR Studio, both on source level and on disassembly level.
The user can execute the program, single step through the code either by tracing into or stepping over functions,
step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have an unlimited number of code Break Points (using
the BREAK instruction) and up to two data memory Break Points, alternatively combined as a mask (range) Break
Point.
27.6
27.6.1
PRIVATE0; 0x8
Private JTAG instruction for accessing On-chip debug system.
27.6.2
PRIVATE1; 0x9
Private JTAG instruction for accessing On-chip debug system.
27.6.3
PRIVATE2; 0xA
Private JTAG instruction for accessing On-chip debug system.
27.6.4
PRIVATE3; 0xB
Private JTAG instruction for accessing On-chip debug system.
27.7
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the
OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no
back-door exists for reading out the content of a secured device.
The details on programming through the JTAG interface and programming specific JTAG instructions are given in
the section Programming via the JTAG Interface on page 342.
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27.8
Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
27.9
27.9.1
IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992
0x31 (0x51)
MSB/IDRD
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OCDR
The OCDR Register provides a communication channel from the running program in the microcontroller to the
debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal
flag; I/O Debug Register Dirty IDRD is set to indicate to the debugger that the register has been written. When
the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The
debugger clears the IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only
be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all
other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
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Features
28.2
System Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well
as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level,
all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An
external controller sets up the devices to drive values at their output pins, and observe the input values received
from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan
provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using
the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and
EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the ID-Code of the device, since IDCODE is the
default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs
to the device may be determined by the scan operations, and the internal software may be in an undetermined
state when exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high impedance
state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the
shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the
output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-Register.
Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for
taking a snapshot of the external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be cleared to enable
the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal
chip frequency is possible. The chip clock is not required to run.
28.3
Data Registers
The Data Registers relevant for Boundary-scan operations are:
Bypass Register
Reset Register
Boundary-scan Chain
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28.3.1
Bypass Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path
between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested.
28.3.2
MSB
Bit
31
Device ID
28.3.2.1
28
27
12
11
Version
Part Number
Manufacturer ID
4 bits
16 bits
11 bits
1-bit
Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the revision
of the device. Revision A is 0x0, revision B is 0x1 and so on.
28.3.2.2
Part Number
The part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega640/1280/1281/2560/2561 is listed in Table 30-6 on page 328.
28.3.2.3
Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed
in Table 30-6 on page 328.
28.3.3
Reset Register
The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port Pins when reset,
the Reset Register can also replace the function of the un-implemented optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there
is a high value present in the Reset Register. Depending on the fuse settings for the clock options, the part will
remain reset for a reset time-out period (see Clock Sources on page 40) after releasing the Reset Register. The
output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 28-2 on
page 297.
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Internal reset
ClockDR AVR_RESET
28.3.4
Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well
as the boundary between digital and analog logic for analog circuitry having off-chip connections.
See Boundary-scan Chain on page 298 for a complete description.
28.4
28.4.1
EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to
the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in
the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital
logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as
the JTAG IR-Register is loaded with the EXTEST instruction.
The active states are:
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain
28.4.2
IDCODE; 0x1
Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register consists of a version
number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after powerup.
The active states are:
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain
297
28.4.3
SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan
Chain is selected as Data Register.
The active states are:
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain
Update-DR: Data from the Boundary-scan chain is applied to the output latches. However, the output latches
are not connected to the pins
28.4.4
AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG
reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data
Register. Note that the reset will be active as long as there is a logic one in the Reset Chain. The output from this
chain is not latched.
The active states are:
28.4.5
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
28.5
Shift-DR: The Bypass Register cell between TDI and TDO is shifted
Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well
as the boundary between digital and analog logic for analog circuitry having off-chip connection.
28.5.1
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When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port pins even if the
CKOUT fuse is programmed. Even though the clock is output when the JTAG IR contains SAMPLE_PRELOAD,
the clock is not sampled by the boundary scan.
Figure 28-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
To Next Cell
ShiftDR
EXTEST
Vcc
0
1
LD1
0
D
0
1
1
G
0
1
FF0
LD0
0
D
0
1
1
G
ClockDR
UpdateDR
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See Boundary-scan
Description for Details!
PUExn
PUD
DDxn
Q CLR
RESET
OCxn
WDx
Pxn
ODxn
PORTxn
Q CLR
WRx
IDxn
DATA BUS
RDx
RESET
SLEEP
RRx
SYNCHRONIZER
D
RPx
PINxn
CLK I/O
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
28.5.2
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
WDx:
RDx:
WRx:
RRx:
RPx:
CLK I/O :
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
ShiftDR
To System Logic
FF1
0
D
From
Previous
Cell
ClockDR
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28.6
28.6.1
0x35 (0x55)
JTD
PUD
IVSEL
IVCE
Read/Write
R/W
R/W
R/W
R/W
Initial Value
MCUCR
0x34 (0x54)
JTRF
WDRF
BORF
EXTRF
PORF
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUSR
28.7
28.8
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Table 28-1.
Bit Number
Signal Name
164
PG5.Data
163
PG5.Control
162
PE0.Data
161
PE0.Control
160
PE1.Data
159
PE1.Control
158
PE2.Data
157
PE2.Control
156
PE3.Data
155
PE3.Control
154
PE4.Data
153
PE4.Control
152
PE5.Data
151
PE5.Control
150
PE6.Data
149
PE6.Control
148
PE7.Data
147
PE7.Control
146
PH0.Data
145
PH0.Control
144
PH1.Data
143
PH1.Control
142
PH2.Data
141
PH2.Control
140
PH3.Data
139
PH3.Control
138
PH4.Data
137
PH4.Control
136
PH5.Data
135
PH5.Control
134
PH6.Data
133
PH6.Control
Module
Port G
Port E
Port H
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Table 28-1.
Bit Number
Signal Name
132
PB0.Data
131
PB0.Control
130
PB1.Data
129
PB1.Control
128
PB2.Data
127
PB2.Control
126
PB3.Data
125
PB3.Control
124
PB4.Data
123
PB4.Control
122
PB5.Data
121
PB5.Control
120
PB6.Data
119
PB6.Control
118
PB7.Data
117
PB7.Control
116
PH7.Data
115
PH7.Control
114
PG3.Data
113
PG3.Control
112
PG4.Data
111
PG4.Control
110
RSTT
109
PL0.Data
108
PL0.Control
107
PL1.Data
106
PL1.Control
105
PL2.Data
Module
Port B
Port H
Port G
Port L
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Table 28-1.
Bit Number
Signal Name
104
PL2.Control
103
PL3.Data
102
PL3.Control
101
PL4.Data
100
PL4.Control
99
PL5.Data
98
PL5.Control
97
PL6.Data
96
PL6.Control
95
PL7.Data
94
PL7.Control
93
PD0.Data
92
PD0.Control
91
PD1.Data
90
PD1.Control
89
PD2.Data
88
PD2.Control
87
PD3.Data
86
PD3.Control
85
PD4.Data
84
PD4.Control
83
PD5.Data
82
PD5.Control
81
PD6.Data
80
PD6.Control
79
PD7.Data
78
PD7.Control
77
PG0.Data
76
PG0.Control
75
PG1.Data
74
PG1.Control
73
PC0.Data
72
PC0.Control
71
PC1.Data
70
PC1.Control
69
PC2.Data
Module
Port D
Port G
Port C
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Table 28-1.
Bit Number
Signal Name
68
PC2.Control
67
PC3.Data
66
PC3.Control
65
PC4.Data
64
PC4.Control
63
PC5.Data
62
PC5.Control
61
PC6.Data
60
PC6.Control
59
PC7.Data
58
PC7.Control
57
PJ0.Data
56
PJ0.Control
55
PJ1.Data
54
PJ1.Control
53
PJ2.Data
52
PJ2.Control
51
PJ3.Data
50
PJ3.Control
49
PJ4.Data
48
PJ4.Control
47
PJ5.Data
46
PJ5.Control
45
PJ6.Data
44
PJ6.Control
43
PG2.Data
42
PG2.Control
41
PA7.Data
40
PA7.Control
39
PA6.Data
38
PA6.Control
37
PA5.Data
36
PA5.Control
35
PA4.Data
34
PA4.Control
33
PA3.Data
Module
Port J
Port G
Port A
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Table 28-1.
Bit Number
Signal Name
32
PA3.Control
31
PA2.Data
30
PA2.Control
29
PA1.Data
28
PA1.Control
27
PA0.Data
26
PA0.Control
25
PJ7.Data
24
PJ7.Control
23
PK7.Data
22
PK7.Control
21
PK6.Data
20
PK6.Control
19
PK5.Data
18
PK5.Control
17
PK4.Data
16
PK4.Control
15
PK3.Data
14
PK3.Control
13
PK2.Data
12
PK2.Control
11
PK1.Data
10
PK1.Control
PK0.Data
PK0.Control
PF3.Data
PF3.Control
PF2.Data
PF2.Control
PF1.Data
PF1.Control
PF0.Data
PF0.Control
Module
Port J
Port K
Port F
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Table 28-2.
Bit Number
Signal Name
100
PG5.Data
99
PG5.Control
98
PE0.Data
97
PE0.Control
96
PE1.Data
95
PE1.Control
94
PE2.Data
93
PE2.Control
92
PE3.Data
91
PE3.Control
90
PE4.Data
89
PE4.Control
88
PE5.Data
87
PE5.Control
86
PE6.Data
85
PE6.Control
84
PE7.Data
83
PE7.Control
82
PB0.Data
81
PB0.Control
80
PB1.Data
79
PB1.Control
78
PB2.Data
77
PB2.Control
76
PB3.Data
75
PB3.Control
74
PB4.Data
73
PB4.Control
72
PB5.Data
71
PB5.Control
70
PB6.Data
69
PB6.Control
68
PB7.Data
67
PB7.Control
66
PG3.Data
Module
Port G
Port E
Port B
Port G
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Table 28-2.
Bit Number
Signal Name
65
PG3.Control
64
PG4.Data
63
PG4.Control
62
RSTT
61
PD0.Data
60
PD0.Control
59
PD1.Data
58
PD1.Control
57
PD2.Data
56
PD2.Control
55
PD3.Data
54
PD3.Control
53
PD4.Data
52
PD4.Control
51
PD5.Data
50
PD5.Control
49
PD6.Data
48
PD6.Control
47
PD7.Data
46
PD7.Control
45
PG0.Data
44
PG0.Control
43
PG1.Data
42
PG1.Control
41
PC0.Data
40
PC0.Control
39
PC1.Data
38
PC1.Control
37
PC2.Data
36
PC2.Control
35
PC3.Data
34
PC3.Control
33
PC4.Data
32
PC4.Control
31
PC5.Data
30
PC5.Control
Module
Port D
Port G
Port C
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Table 28-2.
Bit Number
Signal Name
29
PC6.Data
28
PC6.Control
27
PC7.Data
26
PC7.Control
25
PG2.Data
24
PG2.Control
23
PA7.Data
22
PA7.Control
21
PA6.Data
20
PA6.Control
19
PA5.Data
18
PA5.Control
17
PA4.Data
16
PA4.Control
15
PA3.Data
14
PA3.Control
13
PA2.Data
12
PA2.Control
11
PA1.Data
10
PA1.Control
PA0.Data
PA0.Control
PF3.Data
PF3.Control
PF2.Data
PF2.Control
PF1.Data
PF1.Control
PF0.Data
PF0.Control
Module
Port G
Port A
Port F
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29.1
Features
Read-While-Write Self-Programming
Flexible Boot Memory Size
High Security (Separate Boot Lock Bits for a Flexible Protection)
Separate Fuse to Select Reset Vector
Optimized Page(1) Size
Code Efficient Algorithm
Efficient Read-Modify-Write Support
Note:
1. A page is a section in the Flash consisting of several bytes (see Table 30-7 on page 328) used during programming. The page organization does not affect normal operation.
29.2
29.2.1
Application Section
The Application section is the section of the Flash that is used for storing the application code. The protection level
for the Application section can be selected by the application Boot Lock bits (Boot Lock bits 0), see Table 29-2 on
page 313. The Application section can never store any Boot Loader code since the SPM instruction is disabled
when executed from the Application section.
29.2.2
29.3
When erasing or writing a page located inside the RWW section, the NRWW section can be read during the
operation
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When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire
operation
Note that the user software can never read any code that is located inside the RWW section during a Boot Loader
software operation. The syntax Read-While-Write section refers to which section that is being programmed
(erased or written), not which section that actually is being read during a Boot Loader software update.
29.3.1
29.3.2
Read-While-Write Features
CPU Halted?
Read-While-Write
Supported?
RWW Section
NRWW Section
No
Yes
NRWW Section
None
Yes
No
Read-While-Write
(RWW) Section
Z-pointer
Addresses RWW
Section
Z-pointer
Addresses NRWW
Section
No Read-While-Write
(NRWW) Section
CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation
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Program Memory
BOOTSZ = '11'
0x0000
Read-While-Write Section
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
0x0000
Program Memory
BOOTSZ = '01'
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
Program Memory
BOOTSZ = '00'
Note:
29.4
Read-While-Write Section
0x0000
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
0x0000
Flashend
1. The parameters in the figure above are given in Table 29-7 on page 320.
To protect only the Boot Loader Flash section from a software update by the MCU
To protect only the Application Flash section from a software update by the MCU
See Table 29-2 on page 313 and Table 29-3 on page 313 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The
general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction.
Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by (E)LPM/SPM, if it
is attempted.
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Table 29-2.
BLB0 Mode
BLB02
BLB01
Note:
Protection
SPM is not allowed to write to the Application section, and (E)LPM executing from
the Boot Loader section is not allowed to read from the Application section. If
Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while
executing from the Application section.
(E)LPM executing from the Boot Loader section is not allowed to read from the
Application section. If Interrupt Vectors are placed in the Boot Loader section,
interrupts are disabled while executing from the Application section.
Table 29-3.
BLB1 Mode
BLB12
BLB11
Note:
29.4.1
Protection
SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from
the Application section is not allowed to read from the Boot Loader section. If
Interrupt Vectors are placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
(E)LPM executing from the Application section is not allowed to read from the Boot
Loader section. If Interrupt Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.
Note:
Reset Vector = Boot Loader Reset (see Table 29-7 on page 320)
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29.5
Bit
23
22
21
20
19
18
17
15
14
13
12
11
10
16
8
RAMPZ
RAMPZ7
RAMPZ6
RAMPZ5
RAMPZ4
RAMPZ3
RAMPZ2
RAMPZ1
RAMPZ0
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Since the Flash is organized in pages (see Table 30-7 on page 328), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a
page, while the most significant bits are addressing the pages. This is shown in Figure 29-3. Note that the Page
Erase and Page Write operations are addressed independently. Therefore it is of major importance that the Boot
Loader software addresses the same page in both the Page Erase and Page Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations.
The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses the Flash byte-bybyte, also bit Z0 of the Z-pointer is used.
Figure 29-3. Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
1. The different variables used in Figure 29-3 are listed in Table 29-9 on page 320.
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29.6
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary
page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes,
and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading
since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page.
See Simple Assembly Code Example for a Boot Loader on page 318 for an assembly code example.
29.6.1
Page Erase to the RWW section: The NRWW section can be read during the Page Erase
Page Erase to the NRWW section: The CPU is halted during the operation
29.6.2
29.6.3
29.6.4
Page Write to the RWW section: The NRWW section can be read during the Page Write
Page Write to the NRWW section: The CPU is halted during the operation
Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in
SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in soft-
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ware. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an
interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in
Interrupts on page 101.
29.6.5
29.6.6
29.6.7
R0
BLB12
BLB11
BLB02
BLB01
LB2
LB1
See Table 29-2 on page 313 and Table 29-3 on page 313 for how the different settings of the Boot Loader bits
affect the Flash access.
If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is executed
within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is dont care during this operation,
but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lOck
bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to 1 when writing the Lock bits.
When programming the Lock bits the entire Flash can be read during the operation.
29.6.8
29.6.9
Rd
BLB12
BLB11
BLB02
BLB01
LB2
LB1
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The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To
read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When
an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 305 on page 327 for a detailed description and mapping of the Fuse Low byte.
Bit
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte
(FHB) will be loaded in the destination register as shown below. Refer to Table 30-4 on page 327 for detailed
description and mapping of the Fuse High byte.
Bit
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse
byte (EFB) will be loaded in the destination register as shown below. Refer to Table 30-3 on page 326 for detailed
description and mapping of the Extended Fuse byte.
Bit
Rd
EFB2
EFB1
EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be
read as one.
29.6.10
Signature Byte
Device Signature Byte 1
0x0000
0x0002
0x0004
0x0001
Note:
29.6.11
Z-Pointer Address
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Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent
any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not,
an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the
Flash from unintentional writes.
29.6.12
29.6.13
Flash write (Page Erase, Page Write, and write Lock bits by SPM)
3.7ms
4.5ms
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Boot Reset
Address
(Start Boot
Loader Section)
End Application
Section
Boot Loader
Flash Section
Pages
Boot Size
BOOTSZ0
Appli-cation
Flash Section
Table 29-7.
BOOTSZ1
29.6.14
512 words
0x0000 - 0x7DFF
0x7E00 - 0x7FFF
0x7DFF
0x7E00
1024 words
0x0000 - 0x7BFF
0x7C00 - 0x7FFF
0x7BFF
0x7C00
2048 words
16
0x0000 - 0x77FF
0x7800 - 0x7FFF
0x77FF
0x7800
4096 words
32
0x0000 - 0x6FFF
0x7000 - 0x7FFF
0x6FFF
0x7000
Note:
1. The different BOOTSZ Fuse configurations are shown in Figure 29-2 on page 312.
Table 29-8.
Section(1)
Pages
Address
224
0x0000 - 0x6FFF
32
0x7000 - 0x7FFF
Note:
1. For details about these two section, see NRWW No Read-While-Write Section on page 311 and RWW ReadWhile-Write Section on page 311.
Table 29-9.
Explanation of different variables used in Figure 29-3 on page 314 and the mapping to the Z-pointer,
ATmega640
Corresponding
Z-value(2)
Variable
Description(1)
PCMSB
14
PAGEMSB
Most significant bit which is used to address the words within one page
(128 words in a page requires seven bits PC [6:0]).
ZPCMSB
Z15
ZPAGEMSB
Z7
PCPAGE
PC[14:7]
Z15:Z8
Program Counter page address: Page select, for Page Erase and Page
Write.
PCWORD
PC[6:0]
Z7:Z1
Program Counter word address: Word select, for filling temporary buffer
(must be zero during Page Write operation).
Note:
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See Addressing the Flash During Self-Programming on page 314 for details about the use of Z-pointer during
Self-Programming.
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End Application
Section
Boot Loader
Flash Section
Appli-cation
Flash Section
Pages
Boot Size
BOOTSZ0
BOOTSZ1
29.6.15
512 words
0x0000 - 0xFDFF
0xFE00 - 0xFFFF
0xFDFF
0xFE00
1024 words
0x0000 - 0xFBFF
0xFC00 - 0xFFFF
0xFBFF
0xFC00
2048 words
16
0x0000 - 0xF7FF
0xF800 - 0xFFFF
0xF7FF
0xF800
4096 words
32
0x0000 - 0xEFFF
0xF000 - 0xFFFF
0xEFFF
0xF000
Note:
1. The different BOOTSZ Fuse configurations are shown in Figure 29-2 on page 312.
Pages
Address
480
0x0000 - 0xEFFF
32
0xF000 - 0xFFFF
Note:
1. For details about these two section, see NRWW No Read-While-Write Section on page 311 and RWW ReadWhile-Write Section on page 311.
Table 29-12. Explanation of different variables used in Figure 29-3 on page 314 and the mapping to the Z-pointer,
ATmega1280/1281
Corresponding
Z-value(2)
Variable
Description(1)
PCMSB
15
PAGEMSB
Most significant bit which is used to address the words within one page
(128 words in a page requires seven bits PC [6:0]).
ZPCMSB
ZPAGEMSB
Z16(3)
Z7
PCPAGE
PC[15:7]
Z16(3):Z8
Program Counter page address: Page select, for Page Erase and Page
Write
PCWORD
PC[6:0]
Z7:Z1
Program Counter word address: Word select, for filling temporary buffer
(must be zero during Page Write operation)
Notes:
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See Addressing the Flash During Self-Programming on page 314 for details about the use of Z-pointer during
Self-Programming.
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.
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End Application
Section
Boot Loader
Flash Section
Appli-cation
Flash Section
Pages
Boot Size
BOOTSZ0
BOOTSZ1
29.6.16
512 words
0x00000 - 0x1FDFF
0x1FE00 - 0x1FFFF
0x1FDFF
0x1FE00
1024 words
0x00000 - 0x1FBFF
0x1FC00 - 0x1FFFF
0x1FBFF
0x1FC00
2048 words
16
0x00000 - 0x1F7FF
0x1F800 - 0x1FFFF
0x1F7FF
0x1F800
4096 words
32
0x00000 - 0x1EFFF
0x1F000 - 0x1FFFF
0x1EFFF
0x1F000
Note:
1. The different BOOTSZ Fuse configurations are shown in Figure 29-2 on page 312.
Pages
Address
992
0x00000 - 0x1EFFF
32
0x1F000 - 0x1FFFF
Note:
1. For details about these two section, see NRWW No Read-While-Write Section on page 311 and RWW ReadWhile-Write Section on page 311.
Table 29-15. Explanation of different variables used in Figure 29-3 on page 314 and the mapping to the Z-pointer,
ATmega2560/2561
Corresponding
Z-value(2)
Variable
Description(1)
PCMSB
16
Most significant bit in the Program Counter. (The Program Counter is 17 bits
PC[16:0]).
PAGEMSB
Most significant bit which is used to address the words within one page (128
words in a page requires seven bits PC [6:0]).
ZPCMSB
ZPAGEMSB
Z17:Z16(3)
Z7
PCPAGE
PC[16:7]
Z17(3):Z8
Program Counter page address: Page select, for Page Erase and Page
Write.
PCWORD
PC[6:0]
Z7:Z1
Program Counter word address: Word select, for filling temporary buffer
(must be zero during Page Write operation).
Notes:
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See Addressing the Flash During Self-Programming on page 314 for details about the use of Z-pointer during
Self-Programming.
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.
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29.7
29.7.1
Register Description
SPMCSR Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Boot
Loader operations.
Bit
0x37 (0x57)
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SPMCSR
323
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Description
Default Value
1 (unprogrammed)
1 (unprogrammed)
BLB12
1 (unprogrammed)
BLB11
1 (unprogrammed)
BLB02
1 (unprogrammed)
BLB01
1 (unprogrammed)
LB2
Lock bit
1 (unprogrammed)
LB1
Lock bit
1 (unprogrammed)
Note:
Bit No
Table 30-2.
Protection Type
LB Mode
LB2
LB1
Further programming of the Flash and EEPROM is disabled in Parallel and Serial
Programming mode. The Fuse bits are locked in both Serial and Parallel
Programming mode.(1)
BLB0 Mode
BLB02
BLB01
SPM is not allowed to write to the Application section, and (E)LPM executing from the
Boot Loader section is not allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts are disabled while executing
from the Application section.
(E)LPM executing from the Boot Loader section is not allowed to read from the
Application section. If Interrupt Vectors are placed in the Boot Loader section,
interrupts are disabled while executing from the Application section.
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Table 30-2.
BLB12
BLB11
Notes:
30.2
Protection Type
SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from
the Application section is not allowed to read from the Boot Loader section. If
Interrupt Vectors are placed in the Application section, interrupts are disabled while
executing from the Boot Loader section.
(E)LPM executing from the Application section is not allowed to read from the Boot
Loader section. If Interrupt Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. 1 means unprogrammed, 0 means programmed.
Fuse Bits
The ATmega640/1280/1281/2560/2561 has three Fuse bytes. Table 30-3 through Table 30-5 on page 327
describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses
are read as logical zero, 0, if they are programmed.
Table 30-3.
Bit No
Description
Default Value
(1)
1 (unprogrammed)
(1)
1 (unprogrammed)
(1)
1 (unprogrammed)
BODLEVEL2
BODLEVEL1
BODLEVEL0
Note:
1. See System and Reset Characteristics on page 360 for BODLEVEL Fuse decoding.
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Table 30-4.
Bit No
Description
Default Value
OCDEN
Enable OCD
JTAGEN
Enable JTAG
(1)
WDTON
1 (unprogrammed)
EESAVE
BOOTSZ1
0 (programmed)(2)
BOOTSZ0
0 (programmed)(2)
BOOTRST
1 (unprogrammed)
(4)
SPIEN
(3)
Notes:
1.
2.
3.
4.
Table 30-5.
Description
Default Value
Divide clock by 8
0 (programmed)
CKOUT(3)
Clock output
1 (unprogrammed)
SUT1
1 (unprogrammed)(1)
SUT0
0 (programmed)(1)
CKSEL3
0 (programmed)(2)
CKSEL2
0 (programmed)(2)
CKSEL1
1 (unprogrammed)(2)
CKSEL0
0 (programmed)(2)
(4)
CKDIV8
Notes:
Bit No
1. The default value of SUT1:0 results in maximum start-up time for the default clock source. See System and Reset
Characteristics on page 360 for details.
2. The default setting of CKSEL3:0 results in internal RC Oscillator @ 8MHz. See Table 10-1 on page 40 for details.
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See Clock Output Buffer on page 47 for
details.
4. See System Clock Prescaler on page 47 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is
programmed. Program the Fuse bits before programming the Lock bits.
30.2.1
Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the fuse values will have
no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect
once it is programmed. The fuses are also latched on Power-up in Normal mode.
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30.3
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in
both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATmega640/1280/1281/2560/2561 the signature bytes are given in Table 30-6.
Table 30-6.
30.4
JTAG
Part
0x000
0x001
0x002
Part Number
Manufacture ID
ATmega640
0x1E
0x96
0x08
9608
0x1F
ATmega1280
0x1E
0x97
0x03
9703
0x1F
ATmega1281
0x1E
0x97
0x04
9704
0x1F
ATmega2560
0x1E
0x98
0x01
9801
0x1F
ATmega2561
0x1E
0x98
0x02
9802
0x1F
Calibration Byte
The ATmega640/1280/1281/2560/2561 has a byte calibration value for the internal RC Oscillator. This byte resides
in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written
into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator.
30.5
Page Size
Table 30-7.
Flash Size
Page Size
PCWORD
No. of Pages
PCPAGE
PCMSB
128 words
PC[6:0]
1024
PC[16:7]
16
Table 30-8.
30.6
EEPROM Size
Page Size
PCWORD
No. of Pages
PCPAGE
EEAMSB
4Kbytes
8 bytes
EEA[2:0]
512
EEA[11:3]
11
30.6.1
Signal Names
In this section, some pins of the ATmega640/1280/1281/2560/2561 are referenced by signal names describing
their functionality during parallel programming, see Figure 30-1 and Table 30-9 on page 329. Pins not described in
the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is
shown in Table 30-12 on page 330.
When pulsing WR or OE, the command loaded determines the action executed. The different commands are
shown in Table 30-13 on page 330.
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PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12V
RESET
BS2
PA0
VCC
+5V
AVCC
DATA
PB7 - PB0
XTAL1
GND
Note:
Table 30-9.
Signal Name in
Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
Byte Select 1
XA0
PD5
XA1
PD6
PAGEL
PD7
BS2
PA0
Byte Select 2
DATA
PB7-0
I/O
BS1
Flash / EEPROM
Address
Fuse Programming
Low Byte
Low Byte
Low Byte
High Byte
High Byte
High Byte
Lockbits
Extended High
Byte
Reserved
Extended Byte
Reserved
Reserved
Reserved
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Symbol
Value
PAGEL
Prog_enable[3]
XA1
Prog_enable[2]
XA0
Prog_enable[1]
BS1
Prog_enable[0]
XA0
Load Flash or EEPROM Address (High or low address byte determined by BS2 and BS1)
Load Data (High or Low data byte for Flash determined by BS1)
Load Command
No Action, Idle
30.7
30.7.1
Command Executed
1000 0000
Chip Erase
0100 0000
0010 0000
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
0000 0100
0000 0010
Read Flash
0000 0011
Read EEPROM
Parallel Programming
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5V - 5.5V between VCC and GND.
2. Set RESET to 0 and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in Table 30-11 to 0000 and wait at least 100ns.
4. Apply 11.5V - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied
to RESET, will cause the device to fail entering programming mode.
5. Wait at least 50s before sending a new command.
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30.7.2
30.7.3
The command needs only be loaded once when writing or reading multiple memory locations
Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is
programmed) and Flash after a Chip Erase
Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or
256 byte EEPROM. This consideration also applies to Signature bytes reading
Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the
program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed
before the Flash and/or EEPROM are reprogrammed.
Note:
1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
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PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
PCWORD[PAGEMSB:0]:
00
INSTRUCTION WORD
01
02
PAGEEND
Note:
DATA
0x10
ADDR. LOW
DATA LOW
DATA HIGH
XX
B
ADDR. LOW
DATA LOW
DATA HIGH
E
XX
I
XX
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
Note:
30.7.5
333
DATA
0x11
ADDR. HIGH
ADDR. LOW
DATA
E
XX
B
ADDR. LOW
C
DATA
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
30.7.6
30.7.7
30.7.8
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30.7.9
30.7.10
DATA
0x40
DATA
XX
0x40
DATA
XX
0x40
DATA
XX
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
30.7.11
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30.7.12
0
Extended Fuse Byte
1
DATA
BS2
0
Lock Bits
BS1
BS2
30.7.13
30.7.14
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30.7.15
XTAL1
tDVXH
tXLDX
tBVPH
PAGEL
tWLBX
tPHPL
tWLWH
WR
tPLWL
WLRL
RDY/BSY
tWLRH
Figure 30-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
tXLPH
t XLXH
LOAD ADDRESS
(LOW BYTE)
tPLXH
XTAL1
BS1
PAGEL
DATA
XA0
XA1
Note:
1. The timing requirements shown in Figure 30-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 30-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
DATA
tOHDZ
XA0
XA1
Note:
1. The timing requirements shown in Figure 30-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation.
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Parameter
Min
VPP
11.5
IPP
tDVXH
67
tXLXH
200
tXHXL
150
tXLDX
67
tXLWL
tXLPH
tPLXH
150
tBVPH
67
tPHPL
150
tPLBX
67
tWLBX
67
tPLWL
67
tBVWL
67
tWLWH
150
tWLRL
tWLRH
Max
Units
12.5
250
ns
(2)
3.7
4.5
7.5
s
ms
tWLRH_CE
tXLOL
tBVDV
tOLDV
250
tOHDZ
250
Notes:
30.8
Typ
250
ns
1.
2.
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
tWLRH_CE is valid for the Chip Erase command.
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is
pulled to GND. The serial programming interface consists of pins SCK, PDI (input) and PDO (output). After RESET
is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be
executed. NOTE, in Table 30-15 on page 339, the pin mapping for serial programming is listed. Not all packages
use the SPI pins dedicated for the internal Serial Peripheral Interface - SPI.
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30.8.1
Pins (TQFP-100)
Pins (TQFP-64)
I/O
Description
PDI
PB2
PE0
Serial Data in
PDO
PB3
PE1
SCK
PB1
PB1
Serial Clock
AVCC
PDO
SCK
XT AL1
RESET
GND
Notes:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8V - 5.5V.When programming the
EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and
there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every
memory location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz
30.8.2
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3. The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did
not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying
the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is applied for a given
address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with
the address lines 15:8. Before issuing this command, make sure the instruction Load Extended Address
Byte has been used to define the MSB of the address. The extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and when crossing the
64KWord boundary. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the
next page (see Table 30-16). Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is
written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte (see Table
30-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at serial output PDO. When reading the Flash memory, use the instruction Load Extended Address
Byte to define the upper address byte, which is not included in the Read Program Memory instruction. The
extended address byte is stored until the command is re-issued, that is, the command needs only be issued
for the first page, and when crossing the 64KWord boundary.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET to 1.
Turn VCC power off.
Table 30-16. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
30.8.3
Symbol
tWD_FLASH
4.5ms
tWD_EEPROM
3.6ms
tWD_ERASE
9.0ms
Byte 1
Byte 2
Byte 3
Byte 4
Programming Enable
$AC
$53
$00
$00
$AC
$80
$00
$00
Poll RDY/BSY
$F0
$00
$00
$4D
$00
Extended adr
$00
$48
$00
adr LSB
$40
$00
adr LSB
Load Instructions
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Byte 1
Byte 2
Byte 3
Byte 4
$C1
$00
0000 000aa
data byte in
$28
adr MSB
adr LSB
$20
adr MSB
adr LSB
$A0
0000 aaaa
aaaa aaaa
$58
$00
$00
$30
$00
0000 000aa
$50
$00
$00
$58
$08
$00
$50
$08
$00
$38
$00
$00
$4C
adr MSB
adr LSB
$00
$C0
0000 aaaa
aaaa aaaa
data byte in
$C2
0000 aaaa
aaaa 00
$00
$AC
$E0
$00
data byte in
$AC
$A0
$00
data byte in
$AC
$A8
$00
data byte in
$AC
$A4
$00
data byte in
Write Instructions
Notes:
1.
2.
3.
4.
5.
6.
If the LSB in RDY/BSY data byte out is 1, a programming operation is still pending. Wait until this bit returns 0
before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 30-11 on page 342.
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Byte 1
Byte 2
Adr MSB
A
Byte 3
Byte 1
Byte 4
Byte 2
Adr LSB
Bit 15 B
Adr MSB
Byte 3
Adrr LSB
B
Bit 15 B
Byte 4
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
30.8.4
MSB
LSB
MSB
LSB
30.9
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while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when
using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for
this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip.
The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
30.9.1
Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Shift-IR
Update-IR
0
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30.9.2
AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out
from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as
Data Register. Note that the reset will be active as long as there is a logic one in the Reset Chain. The output
from this chain is not latched.
The active states are:
30.9.3
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming
Enable Register is selected as Data Register. The active states are the following:
Shift-DR: The programming enable signature is shifted into the Data Register
Update-DR: The programming enable signature is compared to the correct value, and Programming mode is
entered if the signature is valid
30.9.4
PROG_COMMANDS (0x5)
The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following:
Capture-DR: The result of the previous command is loaded into the Data Register
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and
shifting in the new command
30.9.5
PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash
Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command
Register. The active states are the following:
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence
is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The
AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting
with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The
Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures
that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the
page buffer does not make the program counter increment into the next page.
30.9.6
PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash
Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command
Register. The active states are the following:
Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR
automatically alternates between reading the low and the high byte for each new Capture-DR state, starting
with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The
Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures
that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last
location in the page makes the program counter increment into the next page.
Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
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30.9.7
Data Registers
The Data Registers are selected by the JTAG instruction registers described in section Programming Specific
JTAG Instructions on page 343. The Data Registers relevant for programming operations are:
30.9.8
Reset Register
The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the
part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there
is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will
remain reset for a Reset Time-out period (refer to Clock Sources on page 40) after releasing the Reset Register.
The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 28-2
on page 297.
30.9.9
D
A
T
A
0xA370
Programming Enable
TDO
30.9.10
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S
T
R
O
B
E
S
A
D
D
R
E
S
S
/
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
TDO
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TDI Sequence
TDO Sequence
Notes
0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
0110011_10000000
xxxxxox_xxxxxxxx
0100011_00010000
xxxxxxx_xxxxxxxx
0001011_cccccccc
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
0010111_iiiiiiii
xxxxxxx_xxxxxxxx
0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00000010
xxxxxxx_xxxxxxxx
0001011_cccccccc
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
0100011_00010001
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
(2)
(10)
(10)
Low byte
High byte
(10)
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TDI Sequence
TDO Sequence
0100011_00000011
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110011_bbbbbbbb
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0100011_01000000
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
(3)
0111011_00000000
0111001_00000000
0111011_00000000
0111011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
xxxxxox_xxxxxxxx
(2)
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
(3)
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
xxxxxox_xxxxxxxx
(2)
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
(3)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00100000
xxxxxxx_xxxxxxxx
0010011_11iiiiii
xxxxxxx_xxxxxxxx
(4)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00000100
xxxxxxx_xxxxxxxx
0111010_00000000
0111011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0111110_00000000
0111111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
(7)
(9)
Notes
(10)
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TDI Sequence
TDO Sequence
Notes
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo
(5)
0111010_00000000
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
(5)
Fuse Ext. byte
Fuse High byte
Fuse Low byte
Lock bits
0100011_00001000
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0100011_00001000
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0100011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
Notes:
1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is
normally the case).
2. Repeat until o = 1.
3. Set bits to 0 to program the corresponding Fuse, 1 to unprogram the Fuse.
4. Set bits to 0 to program the corresponding Lock bit, 1 to leave the Lock bit unchanged.
5. 0 = programmed, 1 = unprogrammed.
6. The bit mapping for Fuses Extended byte is listed in Table 30-3 on page 326.
7. The bit mapping for Fuses High byte is listed in Table 30-4 on page 327.
8. The bit mapping for Fuses Low byte is listed in Table 30-5 on page 327.
9. The bit mapping for Lock bits byte is listed in Table 30-1 on page 325.
10. Address bits exceeding PCMSB and EEAMSB (Table 30-7 and Table 30-8 on page 328) are dont care.
11. All TDI and TDO sequences are represented by binary digits (0b...).
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Figure 30-16. State Machine Sequence for Changing/Reading the Data Word
1
Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Pause-DR
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
30.9.11
Exit1-IR
Update-IR
0
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STROBES
TDI
State
Machine
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which
eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its
operation transparently for the user. However, if too few bits are shifted between each Update-DR state during
page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are
at least 11 TCK cycles between each Update-DR state.
30.9.12
Programming Algorithm
All references below of type 1a, 1b, and so on, refer to Table 30-18 on page 347.
30.9.13
30.9.14
30.9.15
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30.9.16
30.9.17
352
30.9.19
30.9.20
30.9.21
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30.9.22
30.9.23
30.9.24
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*NOTICE:
31.1
DC Characteristics
Parameter
Condition
Min.
Typ.
Max.
Units
(1)
VIL
-0.5
-0.5
0.2VCC
0.3VCC(1)
VIL1
-0.5
0.1VCC(1)
VIL2
-0.5
0.1VCC(1)
VIH
0.7VCC(2)
0.6VCC(2)
VCC + 0.5
VCC + 0.5
(2)
VIH1
0.8VCC
0.7VCC(2)
VCC + 0.5
VCC + 0.5
VIH2
0.9VCC(2)
VCC + 0.5
VOL
VOH
IIL
Input Leakage
Current I/O Pin
IIH
Input Leakage
Current I/O Pin
RRST
30
60
RPU
20
50
0.9
0.6
4.2
2.3
1
A
1
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Parameter
Condition
(5)
Min.
Typ.
Max.
0.5
0.8
3.2
10
14
0.14
0.22
0.7
1.1
2.7
<5
15
<1
7.5
<10
40
mV
50
nA
mA
Power-down mode
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
Vin = VCC/2
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2
tACID
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 4.0V
Notes:
Units
-50
750
500
ns
1. "Max" means the highest value where the pin is guaranteed to be read as low.
2. "Min" means the lowest value where the pin is guaranteed to be read as high.
3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
ATmega1281/2561:
1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
4.)The sum of all IOL, for ports F0-F7 should not exceed 100mA.
ATmega640/1280/2560:
1.)The sum of all IOL, for ports J0-J7, A0-A7, G2 should not exceed 200mA.
2.)The sum of all IOL, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200mA.
3.)The sum of all IOL, for ports G3-G4, B0-B7, H0-B7 should not exceed 200mA.
4.)The sum of all IOL, for ports E0-E7, G5 should not exceed 100mA.
5.)The sum of all IOL, for ports F0-F7, K0-K7 should not exceed 100mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady
state conditions (non-transient), the following must be observed:
ATmega1281/2561:
1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
4)The sum of all IOH, for ports F0-F7 should not exceed 100mA.
ATmega640/1280/2560:
1)The sum of all IOH, for ports J0-J7, G2, A0-A7 should not exceed 200mA.
2)The sum of all IOH, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200mA.
3)The sum of all IOH, for ports G3-G4, B0-B7, H0-H7 should not exceed 200mA.
4)The sum of all IOH, for ports E0-E7, G5 should not exceed 100mA.
5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100mA.
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If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Values with PRR1 Power Reduction Register 1 on page 56 enabled (0xFF).
31.2
Speed Grades
Maximum frequency is depending on VCC. As shown in Figure 31-1 trough Figure 31-4 on page 358, the Maximum
Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.
31.2.1
8MHz
Figure 31-1. Maximum Frequency vs. VCC, ATmega640V/1280V/1281V/2560V/2561V
8 MHz
4 MHz
1.8V
2.7V
5.5V
Figure 31-2. Maximum Frequency vs. VCC when also No-Read-While-Write Section(1),
ATmega2560V/ATmega2561V, is used
8 MHz
1.8V
Note:
2.7V
5.5V
1. When only using the Read-While-Write Section of the program memory, a higher speed can be achieved at low
voltage, see Read-While-Write and No Read-While-Write Flash Sections on page 310 for addresses.
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31.2.2
16MHz
Figure 31-3. Maximum Frequency vs. VCC, ATmega640/ATmega1280/ATmega1281
16 MHz
8 MHz
2.7V
4.5V
5.5V
16 MHz
4.5V
5.5V
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31.3
31.3.1
Clock Characteristics
Calibrated Internal RC Oscillator Accuracy
Table 31-1.
Factory Calibration
Frequency
VCC
8.0MHz
3V
Temperature
Calibration Accuracy
25C
10%
-40C - 85C
1%
(1)
User Calibration
Notes:
31.3.2
1.8V - 5.5V
2.7V - 5.5V(2)
7.3MHz - 8.1MHz
V IH1
V IL1
31.4
Table 31-2.
Symbol
Parameter
1/tCLCL
Oscillator Frequency
Min.
Max.
Min.
Max.
Min.
Max.
Units
16
MHz
tCLCL
Clock Period
500
125
62.5
tCHCX
High Time
200
50
25
tCLCX
Low Time
200
50
25
tCLCH
Rise Time
2.0
1.6
0.5
tCHCL
Fall Time
2.0
1.6
0.5
tCLCL
ns
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31.5
Parameter
Condition
Min
Typ
0.2VCC
VRST
tRST
Max
Units
0.9VCC
2.5
50
mV
tBOD
VBG
tBG
IBG
VHYST
Note:
31.5.1
1.0
1.1
1.2
40
70
10
1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
ATmega640: revision A
ATmega1280: revision A
ATmega1281: revision A
ATmega2560: revision A to E
ATmega2561: revision A to E
Table 31-4.
Symbol
Min.(1)
Typ.(1)
Max.(1)
Units
(2)
0.7
1.0
1.4
(3)
0.05
0.9
1.3
0.01
4.5
V/ms
Parameter
Power-on Reset Threshold Voltage (rising)
VPOT
VPSR
Notes:
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31.5.2
Table 31-5.
Symbol
Min.(1)
Typ.(1)
Max.(1)
Units
(2)
1.1
1.4
1.6
(3)
0.6
1.3
1.6
0.01
Parameter
Power-on Reset Threshold Voltage (rising)
VPOT
VPSR
Notes:
V/ms
Table 31-6.
Min. VBOT
111
Typ. VBOT
Max. VBOT
Units
BOD Disabled
110
1.7
1.8
2.0
101
2.5
2.7
2.9
100
4.1
4.3
4.5
011
010
Reserved
001
000
Note:
31.6
1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the
device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur
before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is
performed using BODLEVEL = 110 for 4MHz operation of ATmega640V/1280V/1281V/2560V/2561V, BODLEVEL
= 101 for 8MHz operation of ATmega640V/1280V/1281V/2560V/2561V and ATmega640/1280/1281, and BODLEVEL = 100 for 16MHz operation of ATmega640/1280/1281/2560/2561.
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Table 31-7.
Symbol
Parameter
VIL
VIH
(1)
Min.
Max.
Input Low-voltage
-0.5
0.3 VCC
Input High-voltage
0.7 VCC
VCC + 0.5
Vhys
(1)
VOL
Output Low-voltage
tr
(1)
Condition
0.05
3mA sink current
(1)
tSP
Ii
Ci(1)
Rp
20 +
0.1Cb(3)(2)
300
20 +
0.1Cb(3)(2)
250
50(2)
-10
10
10
pF
400
kHz
fSCL 100kHz
V CC 0.4V
---------------------------3mA
1000ns
------------------Cb
V CC 0.4V
---------------------------3mA
300
ns----------------Cb
fSCL 100kHz
4.0
0.6
fSCL 100kHz(6)
4.7
(7)
1.3
fSCL 100kHz
4.0
0.6
fSCL 100kHz
4.7
0.6
fSCL 100kHz
3.45
0.9
fSCL 100kHz
250
100
fSCL 100kHz
4.0
0.6
fSCL 100kHz
4.7
1.3
fCK(4)
> max(16fSCL,
250kHz)(5)
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Note:
0.4
fSCL
(1)
tof
VCC(2)
Units
ns
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6. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK),
thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz.
7. The actual low period generated by the ATmega640/1280/1281/2560/2561 2-wire Serial Interface is (1/fSCL - 2/fCK),
thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still,
ATmega640/1280/1281/2560/2561 devices connected to the bus may communicate at full speed (400kHz) with
other ATmega640/1280/1281/2560/2561 devices, as well as any other device with a proper tLOW acceptance
margin.
tHIGH
tr
tLOW
tLOW
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
SDA
tBUF
31.7
Mode
SCK period
Master
SCK high/low
Master
Rise/Fall time
Master
3.6
Setup
Master
10
Hold
Master
10
Out to SCK
Master
0.5 tsck
SCK to out
Master
10
Master
10
SS low to out
Slave
15
10
SCK period
Slave
4 tck
11
SCK high/low(1)
Slave
2 tck
12
Rise/Fall time
Slave
13
Setup
Slave
10
14
Hold
Slave
tck
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Note:
Min.
Typ.
Max.
ns
1600
15
20
10
20
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SCK
(CPOL = 0)
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
MSB
...
LSB
8
MOSI
(Data Output)
MSB
...
LSB
16
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
MSB
...
LSB
15
MISO
(Data Output)
MSB
17
...
LSB
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31.8
Table 31-9.
Symbol
Max. (1)
Condition
Resolution
10
2.25
1.25
0.5
Gain Error
Offset Error
-2
Conversion Time
13
260
Clock Frequency
50
1000
kHz
VCC - 0.3
VCC + 0.3
1.0
AVCC
GND
VREF
AVCC
VREF
Reference Voltage
VIN
Min. (1)
Parameter
Input Voltage
Units
Bits
2.5
LSB
Input Bandwidth
38,5
kHz
VINT1
1.1V
1.0
1.1
1.2
VINT2
2.56V
2.4
2.56
2.8
RREF
32
RAIN
100
Note:
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Parameter
Condition
Gain =
Resolution
Gain Error
Offset Error
Clock Frequency
Min. (1)
Typ. (1)
Gain = 10
Gain = 200
Gain = 1
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
18
Gain = 10
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
17
Gain = 200
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Gain = 1
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
2.5
Gain = 10
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Gain = 200
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Gain = 1
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
0.75
Gain = 10
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Max. (1)
Unit
s
Bits
LSB
1.5
Gain = 200
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
10
Gain =
1.7
Gain = 10
1.7
Gain = 200
0.5
Gain = 1
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Gain = 10
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
Gain = 200
VREF = 4V, VCC = 5V
CLKADC = 50 - 200kHz
3
50
LSB
200
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Max. (1)
Unit
s
65
260
VCC - 0.3
VCC + 0.3
2.7
AVCC - 0.5
GND
VCC
-VREF/Gain
VREF/Gain
-511
511
Parameter
Condition
Min. (1)
Conversion Time
AVCC
VREF
Reference Voltage
Typ. (1)
VIN
Input Voltage
VDIFF
Input Bandwidth
kHz
VINT
RREF
32
RAIN
100
Note:
31.9
2.3
LSB
2.56
2.8
Table 31-11. External Data Memory Characteristics, 4.5 to 5.5 Volts, No Wait-state
8MHz Oscillator
Min.
Max.
Variable Oscillator
Symbol
Parameter
1/tCLCL
Oscillator Frequency
tLHLL
115
1.0tCLCL-10
tAVLL
57.5
0.5tCLCL-5(1)
3a
tLLAX_ST
3b
tLLAX_LD
tAVLLC
57.5
0.5tCLCL-5(1)
tAVRL
115
1.0tCLCL-10
tAVWL
115
1.0tCLCL-10
tLLWL
47.5
67.5
tLLRL
47.5
67.5
tDVRH
10
tRLDV
11
tRHDX
12
tRLRH
13
40
Min.
Max.
0.0
16
MHz
0.5tCLCL-15(2)
0.5tCLCL+5(2)
ns
0.5tCLCL-15(2)
0.5tCLCL+5(2)
40
75
1.0tCLCL-50
RD Pulse Width
115
1.0tCLCL-10
tDVWL
42.5
0.5tCLCL-20(1)
14
tWHDX
115
1.0tCLCL-10
15
tDVWH
125
1.0tCLCL
16
tWLWH
WR Pulse Width
115
1.0tCLCL-10
Notes:
Unit
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
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2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 31-12. External Data Memory Characteristics, 4.5 to 5.5 Volts, 1 Cycle Wait-state
8MHz Oscillator
Min.
Max.
Variable Oscillator
Symbol
Parameter
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
16
MHz
10
tRLDV
12
tRLRH
RD Pulse Width
240
2.0tCLCL-10
15
tDVWH
240
2.0tCLCL
16
tWLWH
WR Pulse Width
240
2.0tCLCL-10
200
2.0tCLCL-50
ns
Table 31-13. External Data Memory Characteristics, 4.5 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4MHz Oscillator
Symbol
Parameter
Min.
Max.
Variable Oscillator
Min.
Max.
Unit
0.0
16
MHz
1/tCLCL
Oscillator Frequency
10
tRLDV
12
tRLRH
RD Pulse Width
365
3.0tCLCL-10
15
tDVWH
375
3.0tCLCL
16
tWLWH
WR Pulse Width
365
3.0tCLCL-10
325
3.0tCLCL-50
ns
Table 31-14. External Data Memory Characteristics, 4.5 to 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4MHz Oscillator
Min.
Max.
Variable Oscillator
Symbol
Parameter
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
16
MHz
10
tRLDV
12
tRLRH
RD Pulse Width
365
3.0tCLCL-10
14
tWHDX
240
2.0tCLCL-10
15
tDVWH
375
3.0tCLCL
16
tWLWH
WR Pulse Width
365
3.0tCLCL-10
325
3.0tCLCL-50
ns
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Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state
4MHz Oscillator
Min.
Max.
Variable Oscillator
Symbol
Parameter
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
MHz
tLHLL
235
tCLCL-15
tAVLL
115
0.5tCLCL-10(1)
3a
tLLAX_ST
3b
tLLAX_LD
tAVLLC
115
0.5tCLCL-10(1)
tAVRL
235
1.0tCLCL-15
tAVWL
235
1.0tCLCL-15
tLLWL
115
130
0.5tCLCL-10(2)
0.5tCLCL+5(2)
tLLRL
115
130
ns
0.5tCLCL-10(2)
0.5tCLCL+5(2)
tDVRH
45
10
tRLDV
11
tRHDX
12
tRLRH
13
45
190
1.0tCLCL-60
RD Pulse Width
235
1.0tCLCL-15
tDVWL
105
0.5tCLCL-20(1)
14
tWHDX
235
1.0tCLCL-15
15
tDVWH
250
1.0tCLCL
16
tWLWH
WR Pulse Width
235
1.0tCLCL-15
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 31-16. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 0, SRWn0 = 1
4MHz Oscillator
Min.
Max.
Variable Oscillator
Symbol
Parameter
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
MHz
10
tRLDV
12
tRLRH
RD Pulse Width
485
2.0tCLCL-15
15
tDVWH
500
2.0tCLCL
16
tWLWH
WR Pulse Width
485
2.0tCLCL-15
440
2.0tCLCL-60
ns
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Table 31-17. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4MHz Oscillator
Min.
Variable Oscillator
Symbol
Parameter
Max.
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
MHz
10
tRLDV
12
tRLRH
RD Pulse Width
735
3.0tCLCL-15
15
tDVWH
750
3.0tCLCL
16
tWLWH
WR Pulse Width
735
3.0tCLCL-15
690
3.0tCLCL-60
ns
Table 31-18. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4MHz Oscillator
Min.
Variable Oscillator
Symbol
Parameter
Max.
Min.
Max.
Unit
1/tCLCL
Oscillator Frequency
0.0
MHz
10
tRLDV
12
tRLRH
RD Pulse Width
735
3.0tCLCL-15
14
tWHDX
485
2.0tCLCL-15
15
tDVWH
750
3.0tCLCL
16
tWLWH
WR Pulse Width
735
3.0tCLCL-15
690
3.0tCLCL-60
ns
T2
T3
T4
ALE
4
A15:8
Prev. addr.
Address
15
3a
DA7:0
Prev. data
Address
13
XX
Data
14
16
Write
WR
3b
Address
11
Data
Read
DA7:0 (XMBK = 0)
10
8
12
RD
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T2
T3
T4
T5
ALE
4
A15:8
Prev. addr.
Address
15
3a
DA7:0
Prev. data
Address
13
Data
XX
14
16
Write
WR
3b
DA7:0 (XMBK = 0)
11
9
Data
Read
Address
10
8
12
RD
T2
T3
T4
T5
T6
ALE
4
A15:8
7
Address
Prev. addr.
15
DA7:0
Prev. data
3a
Address
13
XX
Data
14
16
Write
WR
9
3b
Address
Data
Read
DA7:0 (XMBK = 0)
11
10
8
12
RD
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T2
T3
T4
T6
T5
T7
ALE
4
A15:8
7
Address
Prev. addr.
15
3a
DA7:0
Prev. data
Address
13
XX
Data
14
16
Write
WR
9
3b
Address
11
Data
Read
DA7:0 (XMBK = 0)
10
8
12
RD
The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or
external).
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5.5V
5.0V
ICC (m A)
32.1
1.5
4.5V
4.0V
3.3V
2.7V
1.8V
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
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5.5V
5.0V
20
ICC (m A)
4.5V
15
4.0V
10
3.3V
2.7V
1.8V
0
0
10
12
14
16
Frequency (MHz)
Figure 32-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
14
85C
25C
-40C
12
ICC (mA)
10
8
6
4
2
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
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Figure 32-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
2.5
-40C
85C
25C
ICC (mA)
1.5
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 32-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
0.7
0.6
-40C
ICC (mA)
0.5
0.4
25C
85C
0.3
0.2
0.1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
375
5.5V
0.5
5.0V
ICC (mA)
0.4
4.5V
4.0V
0.3
3.3V
0.2
2.7V
1.8V
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
5.5V
6
5.0V
5
ICC (m A)
32.2
4.5V
4.0V
3
2
3.3V
2.7V
1.8V
0
0
10
12
14
16
Frequency (MHz)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
376
Figure 32-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
3.5
85C
25C
-40C
ICC (mA)
2.5
2
1.5
1
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 32-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.9
-40C
0.8
0.7
85C
25C
ICC (mA)
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
377
Figure 32-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)I
0.3
-40C
0.25
ICC (m A)
0.2
0.15
25C
85C
0.1
0.05
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
32.2.1
Additional Current Consumption for the different I/O modules (absolute values)
PRR bit
Typical numbers
VCC = 2V, F = 1MHz
PRUSART3
8.0A
51A
220A
PRUSART2
8.0A
51A
220A
PRUSART1
8.0A
51A
220A
PRUSART0
8.0A
51A
220A
PRTWI
12A
75A
315A
PRTIM5
6.0A
39A
150A
PRTIM4
6.0A
39A
150A
PRTIM3
6.0A
39A
150A
PRTIM2
11A
72A
300A
PRTIM1
6.0A
39A
150A
PRTIM0
4.0A
24A
100A
PRSPI
15A
95A
400A
PRADC
12A
75A
315A
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
378
Table 32-2.
PRUSART3
3.0%
17%
PRUSART2
3.0%
17%
PRUSART1
3.0%
17%
PRUSART0
3.0%
17%
PRTWI
4.4%
24%
PRTIM5
1.8%
10%
PRTIM4
1.8%
10%
PRTIM3
1.8%
10%
PRTIM2
4.3%
23%
PRTIM1
1.8%
10%
PRTIM0
1.5%
8.0%
PRSPI
3.3%
18%
PRADC
4.5%
24%
PRR bit
It is possible to calculate the typical current consumption based on the numbers from Table 32-1 on page 378 for
other VCC and frequency settings than listed in Table 32-2.
32.2.1.1
Example 1
Calculate the expected current consumption in idle mode with USART0, TIMER1, and TWI enabled at VCC = 2.0V
and F = 1MHz. From Table 32-2, third column, we see that we need to add 17% for the USART0, 24% for the TWI,
and 10% for the TIMER1 module. Reading from Figure 32-6 on page 376, we find that the idle current consumption
is ~0.15mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and
TWI enabled, gives:
I CC total 0.15mA 1 + 0.17 + 0.24 + 0.10 0.227mA
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
379
85C
3.5
3
ICC (A)
2.5
2
1.5
-40C
25C
1
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 32-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
12
85C
10
-40C
25C
ICC (A)
32.3
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
380
25C
10
ICC(A)
9
8
7
6
5
4
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 32-14. Power-save Supply Current vs. VCC (Watchdog Timer Enabled)
9
8
25C
7
6
I CC (A)
32.4
5
4
3
2
1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
381
32.5
0.18
0.16
ICC (mA)
0.14
4MHz res
4MHz xtal
0.12
0.1
0.08
2MHz res
2MHz xtal
0.06
1MHz res
455kHz res
0.04
0.02
32kHz xtal
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Pin Pull-up
Figure 32-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
60
50
40
IOP (A)
32.6
30
20
10
25C
85C
-40C
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VOP (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
382
Figure 32-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
90
80
70
IOP (A)
60
50
40
30
20
85C
25C
-40C
10
0
0
0.5
1.5
2.5
VOP (V)
Figure 32-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
160
140
120
IOP (A)
100
80
60
40
25C
85C
-40C
20
0
0
VOP (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
383
Figure 32-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
40
35
IRESET (A)
30
25
20
15
10
25C
-40C
85C
5
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VRESET (V)
Figure 32-20. Reset pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
70
60
IRESET (A)
50
40
30
20
25C
-40C
85C
10
0
0
0.5
1.5
2.5
VRESET (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
384
Figure 32-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120
100
IRESET (A)
80
60
40
20
25C
-40C
85C
0
0
VRESET (V)
85C
0.8
VOL (V)
32.7
0.7
25C
0.6
-40C
0.5
0.4
0.3
0.2
0.1
0
0
10
15
20
25
IOL (mA)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
385
Figure 32-23. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
0.6
85C
0.5
25C
-40C
VOL (V)
0.4
0.3
0.2
0.1
0
0
10
15
20
25
IOL (mA)
Figure 32-24. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
3.5
VOH (V)
2.5
-40C
25C
85C
1.5
0.5
0
0
10
15
20
25
IOH (mA)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
386
Figure 32-25. I/O Pin Output Voltage vs. Source Current (VCC = 5V)
5.1
5
4.9
VOH (V)
4.8
4.7
4.6
-40C
4.5
25C
4.4
85C
4.3
0
10
15
20
25
IOH (mA)
-40C
25C
85C
3
2.5
Threshold (V)
32.8
2
1.5
1
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
387
Figure 32-27. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as 0)
2.5
85C
25C
-40C
Threshold (V)
1.5
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
-40C
0.7
0.6
0.5
25C
85C
0.4
0.3
0.2
0.1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
388
Figure 32-29. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as 1)
2.5
-40C
25C
85C
Threshold (V)
1.5
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 32-30. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as 0)
2.5
85C
25C
-40C
Threshold (V)
1.5
0.5
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
389
0.6
0.5
0.4
0.3
0.2
0.1
-40C
25C
85C
0
1.5
2.5
3.5
4.5
5.5
60
80
100
VCC (V)
4.35
Rising Vcc
Threshold (V)
32.9
4.3
4.25
Falling Vcc
4.2
-60
-40
-20
20
40
Temperature (C)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
390
Rising Vcc
Threshold (V)
2.75
2.7
Falling Vcc
2.65
2.6
-60
-40
-20
20
40
60
80
60
80
100
Temperature (C)
1.85
T hre shold ( V )
Rising Vcc
1.8
Fallling Vcc
1.75
1.7
-60
-40
-20
20
40
Temperature (C)
100
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
391
-40C
FRC (kHz)
124
25C
122
120
118
116
85C
114
2
2.5
3.5
4.5
5.5
VCC (V)
FRC (kHz)
124
122
120
2.1V
2.7V
3.3V
4.0V
5.5V
118
116
114
-60
-40
-20
20
40
60
80
100
Temperature (C)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
392
85C
8.2
FRC (MHz)
8.1
25C
8
7.9
-40C
7.8
7.7
7.6
1.5
2.5
3.5
4.5
5.5
VCC (V)
5.0V
8.4
3.0V
FRC (MHz)
8.3
8.2
8.1
7.9
-60
-40
-20
20
40
60
80
100
Temperature (C)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
393
85C
25C
-40C
14
FRC (MHz)
12
10
8
6
4
2
0
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
256
OSCCAL (X1)
85C
25C
-40C
25
ICC (A)
20
15
10
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
394
-40C
25C
85C
300
ICC (A)
250
200
150
100
50
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
-40C
25C
85C
200
ICC (A)
150
100
50
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
395
-40C
25C
85C
ICC (A)
6
5
4
3
2
1
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
-40C
25C
85C
90
80
ICC (A)
70
60
50
40
30
20
10
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
396
-40C
14
12
25C
ICC (mA)
10
8
85C
6
4
2
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
5.5V
0.3
5.0V
0.25
ICC (m A)
4.5V
0.2
4.0V
0.15
3.3V
0.1
2.7V
1.8V
0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
397
Figure 32-47. Reset Supply Current vs. VCC (1MHz - 16MHz, Excluding Current Through The Reset Pull-up)
4
5.5V
3.5
5.0V
ICC (m A)
4.5V
2.5
2
4.0V
1.5
1
3.3V
2.7V
0.5
1.8V
0
0
10
12
14
16
Frequency (MHz)
Pu lsewidth (ns)
2000
1500
1000
85C
25C
-40C
500
0
1.5
2.5
3.5
4.5
5.5
VCC (V)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
398
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0x1FF)
Reserved
...
Reserved
(0x13F)
Reserved
(0x13E)
Reserved
(0x13D)
Reserved
(0x13C)
Reserved
(0x13B)
Reserved
(0x13A)
Reserved
(0x139)
Reserved
(0x138)
Reserved
(0x137)
Reserved
(0x136)
UDR3
(0x135)
UBRR3H
(0x134)
UBRR3L
(0x133)
Reserved
(0x132)
UCSR3C
UMSEL31
(0x131)
UCSR3B
RXCIE3
page 218
USART3 Baud Rate Register High Byte
page 222
UMSEL30
UPM31
UPM30
TXCIE3
UDRIE3
RXEN3
Page
page 222
-
USBS3
UCSZ31
UCSZ30
UCPOL3
page 235
TXEN3
UCSZ32
RXB83
TXB83
page 234
page 233
(0x130)
UCSR3A
RXC3
TXC3
UDRE3
FE3
DOR3
UPE3
U2X3
MPCM3
(0x12F)
Reserved
(0x12E)
Reserved
(0x12D)
OCR5CH
page 160
(0x12C)
OCR5CL
page 160
(0x12B)
OCR5BH
page 160
(0x12A)
OCR5BL
page 160
(0x129)
OCR5AH
page 160
(0x128)
OCR5AL
page 160
(0x127)
ICR5H
page 161
(0x126)
ICR5L
page 161
(0x125)
TCNT5H
page 158
(0x124)
TCNT5L
(0x123)
Reserved
page 158
-
(0x122)
TCCR5C
FOC5A
FOC5B
FOC5C
page 157
(0x121)
TCCR5B
ICNC5
ICES5
WGM53
WGM52
CS52
CS51
CS50
page 156
(0x120)
TCCR5A
COM5A1
COM5A0
COM5B1
COM5B0
COM5C1
COM5C0
WGM51
WGM50
page 154
(0x11F)
Reserved
(0x11E)
Reserved
(0x11D)
Reserved
(0x11C)
Reserved
(0x11B)
Reserved
(0x11A)
Reserved
(0x119)
Reserved
(0x118)
Reserved
(0x117)
Reserved
(0x116)
Reserved
(0x115)
Reserved
(0x114)
Reserved
(0x113)
Reserved
(0x112)
Reserved
(0x111)
Reserved
(0x110)
Reserved
(0x10F)
Reserved
(0x10E)
Reserved
(0x10D)
Reserved
(0x10C)
Reserved
(0x10B)
PORTL
PORTL7
PORTL6
PORTL5
PORTL4
PORTL3
PORTL2
PORTL1
PORTL0
(0x10A)
DDRL
DDL7
DDL6
DDL5
DDL4
DDL3
DDL2
DDL1
DDL0
page 100
(0x109)
PINL
PINL7
PINL6
PINL5
PINL4
PINL3
PINL2
PINL1
PINL0
page 100
(0x108)
PORTK
PORTK7
PORTK6
PORTK5
PORTK4
PORTK3
PORTK2
PORTK1
PORTK0
page 99
(0x107)
DDRK
DDK7
DDK6
DDK5
DDK4
DDK3
DDK2
DDK1
DDK0
page 99
(0x106)
PINK
PINK7
PINK6
PINK5
PINK4
PINK3
PINK2
PINK1
PINK0
page 99
(0x105)
PORTJ
PORTJ7
PORTJ6
PORTJ5
PORTJ4
PORTJ3
PORTJ2
PORTJ1
PORTJ0
page 99
(0x104)
DDRJ
DDJ7
DDJ6
DDJ5
DDJ4
DDJ3
DDJ2
DDJ1
DDJ0
page 99
(0x103)
PINJ
PINJ7
PINJ6
PINJ5
PINJ4
PINJ3
PINJ2
PINJ1
PINJ0
page 99
(0x102)
PORTH
PORTH7
PORTH6
PORTH5
PORTH4
PORTH3
PORTH2
PORTH1
PORTH0
page 98
(0x101)
DDRH
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
page 99
page 100
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
399
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x100)
PINH
PINH7
PINH6
PINH5
PINH4
PINH3
PINH2
PINH1
PINH0
page 99
(0xFF)
Reserved
(0xFE)
Reserved
(0xFD)
Reserved
(0xFC)
Reserved
(0xFB)
Reserved
(0xFA)
Reserved
(0xF9)
Reserved
(0xF8)
Reserved
(0xF7)
Reserved
(0xF6)
Reserved
(0xF5)
Reserved
(0xF4)
Reserved
(0xF3)
Reserved
(0xF2)
Reserved
(0xF1)
Reserved
(0xF0)
Reserved
(0xEF)
Reserved
(0xEE)
Reserved
(0xED)
Reserved
(0xEC)
Reserved
(0xEB)
Reserved
(0xEA)
Reserved
(0xE9)
Reserved
(0xE8)
Reserved
(0xE7)
Reserved
(0xE6)
Reserved
(0xE5)
Reserved
(0xE4)
Reserved
(0xE3)
Reserved
(0xE2)
Reserved
(0xE1)
Reserved
(0xE0)
Reserved
(0xDF)
Reserved
(0xDE)
Reserved
(0xDD)
Reserved
(0xDC)
Reserved
(0xDB)
Reserved
(0xDA)
Reserved
(0xD9)
Reserved
(0xD8)
Reserved
(0xD7)
Reserved
(0xD6)
UDR2
(0xD5)
UBRR2H
(0xD4)
UBRR2L
(0xD3)
Reserved
(0xD2)
UCSR2C
UMSEL21
UMSEL20
(0xD1)
UCSR2B
RXCIE2
TXCIE2
(0xD0)
UCSR2A
RXC2
TXC2
(0xCF)
Reserved
page 218
USART2 Baud Rate Register High Byte
page 222
page 222
UPM21
UPM20
USBS2
UCSZ21
UCSZ20
UCPOL2
page 235
UDRIE2
RXEN2
TXEN2
UCSZ22
RXB82
TXB82
page 234
UDRE2
FE2
DOR2
UPE2
U2X2
MPCM2
page 233
(0xCE)
UDR1
(0xCD)
UBRR1H
(0xCC)
UBRR1L
(0xCB)
Reserved
(0xCA)
UCSR1C
UMSEL11
UMSEL10
(0xC9)
UCSR1B
RXCIE1
TXCIE1
(0xC8)
UCSR1A
RXC1
TXC1
(0xC7)
Reserved
page 218
USART1 Baud Rate Register High Byte
page 222
page 222
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
page 235
UDRIE1
RXEN1
TXEN1
UCSZ12
RXB81
TXB81
page 234
UDRE1
FE1
DOR1
UPE1
U2X1
MPCM1
page 233
(0xC6)
UDR0
(0xC5)
UBRR0H
(0xC4)
UBRR0L
(0xC3)
Reserved
(0xC2)
UCSR0C
UMSEL01
UMSEL00
(0xC1)
UCSR0B
RXCIE0
TXCIE0
(0xC0)
UCSR0A
RXC0
TXC0
(0xBF)
Reserved
(0xBE)
Reserved
(0xBD)
TWAMR
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
page 218
USART0 Baud Rate Register High Byte
page 222
page 222
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
page 235
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
page 234
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
page 234
TWAM1
TWAM0
page 264
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
400
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
page 261
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
page 263
(0xB9)
TWSR
TWS7
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
page 262
page 263
(0xB8)
TWBR
(0xB7)
Reserved
page 261
(0xB6)
ASSR
EXCLK
AS2
TCN2UB
OCR2AUB
OCR2BUB
TCR2AUB
TCR2BUB
(0xB5)
Reserved
(0xB4)
OCR2B
page 186
(0xB3)
OCR2A
page 186
(0xB2)
TCNT2
Timer/Counter2 (8 Bit)
(0xB1)
TCCR2B
FOC2A
FOC2B
WGM22
CS22
CS21
CS20
page 185
(0xB0)
TCCR2A
COM2A1
COM2A0
COM2B1
COM2B0
WGM21
WGM20
page 186
page 179
page 186
(0xAF)
Reserved
(0xAE)
Reserved
(0xAD)
OCR4CH
page 160
(0xAC)
OCR4CL
page 160
(0xAB)
OCR4BH
page 160
(0xAA)
OCR4BL
page 160
(0xA9)
OCR4AH
page 159
(0xA8)
OCR4AL
page 159
(0xA7)
ICR4H
page 161
(0xA6)
ICR4L
page 161
(0xA5)
TCNT4H
page 158
(0xA4)
TCNT4L
(0xA3)
Reserved
(0xA2)
TCCR4C
FOC4A
FOC4B
FOC4C
page 157
(0xA1)
TCCR4B
ICNC4
ICES4
WGM43
WGM42
CS42
CS41
CS40
page 156
(0xA0)
TCCR4A
COM4A1
COM4A0
COM4B1
COM4B0
COM4C1
COM4C0
WGM41
WGM40
page 154
(0x9F)
Reserved
page 158
-
(0x9E)
Reserved
(0x9D)
OCR3CH
page 159
(0x9C)
OCR3CL
page 159
(0x9B)
OCR3BH
page 159
(0x9A)
OCR3BL
page 159
(0x99)
OCR3AH
page 159
(0x98)
OCR3AL
page 159
(0x97)
ICR3H
page 161
(0x96)
ICR3L
page 161
(0x95)
TCNT3H
page 158
(0x94)
TCNT3L
(0x93)
Reserved
page 158
-
(0x92)
TCCR3C
FOC3A
FOC3B
FOC3C
page 157
(0x91)
TCCR3B
ICNC3
ICES3
WGM33
WGM32
CS32
CS31
CS30
page 156
(0x90)
TCCR3A
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
page 154
(0x8F)
Reserved
(0x8E)
Reserved
(0x8D)
OCR1CH
page 159
(0x8C)
OCR1CL
page 159
(0x8B)
OCR1BH
page 159
(0x8A)
OCR1BL
page 159
(0x89)
OCR1AH
page 159
(0x88)
OCR1AL
page 159
(0x87)
ICR1H
page 160
(0x86)
ICR1L
page 160
(0x85)
TCNT1H
page 158
(0x84)
TCNT1L
(0x83)
Reserved
page 158
-
(0x82)
TCCR1C
FOC1A
FOC1B
FOC1C
page 157
(0x81)
TCCR1B
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
page 156
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
COM1C1
COM1C0
WGM11
WGM10
page 154
(0x7F)
DIDR1
AIN1D
AIN0D
page 267
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
page 287
(0x7D)
DIDR2
ADC15D
ADC14D
ADC13D
ADC12D
ADC11D
ADC10D
ADC9D
ADC8D
page 288
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
page 281
(0x7B)
ADCSRB
ACME
MUX5
ADTS2
ADTS1
ADTS0
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 285
(0x79)
ADCH
page 286
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
401
Address
Name
(0x78)
ADCL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0x77)
Reserved
(0x76)
Reserved
(0x75)
XMCRB
XMBK
XMM2
XMM1
XMM0
(0x74)
XMCRA
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00
page 36
(0x73)
TIMSK5
ICIE5
OCIE5C
OCIE5B
OCIE5A
TOIE5
page 162
(0x72)
TIMSK4
ICIE4
OCIE4C
OCIE4B
OCIE4A
TOIE4
page 161
(0x71)
TIMSK3
ICIE3
OCIE3C
OCIE3B
OCIE3A
TOIE3
page 161
(0x70)
TIMSK2
OCIE2B
OCIE2A
TOIE2
page 188
(0x6F)
TIMSK1
ICIE1
OCIE1C
OCIE1B
OCIE1A
TOIE1
page 161
(0x6E)
TIMSK0
OCIE0B
OCIE0A
TOIE0
page 131
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
page 113
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
page 113
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
page 114
(0x6A)
EICRB
ISC71
ISC70
ISC61
ISC60
ISC51
ISC50
ISC41
ISC40
page 110
(0x69)
EICRA
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
page 110
(0x68)
PCICR
PCIE2
PCIE1
PCIE0
page 112
(0x67)
Reserved
(0x66)
OSCCAL
(0x65)
PRR1
PRTIM5
PRTIM4
PRTIM3
PRUSART3
PRUSART2
PRUSART1
page 56
(0x64)
PRR0
PRTWI
PRTIM2
PRTIM0
PRTIM1
PRSPI
PRUSART0
PRADC
page 55
(0x63)
Reserved
(0x62)
Reserved
(0x61)
CLKPR
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 48
(0x60)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
page 65
Page
page 286
page 38
page 48
0x3F (0x5F)
SREG
page 13
0x3E (0x5E)
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
page 15
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
page 15
0x3C (0x5C)
EIND
EIND0
page 16
0x3B (0x5B)
RAMPZ
RAMPZ1
RAMPZ0
page 16
0x3A (0x5A)
Reserved
0x39 (0x59)
Reserved
0x38 (0x58)
Reserved
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
0x35 (0x55)
MCUCR
JTD
PUD
IVSEL
IVCE
0x34 (0x54)
MCUSR
JTRF
WDRF
BORF
EXTRF
PORF
page 301
0x33 (0x53)
SMCR
SM2
SM1
SM0
SE
page 50
0x32 (0x52)
Reserved
0x31 (0x51)
OCDR
OCDR7
OCDR6
OCDR5
OCDR4
OCDR3
OCDR2
OCDR1
OCDR0
page 294
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
page 266
0x2F (0x4F)
Reserved
page 323
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
SPI2X
page 198
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
page 197
0x2B (0x4B)
GPIOR2
0x2A (0x4A)
GPIOR1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
page 130
0x27 (0x47)
OCR0A
page 130
0x26 (0x46)
TCNT0
Timer/Counter0 (8 Bit)
0x25 (0x45)
TCCR0B
FOC0A
FOC0B
WGM02
CS02
CS01
CS00
page 129
0x24 (0x44)
TCCR0A
COM0A1
COM0A0
COM0B1
COM0B0
WGM01
WGM00
page 126
0x23 (0x43)
GTCCR
TSM
PSRASY
PSRSYNC
0x22 (0x42)
EEARH
0x21 (0x41)
EEARL
0x20 (0x40)
EEDR
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
0x1D (0x3D)
EIMSK
INT7
INT6
INT5
INT4
INT3
0x1C (0x3C)
EIFR
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
0x1B (0x3B)
PCIFR
PCIF2
0x1A (0x3A)
TIFR5
ICF5
OCF5C
OCF5B
0x19 (0x39)
TIFR4
ICF4
OCF4C
0x18 (0x38)
TIFR3
ICF3
0x17 (0x37)
TIFR2
0x16 (0x36)
TIFR1
0x15 (0x35)
TIFR0
EEPM1
EEPM0
page 199
page 36
page 36
page 130
EERIE
page 34
page 34
page 34
EEMPE
EEPE
EERE
page 34
INT2
INT1
INT0
page 111
INTF1
INTF0
page 112
PCIF1
PCIF0
page 113
OCF5A
TOV5
page 162
OCF4B
OCF4A
TOV4
page 162
OCF3C
OCF3B
OCF3A
TOV3
page 162
OCF2B
OCF2A
TOV2
page 188
ICF1
OCF1C
OCF1B
OCF1A
TOV1
page 162
OCF0B
OCF0A
TOV0
page 131
page 36
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
402
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x14 (0x34)
PORTG
PORTG5
PORTG4
PORTG3
PORTG2
PORTG1
PORTG0
page 98
0x13 (0x33)
DDRG
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
page 98
0x12 (0x32)
PING
PING5
PING4
PING3
PING2
PING1
PING0
page 98
0x11 (0x31)
PORTF
PORTF7
PORTF6
PORTF5
PORTF4
PORTF3
PORTF2
PORTF1
PORTF0
page 97
0x10 (0x30)
DDRF
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
page 98
0x0F (0x2F)
PINF
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
page 98
0x0E (0x2E)
PORTE
PORTE7
PORTE6
PORTE5
PORTE4
PORTE3
PORTE2
PORTE1
PORTE0
page 97
0x0D (0x2D)
DDRE
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
page 97
0x0C (0x2C)
PINE
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
page 98
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
page 97
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
page 97
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
page 97
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
page 97
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
page 97
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
page 97
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 96
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 96
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 96
page 96
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
page 96
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
page 96
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the
64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
403
Operands
Description
Operation
Flags
#Clocks
Rd, Rr
Rd Rd + Rr
Z, C, N, V, H
ADC
Rd, Rr
Rd Rd + Rr + C
Z, C, N, V, H
ADIW
Rdl,K
Rdh:Rdl Rdh:Rdl + K
Z, C, N, V, S
SUB
Rd, Rr
Rd Rd - Rr
Z, C, N, V, H
SUBI
Rd, K
Rd Rd - K
Z, C, N, V, H
SBC
Rd, Rr
Rd Rd - Rr - C
Z, C, N, V, H
SBCI
Rd, K
Rd Rd - K - C
Z, C, N, V, H
SBIW
Rdl,K
Rdh:Rdl Rdh:Rdl - K
Z, C, N, V, S
AND
Rd, Rr
Rd Rd Rr
Z, N, V
ANDI
Rd, K
Rd Rd K
Z, N, V
OR
Rd, Rr
Logical OR Registers
Rd Rd v Rr
Z, N, V
ORI
Rd, K
Rd Rd v K
Z, N, V
EOR
Rd, Rr
Exclusive OR Registers
Rd Rd Rr
Z, N, V
COM
Rd
Ones Complement
Rd 0xFF Rd
Z, C, N, V
NEG
Rd
Twos Complement
Rd 0x00 Rd
Z, C, N, V, H
SBR
Rd,K
Rd Rd v K
Z, N, V
CBR
Rd,K
Rd Rd (0xFF - K)
Z, N, V
INC
Rd
Increment
Rd Rd + 1
Z, N, V
DEC
Rd
Decrement
Rd Rd 1
Z, N, V
TST
Rd
Rd Rd Rd
Z, N, V
CLR
Rd
Clear Register
Rd Rd Rd
Z, N, V
SER
Rd
Set Register
Rd 0xFF
None
MUL
Rd, Rr
Multiply Unsigned
R1:R0 Rd x Rr
Z, C
MULS
Rd, Rr
Multiply Signed
R1:R0 Rd x Rr
Z, C
MULSU
Rd, Rr
R1:R0 Rd x Rr
Z, C
FMUL
Rd, Rr
Z, C
FMULS
Rd, Rr
Z, C
FMULSU
Rd, Rr
Z, C
1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
BRANCH INSTRUCTIONS
RJMP
Relative Jump
PC PC + k + 1
None
None
None
None
3
4
PC Z
PC (EIND:Z)
JMP
Direct Jump
PC k
RCALL
IJMP
EIJMP
PC PC + k + 1
None
ICALL
None
EICALL
PC Z
PC (EIND:Z)
None
PC k
None
RET
Subroutine Return
PC STACK
None
RETI
Interrupt Return
PC STACK
if (Rd = Rr) PC PC + 2 or 3
None
CALL
CPSE
Rd,Rr
5
1/2/3
CP
Rd,Rr
Compare
Rd Rr
Z, N, V, C, H
CPC
Rd,Rr
Rd Rr C
Z, N, V, C, H
CPI
Rd,K
Rd K
Z, N, V, C, H
SBRC
Rr, b
if (Rr(b)=0) PC PC + 2 or 3
None
1
1/2/3
SBRS
Rr, b
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
P, b
if (P(b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
P, b
if (P(b)=1) PC PC + 2 or 3
None
1/2/3
BRBS
s, k
None
1/2
BRBC
s, k
None
1/2
BREQ
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
1/2
BRNE
if (Z = 0) then PC PC + k + 1
None
BRCS
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
if (C = 0) then PC PC + k + 1
None
1/2
BRSH
if (C = 0) then PC PC + k + 1
None
1/2
BRLO
Branch if Lower
if (C = 1) then PC PC + k + 1
None
1/2
BRMI
Branch if Minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
Branch if Plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
if (T = 0) then PC PC + k + 1
None
1/2
BRVS
if (V = 1) then PC PC + k + 1
None
1/2
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
404
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
if ( I = 1) then PC PC + k + 1
None
1/2
BRID
if ( I = 0) then PC PC + k + 1
None
1/2
P,b
I/O(P,b) 1
None
CBI
P,b
I/O(P,b) 0
None
LSL
Rd
Z, C, N, V
LSR
Rd
Z, C, N, V
ROL
Rd
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z, C, N, V
ROR
Rd
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z, C, N, V
ASR
Rd
Z, C, N, V
SWAP
Rd
Swap Nibbles
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
None
BSET
Flag Set
SREG(s) 1
SREG(s)
BCLR
Flag Clear
SREG(s) 0
SREG(s)
BST
Rr, b
T Rr(b)
BLD
Rd, b
Rd(b) T
None
SEC
Set Carry
C1
CLC
Clear Carry
C0
SEN
N1
CLN
N0
SEZ
Z1
CLZ
Z0
SEI
I1
CLI
I 0
SES
S1
CLS
S0
SEV
V1
CLV
V0
SET
Set T in SREG
T1
CLT
Clear T in SREG
T0
SEH
CLH
H1
H0
H
H
1
1
Rd, Rr
Rd, Rr
Rd Rr
Rd+1:Rd Rr+1:Rr
None
MOVW
None
LDI
Rd, K
Load Immediate
Rd K
None
LD
Rd, X
Load Indirect
Rd (X)
None
LD
Rd, X+
Rd (X), X X + 1
None
LD
Rd, - X
X X - 1, Rd (X)
None
LD
Rd, Y
Load Indirect
Rd (Y)
None
LD
Rd, Y+
Rd (Y), Y Y + 1
None
LD
Rd, - Y
Y Y - 1, Rd (Y)
None
LDD
Rd,Y+q
Rd (Y + q)
None
LD
Rd, Z
Load Indirect
Rd (Z)
None
LD
Rd, Z+
Rd (Z), Z Z+1
None
LD
Rd, -Z
Z Z - 1, Rd (Z)
None
LDD
Rd, Z+q
Rd (Z + q)
None
2
2
LDS
Rd, k
Rd (k)
None
ST
X, Rr
Store Indirect
(X) Rr
None
ST
X+, Rr
(X) Rr, X X + 1
None
ST
- X, Rr
X X - 1, (X) Rr
None
ST
Y, Rr
Store Indirect
(Y) Rr
None
ST
Y+, Rr
(Y) Rr, Y Y + 1
None
ST
- Y, Rr
Y Y - 1, (Y) Rr
None
STD
Y+q,Rr
(Y + q) Rr
None
ST
Z, Rr
Store Indirect
(Z) Rr
None
2
2
ST
Z+, Rr
(Z) Rr, Z Z + 1
None
ST
-Z, Rr
Z Z - 1, (Z) Rr
None
STD
Z+q,Rr
(Z + q) Rr
None
STS
k, Rr
(k) Rr
None
R0 (Z)
None
Rd (Z)
None
3
3
LPM
LPM
Rd, Z
LPM
Rd, Z+
ELPM
ELPM
Rd, Z
ELPM
Rd, Z+
SPM
IN
Rd, P
Rd (Z), Z Z+1
None
R0 (RAMPZ:Z)
None
Rd (RAMPZ:Z)
None
3
3
None
(Z) R1:R0
None
In Port
Rd P
None
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
405
Mnemonics
Operands
Description
Operation
Flags
#Clocks
OUT
P, Rr
Out Port
P Rr
None
PUSH
Rr
STACK Rr
None
POP
Rd
Rd STACK
None
No Operation
None
SLEEP
Sleep
None
WDR
BREAK
Watchdog Reset
Break
None
None
1
N/A
Note:
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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ATmega640
Speed [MHz](2)
16
Notes:
Power Supply
Ordering Code
Package(1)(3)
1.8 - 5.5V
ATmega640V-8AU
ATmega640V-8AUR(4)
ATmega640V-8CU
ATmega640V-8CUR(4)
100A
100A
100C1
100C1
2.7 - 5.5V
ATmega640-16AU
ATmega640-16AUR(4)
ATmega640-16CU
ATmega640-16CUR(4)
100A
100A
100C1
100C1
Operation Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. See Speed Grades on page 357.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
4. Tape & Reel.
Package Type
100A
100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
100C1
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
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35.2
ATmega1280
Speed [MHz](2)
16
Notes:
Power Supply
Ordering Code
Package(1)(3)
1.8V - 5.5V
ATmega1280V-8AU
ATmega1280V-8AUR(4)
ATmega1280V-8CU
ATmega1280V-8CUR(4)
100A
100A
100C1
100C1
2.7V - 5.5V
ATmega1280-16AU
ATmega1280-16AUR(4)
ATmega1280-16CU
ATmega1280-16CUR(4)
100A
100A
100C1
100C1
Operation Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. See Speed Grades on page 357.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
4. Tape & Reel.
Package Type
100A
100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
100C1
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
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35.3
ATmega1281
Speed [MHz](2)
16
Notes:
Ordering Code
Package(1)(3)
1.8 - 5.5V
ATmega1281V-8AU
ATmega1281V-8AUR(4)
ATmega1281V-8MU
ATmega1281V-8MUR(4)
64A
64A
64M2
64M2
2.7 - 5.5V
ATmega1281-16AU
ATmega1281-16AUR(4)
ATmega1281-16MU
ATmega1281-16MUR(4)
64A
64A
64M2
64M2
Power Supply
Operation Range
Industrial
(-40C to 85C)
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. See Speed Grades on page 357.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
4. Tape & Reel.
Package Type
64A
64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M2
64-pad, 9mm 9mm 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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35.4
ATmega2560
Speed [MHz](2)
16
Notes:
Power Supply
Ordering Code
Package(1)(3)
1.8V - 5.5V
ATmega2560V-8AU
ATmega2560V-8AUR(4)
ATmega2560V-8CU
ATmega2560V-8CUR(4)
100A
100A
100C1
100C1
4.5V - 5.5V
ATmega2560-16AU
ATmega2560-16AUR(4)
ATmega2560-16CU
ATmega2560-16CUR(4)
100A
100A
100C1
100C1
Operation Range
1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. See Speed Grades on page 357.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
4. Tape & Reel.
Package Type
100A
100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
100C1
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
410
35.5
ATmega2561
Speed [MHz](2)
16
Notes:
Power Supply
Ordering Code
Package(1)(3)
1.8V - 5.5V
ATmega2561V-8AU
ATmega2561V-8AUR(4)
ATmega2561V-8MU
ATmega2561V-8MUR(4)
64A
64A
64M2
64M2
4.5V - 5.5V
ATmega2561-16AU
ATmega2561-16AUR(4)
ATmega2561-16MU
ATmega2561-16MUR(4)
64A
64A
64M2
64M2
Operation Range
Industrial
(-40C to 85C)
1. This device can also be supplied in wafer form.Contact your local Atmel sales office for detailed ordering information and
minimum quantities.
2. See Speed Grades on page 357.
3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
4. Tape & Reel.
Package Type
64A
64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M2
64-pad, 9mm 9mm 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
411
100A
PIN 1
B
PIN 1 IDENTIFIER
E1
D1
D
C
0~7
A1
A2
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
1.20
A1
0.05
0.15
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
MAX
A2
0.95
1.00
1.05
15.75
16.00
16.25
D1
13.90
14.00
14.10
15.75
16.00
16.25
E1
13.90
14.00
14.10
0.17
0.27
0.09
0.20
0.45
0.75
NOTE
Note 2
Note 2
0.50 TYP
2010-10-20
100A
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
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36.2
100C1
0.12 Z
Marked A1 Identifier
SIDE VIEW
TOP VIEW
A1
b
A1 Corner
0.90 TYP
10
0.90 TYP
B
C
D
COMMON DIMENSIONS
(Unit of Measure = mm)
D1
SYMBOL
MIN
NOM
MAX
1.10
1.20
A1
0.30
0.35
0.40
8.90
9.00
9.10
8.90
9.00
9.10
E1
BOTTOM VIEW
D1
7.10
7.20
7.30
E1
7.10
7.20
7.30
0.35
0.40
0.45
NOTE
0.80 TYP
5/25/06
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm
Chip Array BGA Package (CBGA)
DRAWING NO.
100C1
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
REV.
A
413
36.3
64A
PIN 1
PIN 1 IDENTIFIER
E1
D1
D
0~7
A1
A2
L
COMMON DIMENSIONS
(Unit of measure = mm)
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
15.75
16.00
16.25
D1
13.90
14.00
14.10
15.75
16.00
16.25
E1
13.90
14.00
14.10
0.30
0.45
0.09
0.20
0.45
0.75
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
64A
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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36.4
64M2
Marked pin# 1 I D
SEATING PLANE
A1
TOP VIEW
A3
A
K
0.08 C
Pin #1 Corner
D2
1
2
3
SIDE VIEW
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of measure = mm)
E2
Option B
Pin #1
Chamfer
(C 0.30)
SYMBOL
MIN
NOM
MAX
0.80
0.90
1.00
A1
0.02
0.05
A3
Option C
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
0.20 REF
0.18
0.25
0.30
8.90
9.00
9.10
D2
7.50
7.65
7.80
8.90
9.00
9.10
E2
7.50
7.65
7.80
NOTE
0.50 BSC
0.35
0.40
0.45
0.20
0.27
0.40
2014-02-12
TITLE
2325 Orchard Parkway
64M2, 64-pad, 9 x 9 x 1.0mm Bod y, Lead Pitch 0.50mm ,
San Jose, CA 95131
7.65mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
64M2
REV.
E
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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415
37. Errata
37.1
ATmega640 rev. B
Inaccurate ADC conversion in differential mode with 200 gain
High current consumption in sleep mode
1. Inaccurate ADC conversion in differential mode with 200 gain
With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB.
Problem Fix/Workaround
None.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will
increase during sleep when executing the SLEEP instruction directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
37.2
ATmega640 rev. A
Inaccurate ADC conversion in differential mode with 200 gain
High current consumption in sleep mode
1.
37.3
ATmega1280 rev. B
High current consumption in sleep mode
1. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will
increase during sleep when executing the SLEEP instruction directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
37.4
ATmega1280 rev. A
Inaccurate ADC conversion in differential mode with 200 gain
High current consumption in sleep mode
1.
416
Problem Fix/Workaround
None.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will
increase during sleep when executing the SLEEP instruction directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
37.5
ATmega1281 rev. B
High current consumption in sleep mode
1. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will
increase during sleep when executing the SLEEP instruction directly after a SEI instruction.
Problem Fix/Workaround
Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
37.6
ATmega1281 rev. A
Inaccurate ADC conversion in differential mode with 200 gain
High current consumption in sleep mode
1.
37.7
ATmega2560 rev. F
ADC differential input amplification by 46dB (200x) not functional
1. ADC differential input amplification by 46dB (200x) not functional
Problem Fix/Workaround
None.
37.8
ATmega2560 rev. E
No known errata.
37.9
ATmega2560 rev. D
Not sampled.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
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1.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
419
1.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
420
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
421
38.1
Rev. 2549Q-02/2014
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
38.2
Rev. 2549P-10/2012
1.
2.
3.
38.3
Rev. 2549O-05/2012
1.
2.
3.
38.4
Updated the Reset Sources on page 57. Brown-out Reset: The MCU is reset when the supply voltage
AVcc is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
Updated the Figure 12-1 on page 58. Power-on reset is now connected to AVcc and not to Vcc.
Updated the content in Brown-out Detection on page 59. Replaced Vcc by AVcc throughout the section.
Updated the Figure 12-5 on page 60. Replaced Vcc by AVcc.
Updated External Interrupts on page 109. Removed the text Note that recognition of falling or rising
edge......
Updated the description of PCMSK1 Pin Change Mask Register 1 on page 113. The description mentions "PCIE1 bit in EIMSK". This has been changed to PCIE1 bit in PCICR.
Updated Ordering Information in ATmega2561 on page 411.
Removed Errata Inaccurate ADC conversion in differential mode with 200 gain from ATmega1280 rev.
B on page 416 and from ATmega1281 rev. B on page 417
Updated Errata in ATmega2560 rev. F on page 417 and in ATmega2561 rev. F on page 419.
Updated the datasheet with new Atmel brand (new logo and addresses).
The datasheet changed status from Preliminary to Complete. Removed Preliminary from the front page.
Replaced Figure 10-3 on page 44 by a new one.
Updated the last page to include the new address for Atmel Japan site.
Rev. 2549N-05/2011
1.
2.
3.
4.
Added Atmel QTouch Library Support and QTouch Sensing Capablity Features.
Updated Cross-reference in Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 on page 65.
Updated Assembly codes in section USART Initialization on page 205.
Added Standard Power-On Reset on page 360.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
422
5.
6.
7.
38.5
Rev. 2549M-09/2010
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
38.6
Updated typos in Figure 26-9 on page 276 and in Figure 26-10 on page 277.
Note is added below Table 1-1 on page 3.
The values for typical characteristics in Table 31-9 on page 365 and Table 31-10 on page 366, has been
rounded.
Units for tRST and tBOD in Table 31-3 on page 360 have been changed from ns to s.
The figure text for Table 31-2 on page 359 has been changed.
Text in first column in Table 30-3 on page 326 has been changed from Fuse Low Byte to Extended
Fuse Byte.
The text in Power Reduction Register on page 52 has been changed.
The value of the inductor in Figure 26-9 on page 276 and Figure 26-10 on page 277 has been changed to
10H.
Port A has been changed into Port K in the first paragraph of Features on page 268.
Minimum wait delay for tWD_EEPROM in Table 30-16 on page 340 has been changed from 9.0ms to 3.6ms
Dimension A3 is added in 64M2 on page 415.
Several cross-references are corrected.
COM0A1:0 on page 127 is corrected to COM0B1:0.
Corrected some Figure and Table numbering.
Updated Section 10.6 Low Frequency Crystal Oscillator on page 43.
Rev. 2549L-08/07
1.
2.
3.
4.
5.
6.
7.
8.
9.
38.7
Rev. 2549K-01/07
1.
2.
3.
423
4.
5.
6:
7.
8.
9.
10.
38.8
Rev. 2549J-09/06
1.
2.
3.
4.
5.
6.
38.9
Rev. 2549I-07/06
1.
2.
3.
1.
2.
3.
1.
2.
3.
4.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
424
5.
6.
7.
8.
9.
10.
1.
2.
3.
4.
Updated Figure 9-3 on page 29, Figure 9-4 on page 30 and Figure 9-5 on page 30.
Updated Table 20-2 on page 182 and Table 20-3 on page 182.
Updated Features in ADC Analog to Digital Converter on page 268.
Updated Fuse Bits on page 326.
1.
2.
3.
4.
5.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549QAVR02/2014
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1.
2.
3.
4.
5.
6.
7.
8.
1.
2.
3.
4.
1.
Initial version.
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Table of Contents
Features .................................................................................................... 1
1
Overview ................................................................................................... 5
2.1Block Diagram ...........................................................................................................5
2.2Comparison Between ATmega1281/2561 and ATmega640/1280/2560 ...................7
2.3Pin Descriptions .........................................................................................................7
Resources ............................................................................................... 10
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13 I/O-Ports .................................................................................................. 67
13.1Introduction ............................................................................................................67
13.2Ports as General Digital I/O ...................................................................................68
13.3Alternate Port Functions ........................................................................................72
13.4Register Description for I/O-Ports ..........................................................................96
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19.2Description ...........................................................................................................167
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24.1Features ..............................................................................................................236
24.22-wire Serial Interface Bus Definition ..................................................................236
24.3Data Transfer and Frame Format ........................................................................237
24.4Multi-master Bus Systems, Arbitration, and Synchronization ..............................239
24.5Overview of the TWI Module ...............................................................................241
24.6Using the TWI ......................................................................................................244
24.7Transmission Modes ...........................................................................................247
24.8Multi-master Systems and Arbitration ..................................................................259
24.9Register Description ............................................................................................261
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