Professional Documents
Culture Documents
588 VTTY: Console port: waiting connection on tcp port 2004 for
protocol IPv4 (FD 17)
Jan 02 18:38:36.589 VTTY: AUX port: waiting connection on tcp port 2504 for prot
ocol IPv4 (FD 18)
Jan 02 18:38:36.600 slot0: C/H/S settings = 16/4/32
Jan 02 18:38:36.606 slot1: C/H/S settings = 0/4/32
Jan 02 18:38:36.915 C3745_BOOT: starting instance (CPU0 PC=0xffffffffbfc00000,id
le_pc=0x60bc2cf8,JIT on)
Jan 02 18:38:36.916 CPU0: CPU_STATE: Starting CPU (old state=2)...
Jan 02 18:38:36.990 ROM: Microcode has started.
Jan 02 18:38:36.997 ROM: trying to read bootvar 'WARM_REBOOT'
Jan 02 18:38:36.999 CPU0: IO_FPGA: write to unknown addr 0x30, value=0x0, pc=0xf
fffffff80bb88c8 (size=1)
Jan 02 18:38:36.999 CPU0: IO_FPGA: read from unknown addr 0x30, pc=0xffffffff80b
b88dc (size=1)
Jan 02 18:38:37.110 CPU0: IO_FPGA: read from unknown addr 0x6, pc=0x60252ef0 (si
ze=2)
Jan 02 18:38:37.111 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x6025ac2
4 (size=2)
Jan 02 18:38:37.111 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x0, pc
=0x6025ac34 (size=2)
Jan 02 18:38:37.111 ROM: unhandled syscall 0x00000047 at pc=0x60bba074 (a1=0x800
07df4,a2=0x63803338,a3=0x0000011c)
Jan 02 18:38:37.407 ROM: trying to read bootvar 'RANDOM_NUM'
Jan 02 18:38:37.440 CPU0: IO_FPGA: write to unknown addr 0x2e, value=0x20, pc=0x
60268558 (size=2)
Jan 02 18:38:37.441 CPU0: PCI: read request for device 'gt96100' at pc=0x6026b44
4: bus=0,device=0,function=0,reg=0x00
Jan 02 18:38:37.441 CPU0: PCI: read request for device 'gt96100' at pc=0x6026b44
8: bus=0,device=0,function=0,reg=0x00
Jan 02 18:38:37.441 CPU0: PCI: read request for device 'gt96100' at pc=0x6026b1f
8: bus=0,device=0,function=0,reg=0x08
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x10
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x10
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x90
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x90
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x10000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x14
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x10000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x14
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x10000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x94
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x10000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x94
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x04000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x20
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x04000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x20
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x04000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0xa0
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x04000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0xa0
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000146) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x04
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000146) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x04
Jan 02 18:38:37.441 CPU0: PCI: write request (data=0x00000146) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x84
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000146) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x84
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000007) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x0c
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000007) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x0c
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000007) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x8c
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000007) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x8c
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x10
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x10
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x90
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x00000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x90
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x20000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x14
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x20000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x14
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x20000000) for device 'gt961
00' at pc=0x6026b340: bus=0,device=0,function=0,reg=0x94
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0x20000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0x94
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xc0000000) for unknown devic
e at pc=0x6026b340 (bus=0,device=0,function=1,reg=0x10).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xc0000000) for unknown devic
e at pc=0x6026b344 (bus=0,device=0,function=1,reg=0x10).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xc0000000) for unknown devic
e at pc=0x6026b340 (bus=0,device=0,function=1,reg=0x90).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xc0000000) for unknown devic
e at pc=0x6026b344 (bus=0,device=0,function=1,reg=0x90).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xe0000000) for unknown devic
e at pc=0x6026b340 (bus=0,device=0,function=1,reg=0x14).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xe0000000) for unknown devic
e at pc=0x6026b344 (bus=0,device=0,function=1,reg=0x14).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xe0000000) for unknown devic
e at pc=0x6026b340 (bus=0,device=0,function=1,reg=0x94).
Jan 02 18:38:37.442 CPU0: PCI: write request (data=0xe0000000) for unknown devic
e at pc=0x6026b344 (bus=0,device=0,function=1,reg=0x94).
Jan 02 18:38:37.442 CPU0: IO_FPGA: write to unknown addr 0x4c, value=0xf000, pc=
0x60268b9c (size=2)
Jan 02 18:38:37.442 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x00
Jan 02 18:38:37.442 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x00
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x0c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x0c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00040100) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x18
Jan 02 18:38:37.443 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00040100) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x18
Jan 02 18:38:37.443 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x02801f00) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x1c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x02801f00) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x1c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x4d704d00) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x20
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x4d704d00) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x20
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00014d01) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x24
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00014d01) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x24
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x30
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x30
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x64
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x64
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x68
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x68
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0xf0
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0xf0
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x00
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x00
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x0c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x0c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00080500) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x18
Jan 02 18:38:37.443 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00080500) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x18
Jan 02 18:38:37.443 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x02803f20) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x1c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x02803f20) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x1c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x4df04d80) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x20
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x4df04d80) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x20
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00014d81) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x24
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00014d81) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x24
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x30
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x30
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x64
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x64
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x68
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x68
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:37.443 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0xf0
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0xf0
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=3,function=0,reg=0x00
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=3,function=0,reg=0x00
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=3,function=0,reg=0x40
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=3,function=0,reg=0x40
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x04
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x04
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x0c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x0c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x000c0900) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x18
Jan 02 18:38:37.444 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x000c0900) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x18
Jan 02 18:38:37.444 PCI: PCI bridge 0,3,0 -> pri: 00, sec: 09, sub: 12
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x02809f80) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x1c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x02809f80) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x1c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x4e704e00) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x20
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x4e704e00) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x20
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00014e01) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x24
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00014e01) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x24
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x30
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x30
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x3c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x3c
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x40
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x40
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x64
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x64
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x68
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x68
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0x04
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0x04
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=3,function=0,reg=0xf0
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=3,function=0,reg=0xf0
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=4,function=0,reg=0x00
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=4,function=0,reg=0x00
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=4,function=0,reg=0x40
Jan 02 18:38:37.444 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=4,function=0,reg=0x40
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
Jan
0b'
Jan
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
0b'
Jan
00'
Jan
00'
Jan
00'
02
at
02
at
02
at
02
at
02
at
02
02
at
02
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
02
at
Jan 02 18:38:37.444 CPU0: PCI: write request (data=0x24000000) for device 'gt961
00' at pc=0x6026b344: bus=0,device=0,function=0,reg=0xa0
Jan 02 18:38:37.445 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x6025af3c (s
ize=2)
Jan 02 18:38:39.891 ROM: unhandled syscall 0x0000003e at pc=0x60bba074 (a1=0x800
07de4,a2=0x63803314,a3=0x000000f8)
Jan 02 18:38:39.891 ROM: unhandled syscall 0x00000047 at pc=0x60bba074 (a1=0x800
07dec,a2=0x63803338,a3=0x0000011c)
Jan 02 18:38:40.866 CPU0: JIT: partial JIT flush (count=174)
Jan 02 18:38:40.908 CPU0: JIT: flushing data structures (compiled pages=222)
Jan 02 18:38:40.992 CPU0: JIT: partial JIT flush (count=175)
Jan 02 18:38:41.003 ROM: trying to read bootvar 'BOOT'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'CONFIG_FILE'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'BOOTLDR'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'RSHELF'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'DSHELF'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'DSHELFINFO'
Jan 02 18:38:41.003 ROM: trying to read bootvar 'RESET_COUNTER'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'CHRG_LOCRECSN'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'CHRG_ID'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'SLOTCACHE'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'OVERTEMP'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'DIAG'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'DIAMETER_ORIGIN_ID'
Jan 02 18:38:41.004 ROM: trying to read bootvar 'WARM_REBOOT'
Jan 02 18:38:41.051 CPU0: JIT: flushing data structures (compiled pages=227)
Jan 02 18:38:41.133 CPU0: JIT: partial JIT flush (count=182)
Jan 02 18:38:41.233 CPU0: IO_FPGA: read from unknown addr 0x16, pc=0x608fa658 (s
ize=2)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c080022 at p
c=0x608fa248 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c08002b at p
c=0x608fa28c (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c08002b at p
c=0x608fa298, value=0x00000020 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c08002b at p
c=0x608fa29c (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c08002b at p
c=0x608fa2a4, value=0x00000000 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c08002b at p
c=0x608fa2b0 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c08002b at p
c=0x608fa2bc, value=0x00000040 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c080023 at p
c=0x608fa2d0 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c080023 at p
c=0x608fa2dc, value=0x00000000 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c080023 at p
c=0x608fa2e8 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c080023 at p
c=0x608fa2f8, value=0x00000080 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc110 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: write access to undefined address 0x3c000002 at p
c=0x608fc11c, value=0x00000080 (size=1)
Jan 02 18:38:41.234 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc120 (size=1)
Jan 02 18:38:41.341 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.459 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.564 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.675 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.783 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.877 CPU0: MTS: read access to undefined address 0x3c000002 at p
c=0x608fc14c (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c080007 at p
c=0x608fa3e4, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c080008 at p
c=0x608fa3ec, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c080009 at p
c=0x608fa3f4, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c08000a at p
c=0x608fa3f8, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c08000b at p
c=0x608fa3fc, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: write access to undefined address 0x3c08000c at p
c=0x608fa400, value=0x00000002 (size=1)
Jan 02 18:38:41.878 CPU0: MTS: read access to undefined address 0x3c080022 at p
c=0x608fb314 (size=1)
Jan 02 18:38:41.894 CPU0: JIT: flushing data structures (compiled pages=231)
Jan 02 18:38:41.979 CPU0: JIT: partial JIT flush (count=193)
Jan 02 18:38:42.024 CPU0: JIT: flushing data structures (compiled pages=231)
Jan 02 18:38:42.091 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x6026860
0 (size=2)
Jan 02 18:38:42.091 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x1000,
pc=0x60268608 (size=2)
Jan 02 18:38:42.091 CPU0: IO_FPGA: read from unknown addr 0x10000a, pc=0x6026860
0 (size=2)
Jan 02 18:38:42.091 CPU0: IO_FPGA: write to unknown addr 0x10000a, value=0x2000,
pc=0x60268608 (size=2)
Jan 02 18:38:42.305 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: write request (data=0x00400000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: write request (data=0x00400000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.305 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: write request (data=0x00400000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: write request (data=0x00400000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.394 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.482 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x00
Jan 02 18:38:42.482 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x00
Jan 02 18:38:42.482 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:42.482 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x0c
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x0c
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x00040100) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x18
Jan 02 18:38:42.482 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x00040100) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x18
Jan 02 18:38:42.482 PCI: PCI bridge 0,1,0 -> pri: 00, sec: 01, sub: 04
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x02801f00) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x1c
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x02801f00) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x1c
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x4d704d00) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x20
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x4d704d00) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x20
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x00014d01) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x24
Jan 02 18:38:42.482 CPU0: PCI: write request (data=0x00014d01) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x24
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x30
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x30
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x3c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x64
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x64
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x68
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x68
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=1,function=0,reg=0xf0
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=1,function=0,reg=0xf0
Jan 02 18:38:42.483 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x00
Jan 02 18:38:42.483 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x00
Jan 02 18:38:42.483 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
4: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: read request for device 'ti2050b' at pc=0x6026b45
8: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0xffff0000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x0c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x0000f810) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x0c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00080500) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x18
Jan 02 18:38:42.483 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00080500) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x18
Jan 02 18:38:42.483 PCI: PCI bridge 0,2,0 -> pri: 00, sec: 05, sub: 08
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x02803f20) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x1c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x02803f20) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x1c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x4df04d80) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x20
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x4df04d80) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x20
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00014d81) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x24
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00014d81) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x24
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x30
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00200020) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x30
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x03000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x3c
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x40
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x64
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x64
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x68
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000000) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x68
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000007) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0x04
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b320: bus=0,device=2,function=0,reg=0xf0
Jan 02 18:38:42.483 CPU0: PCI: write request (data=0x00000001) for device 'ti205
0b' at pc=0x6026b32c: bus=0,device=2,function=0,reg=0xf0
Jan 02 18:38:42.675 CPU0: JIT: partial JIT flush (count=167)
Jan 02 18:38:42.796 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
54: bus=1,device=0,function=0,reg=0x00
Jan 02 18:38:42.797 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
58: bus=1,device=0,function=0,reg=0x00
Jan 02 18:38:42.797 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
54: bus=1,device=0,function=0,reg=0x00
Jan 02 18:38:42.797 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
58: bus=1,device=0,function=0,reg=0x00
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x4d000000) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x10
Jan 02 18:38:42.797 NM-4T(1): registers are mapped at 0x4d000000
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x4d000000) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x10
Jan 02 18:38:42.797 NM-4T(1): registers are mapped at 0x4d000000
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x4d002000) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x14
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x4d002000) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x14
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x00000008) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x40
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x00000008) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x40
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x0000f800) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x0c
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x0000f800) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x0c
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x00000006) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x04
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x00000006) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x04
Jan 02 18:38:42.797 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
54: bus=1,device=0,function=0,reg=0x08
Jan 02 18:38:42.797 CPU0: PCI: read request for device 'NM-4T(1)' at pc=0x6026b4
58: bus=1,device=0,function=0,reg=0x08
Jan 02 18:38:42.797 NM-4T(1): channel 0: unknown value for CRC ctrl reg 0x0600
Jan 02 18:38:42.797 NM-4T(1): channel 0: CRC size set to 0x0002
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x0000f800) for device 'NM-4T
(1)' at pc=0x6026b320: bus=1,device=0,function=0,reg=0x0c
Jan 02 18:38:42.797 CPU0: PCI: write request (data=0x0000f800) for device 'NM-4T
(1)' at pc=0x6026b32c: bus=1,device=0,function=0,reg=0x0c
Jan 02 18:38:42.797 NM-4T(1): channel 0: unknown value for CRC ctrl reg 0x0000
Jan 02 18:38:42.797 NM-4T(1): channel 0: CRC size set to 0x0002
Jan 02 18:38:42.803 NM-4T(1): channel 0 disabled
Jan 02 18:38:42.806 NM-4T(1): channel 0: CRC size set to 0x0002
Jan 02 18:38:42.806 NM-4T(1): channel 0: clock rate set to 2016000
Jan 02 18:38:42.806 NM-4T(1): channel 0 enabled
Jan 02 18:38:42.806 NM-4T(1): unknown command 0x3000c
Jan 02 18:38:42.807 NM-4T(1): channel 0 enabled
Jan 02 18:38:42.809 NM-4T(1): channel 1 disabled
Jan 02 18:38:42.818
Jan 02 18:38:42.818
Jan 02 18:38:42.818
Jan 02 18:38:42.818
Jan 02 18:38:42.818
Jan 02 18:38:42.820
Jan 02 18:38:42.821
Jan 02 18:38:42.821
Jan 02 18:38:42.821
Jan 02 18:38:42.821
Jan 02 18:38:42.821
Jan 02 18:38:42.823
Jan 02 18:38:42.823
Jan 02 18:38:42.823
Jan 02 18:38:42.824
Jan 02 18:38:42.824
Jan 02 18:38:42.824
Jan 02 18:38:42.825
Jan 02 18:38:42.826
Jan 02 18:38:42.826
Jan 02 18:38:42.826
Jan 02 18:38:42.826
Jan 02 18:38:42.826
Jan 02 18:38:42.861
Jan 02 18:38:42.876
ize=2)
Jan 02 18:38:42.878
025c100 (size=2)
Jan 02 18:38:42.878
ize=2)
Jan 02 18:38:42.878
6025c128 (size=2)
Jan 02 18:38:42.943
Jan 02 18:38:42.999
Jan 02 18:38:43.055
Jan 02 18:38:43.104
Jan 02 18:38:43.166
Jan 02 18:38:43.239
Jan 02 18:38:43.575
Jan 02 18:38:43.614
Jan 02 18:38:43.683
Jan 02 18:38:43.743
Jan 02 18:38:43.795
Jan 02 18:38:43.844
Jan 02 18:38:43.905
Jan 02 18:38:44.021
Jan 02 18:38:44.113
Jan 02 18:38:44.152
Jan 02 18:38:44.211
Jan 02 18:38:44.268
Jan 02 18:38:44.327
Jan 02 18:38:44.379
Jan 02 18:38:44.436
Jan 02 18:38:44.507
Jan 02 18:38:44.727
Jan 02 18:38:44.757
Jan 02 18:38:44.819
Jan 02 18:38:44.948
Jan 02 18:38:45.305
Jan 02 18:38:45.362
pages=232)
pages=231)
pages=343)
pages=345)
pages=352)
pages=352)
pages=357)
pages=350)
pages=354)
pages=357)
pages=356)
pages=358)
pages=354)
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
c=0x608fb2f0 (size=1)
Jan 02 18:38:56.502 CPU0:
Jan 02 18:38:56.512 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:56.847 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:57.204 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:57.550 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:57.880 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:58.193 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:58.564 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:58.934 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:59.224 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:59.540 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:38:59.875 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:00.265 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:00.615 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:00.906 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:01.257 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:01.587 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:01.964 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:02.427 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:02.995 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:03.563 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:04.118 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:04.711 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:05.338 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:06.004 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:06.560 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:07.131 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:07.666 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:08.170 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:08.638 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:39:35.590 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:35.817 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:36.038 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:36.290 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:36.521 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:36.774 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:36.995 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:37.246 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:37.475 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:37.727 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:37.948 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:38.204 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:38.441 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:38.721 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:38.948 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:39.015 CPU0: JIT: partial JIT flush (count=177)
Jan 02 18:39:39.021 ROM: trying to set bootvar 'RANDOM_NUM=341962118'
Jan 02 18:39:39.192 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:39.447 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:39.715 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:39.939 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:40.195 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:40.417 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:40.642 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:40.901 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:41.123 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:41.374 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:41.597 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:41.849 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:42.044 CPU0: MTS: read access to undefined address 0x3c08002c
c=0x608fb2f0 (size=1)
Jan 02 18:39:42.289 CPU0: MTS: read access to undefined address 0x3c08002c
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
at p
c=0x608fb2f0 (size=1)
Jan 02 18:39:42.515 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:42.769 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:43.024 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:43.274 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:43.528 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:43.784 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:44.038 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:44.291 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:44.541 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:44.765 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:45.015 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:45.270 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:45.538 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:45.792 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:46.016 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:46.267 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:46.518 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:46.770 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:47.020 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:47.272 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:47.547 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:47.802 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:48.024 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:48.276 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:48.530 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:48.784 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:49.021 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:49.272 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:49.521 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:49.774 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:50.024 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:50.280 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:50.530 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:50.783 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:51.036 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:51.194 CPU0:
Jan 02 18:39:51.298 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:51.539 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:51.810 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:52.034 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:52.287 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:52.541 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:52.770 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:53.025 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:53.282 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:53.536 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:53.795 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:54.018 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:54.275 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:54.530 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:54.785 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:55.041 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:55.293 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:55.521 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:55.775 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:56.030 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:56.284 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:56.536 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:56.791 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:39:57.017 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:40:04.771 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:05.033 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:05.288 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:05.514 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:05.770 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:06.024 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:06.285 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:06.513 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:06.769 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:07.026 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:07.280 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:07.535 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:07.787 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:08.042 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:08.266 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:08.526 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:08.785 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:09.039 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:09.272 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:09.525 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:09.777 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:09.841 CPU0:
Jan 02 18:40:10.040 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:10.293 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:10.526 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:10.784 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:11.036 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:11.266 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:11.520 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:40:11.774 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:41:14.448 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:14.846 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:15.155 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:15.483 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:15.777 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:16.076 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:41:16.415 CPU0:
c=0x608fb2f0 (size=1)
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c=0x608fb2f0 (size=1)
Jan 02 18:46:14.801 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:15.148 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:15.453 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:15.787 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:16.087 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:16.426 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:16.731 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:17.073 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:17.384 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:17.704 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:18.073 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:18.415 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:18.794 CPU0:
Jan 02 18:46:18.806 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:19.103 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:19.455 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:19.757 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:20.122 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:20.489 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:20.827 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:21.137 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:46:30.347 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:30.648 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:31.041 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:31.346 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:31.710 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:32.055 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:32.437 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:32.779 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:33.132 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:33.441 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:33.772 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:34.129 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:34.427 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:34.771 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:35.071 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:35.420 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:35.720 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:36.066 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:36.369 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:36.721 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:37.064 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:37.416 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:37.784 CPU0:
Jan 02 18:46:37.802 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:38.245 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:38.654 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:39.010 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:39.453 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:39.727 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:46:40.154 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:47:49.579 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:49.882 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:50.239 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:50.548 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:50.894 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:51.206 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:51.557 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:51.859 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:52.211 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:52.526 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:52.833 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:53.190 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:53.515 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:53.868 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:53.912 CPU0:
Jan 02 18:47:54.194 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:54.547 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:54.868 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:55.226 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:55.562 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:55.908 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:56.227 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:56.580 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:56.811 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:57.036 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:57.329 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:57.615 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:57.861 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:58.177 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:47:58.480 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:49:08.859 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:09.230 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:09.554 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:09.907 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:10.217 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:10.557 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:10.854 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:11.198 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:11.520 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:11.855 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:12.170 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:12.478 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:12.842 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:13.151 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:13.277 CPU0:
Jan 02 18:49:13.534 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:13.843 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:14.188 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:14.493 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:14.835 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:15.140 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:15.521 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:15.824 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:16.172 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:16.472 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:16.773 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:17.077 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:17.340 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:17.600 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:17.829 CPU0:
c=0x608fb2f0 (size=1)
c=0x608fb2f0 (size=1)
Jan 02 18:49:50.073 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:50.389 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:50.711 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:51.084 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:51.443 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:51.865 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:52.242 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:52.607 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:52.905 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:53.260 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:53.565 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:53.895 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:54.204 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:54.515 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:54.867 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:55.268 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:55.631 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:56.019 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:56.328 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:56.671 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:56.968 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:57.306 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:57.604 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:57.940 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:58.246 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:58.556 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:58.888 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:59.191 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:59.537 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:49:59.950 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:00.267 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:00.622 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:00.925 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:01.224 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:01.537 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:01.866 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:02.191 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:02.519 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:02.860 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:03.167 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:03.468 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:03.800 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:04.105 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:04.444 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:04.744 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:05.093 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:05.386 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:05.726 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:06.045 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:06.374 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:06.670 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:07.006 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:07.298 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:07.595 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:07.929 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:08.224 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:08.564 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:08.853 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:09.199 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:09.510 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:09.853 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:10.165 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:10.507 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:10.807 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:11.166 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:11.471 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:11.808 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:12.116 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:12.459 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:12.762 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:13.102 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:13.407 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:13.719 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:14.077 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:14.381 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:14.784 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:15.113 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:15.448 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:15.746 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:16.094 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:16.388 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:16.741 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:17.052 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:17.362 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:17.722 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:18.023 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:18.365 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:18.657 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:19.016 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:19.325 CPU0:
c=0x608fb2f0 (size=1)
Jan 02 18:50:19.666 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:20.010 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:20.267 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:20.614 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:20.926 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:21.264 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:21.601 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:21.889 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:22.190 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:22.513 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:22.862 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:23.186 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:23.537 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:23.831 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:24.166 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:24.452 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:24.804 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:25.107 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:25.449 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:25.745 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:26.067 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:26.350 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:26.666 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:27.001 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:27.292 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:27.608 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:27.735 CPU0: JIT: flushing data structures (compiled pages=730)
Jan 02 18:50:27.929 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:28.231 CPU0: MTS: read access to undefined address 0x3c08002c at
c=0x608fb2f0 (size=1)
Jan 02 18:50:28.439 C3745_STOP: stopping simulation.
Jan 02 18:50:28.439 CPU0: CPU_STATE: Halting CPU (old state=0)...
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
Jan 02 18:50:28.684
Jan 02 18:50:28.684
Jan 02 18:50:28.685
=2
Jan 02 18:50:28.685
Jan 02 18:50:28.685
=2
Jan 02 18:50:28.685
Jan 02 18:50:28.685
gs=0
Jan 02 18:50:28.685
Jan 02 18:50:28.685
lags=0
Jan 02 18:50:28.685
Jan 02 18:50:28.685
flags=1
Jan 02 18:50:28.685
, len=0x200000
Jan 02 18:50:28.685
Jan 02 18:50:28.685
flags=50
Jan 02 18:50:28.706
Jan 02 18:50:28.706
gs=0
Jan 02 18:50:28.706
Jan 02 18:50:28.706
gs=0
Jan 02 18:50:28.706
Jan 02 18:50:28.706
flags=2
Jan 02 18:50:28.706
, len=0x7000
Jan 02 18:50:28.706
Jan 02 18:50:28.706
flags=0
Jan 02 18:50:28.706
Jan 02 18:50:28.706
Jan 02 18:50:28.706
Jan 02 18:50:28.706
Jan 02 18:50:28.706
Jan 02 18:50:28.706
Jan 02 18:50:28.711
Jan 02 18:51:10.372