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Univ Ques Paper Dec 2010 DLC
Univ Ques Paper Dec 2010 DLC
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PART B (5 16 = 80 Marks)
11. (a) Reduce the following using tabulation method and verify with K maps.
( ) ( ) = 14 , 12 , 10 , 8 , 6 , 4 , 3 , 2 , 1 , 0 , , , D C B A F
Or
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(b) Obtain the minimum SOP using Quine Mccluskys method and verify
using K map for the following.
m13 m12 m11 m10 m9 m8 m4 m2 m0
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A1 0 0 0 0 1 1 0
A2 0 1 1 0 0 1 0
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A3 0 1 0 1 1 0 0
Design the counter.
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13. (a) (i) List and explain the steps used for analyzing an asynchronous
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(b) (i) How do you get output specifications from a flow table in
asynchronous sequential circuit operating in fundamental mode? (6)
(ii) When do you get the critical and non-critical races? How will you
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(8)
(ii) Discuss on the concept, operation and characteristics of CMOS
technology. (8)
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(b) (i) Explain the design procedure of RTL using VHDL. (10)
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15. (a) Construct a VHDL module listing for a 16:1 MUX that is based on the