Thit k VLSI

1
PHAN HI PHONG
HAIPHONGPHAN@GMAIL.COM

Phan Hi Phong

3/10/15

Ni dung chnh
2

Gii thiu v IC v thit k VLSI

Cu trc FPGA
Ngn ng m t phn cng VHDL

Phan Hi Phong

3/10/15

Ti liu tham kho

3

Application-Specific

Integrated Circuits Michael John Sebastian

Smith, Addison-Wesley
VHDL - Programming
by Example By Douglas
L. Perry, McGraw-Hill.
Circuit Design with
VHDL Volnei
A.Pedroni, MIT Press

Phan Hi Phong

3/10/15

Gii thiu v IC v thit k VLSI

4

Phan Hi Phong

3/10/15

Lc s pht trin mch tch hp (IC)

5

1947

1958

1970 1971 1974

Transistor u tin
Gii php SoC u
tin - ng h
Hamilton Pulsar

SoC u tin
ng h
Microma

2009

Chip Xeon 7400

(1,9 t transistor)

Vi mch tch hp u
tin

Phan Hi Phong

CPU Intel 4004

3/10/15

Mch tch hp - Integrated Circuits (IC)

6

(a) A pin-grid array (PGA) package

(b) The silicon die or chip is under the package lid

Phan Hi Phong

3/10/15

ng dng ca IC
7

Processors

CPU, DSP, Controllers

Memory chips
RAM, ROM, EEPROM
Analog

Mobile communication,
audio/video processing

Programmable

PLA, FPGA

Embedded systems
Used in cars, factories
Network cards
System-on-chip (SoC)
Phan Hi Phong

3/10/15

Mch tch hp - Integrated Circuits (IC)

8

Kch thc IC:

Small Scale Integration (SSI): cha 1 10 logic gates (trc1970s)
Medium Scale Integration (MSI): logic functions, counters
Large Scale Integration (LSI): many, first microprocessors on the chip
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor (CMOS)

Fast, cheap, low power transistors

Xy dng mt chip CMOS n gin:

CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication

Phan Hi Phong

3/10/15

Mt s loi transistor bn dn
9

CMOS*
Bipolar (e.g., TTL)
Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
Ga-As - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germa
CMOS: fast, cheap, low power transistor

Phan Hi Phong

3/10/15

CMOS transistor
10

Phan Hi Phong

3/10/15

Thit k logic h CMOS

11

Phan Hi Phong

3/10/15

V d: b o CMOS
12

Phan Hi Phong

3/10/15

V d: mch NAND
13

Phan Hi Phong

3/10/15

Thit k v ch to IC
14

Phan Hi Phong

3/10/15

Cc hng thit k vi mch (IC)

15

Quick design (semi-custom design)

High-performance design (full-custom design)

Phan Hi Phong

3/10/15

Cc phng php thit k vi mch kch thc ln (VLSI)

16

Full Custom
ASIC - Application-Specific Integrated Circuit
PLD, FPGA - Programmable Logic
SoC - System-on-a-Chip

Phan Hi Phong

3/10/15

Phng php thit k Full Custom

17

Mi phn t ca mch u c thit k ring bit

Hiu sut

Chi ph thit k cao

Chi ph NRE (Non-Recurring Engineering) cao
Hiu nng cao
Chi ph cho tng vi mch thp (nu sn xut vi s lng ln)

V d:
Analog and Mixed-Signal
Microprocessor

Phan Hi Phong

3/10/15

Phng php thit k ASIC

18

Constrained design using pre-designed (and sometimes pre-

manufactured) components that are assembled and wired by CAD

tools.

Standard cell (pre-designed cells)

Gate array (pre-manufactured cells - just add wiring)
Structured ASIC (complex function customized by wiring)

Hiu nng:
Low Design Cost (CAD tools greatly reduce design effort)
High NRE Cost (lower in Gate Array / Structured ASIC)
Medium Unit Cost
Medium Performance
V d:

Control chip for cell phone

Graphics chips for desktop computers (e.g. nVidia, ATI)

Phan Hi Phong

3/10/15

Phng php thit k kiu logic ti lp trnh

19

Pre-manufactured components with programmable

interconnect wired by CAD tools

Hiu nng:

Low Design Cost (CAD tools greatly reduce design effort)

Low NRE Cost (basically 0)
Low performance
High unit cost

V d:
Network routers (e.g., Cisco)

Phan Hi Phong

3/10/15

Phng php thit k kiu SOC

20

Idea: combine several large blocks

Pre-designed custom cores, called Intellectual Property (IP) cores (e.g. ARM
processor, microcontroller)
ASIC logic for special-purpose hardware
Programmable Logic (PLD, FPGA)
Analog
Hiu nng:

Medium design cost

High NRE cost
Medium performance
Medium unit cost

V d:
Consumer electronics (e.g., iPod)
Cable set-top boxes
Chip a nng cho thit b di ng
Phan Hi Phong

3/10/15

SOC: OMAP-4
21

Phan Hi Phong

3/10/15

 tng thit k vi li IP
22

tng: ti s dng cc li thit k.

Hard IP pre-designed layout in a specific

technology

Standard Cells
Processor Cores
Memory Cores

Soft IP - synthesizable HDL

Proprietary algorithms (e.g. MPEG encoding/decoding)

Phan Hi Phong

3/10/15

Cc mc thit k VLSI
23

Phan Hi Phong

3/10/15

Lung thit k (design flow)

24

Phan Hi Phong

3/10/15

Designers Tasks Tools

25

Phan Hi Phong

3/10/15

Hng thit k
26

Top-Down Design Method

High level functions are defined first
Lower level implementation details are filled in later
Bottom-Up Design Method

Low level functions are defined and finished first

High level implementation are completed in later

Phan Hi Phong

3/10/15

Cu trc FPGA
27

Phan Hi Phong

3/10/15

Gii thiu chung

28

FPGA: Field Programmable Gate Array mng

logic ti kh trnh.
c thit k u tin bi Ross Freeman (ngi
sng lp cng ty Xilinx), vo nm 1984.
Cha cc phn t logic c kh nng ti cu hnh
to thnh cc vi mch s khc nhau.
FPGA c lp trnh bng cch:

S dng mt s mch logic

S dng ngn ng m t phn cng (Hardware Description
Language - HDL)

Phan Hi Phong

3/10/15

Gii thiu chung

29

FPGA bao gm:

Cc thnh phn logic kh trnh (cc khi logic)
Cc kt ni ti cu hnh cho php cc khi logic c ni
dy vi nhau.
Cc khi logic c th c cu hnh thc hin

cc hm t hp phc tp hay ch n thun l cc

cng logic nh AND v XOR.
Trong hu ht cc FPGA th cc khi logic cng
cha cc phn t nh, cc phn t nh ny c th
l flip-flop hay cc khi nh y hn.
Phan Hi Phong

3/10/15

Cu trc chung ca FPGA

30

Cc khi logic cu hnh c

(configurable logic blocks CLB)

Cc khi I/O cu hnh c
(configurable I/O blocks)
Cc lin kt kh trnh
(Programmable Interconnect)

Phan Hi Phong

3/10/15

Cu trc CLB n gin

31

Bng tm kim 4 u vo (Lookup table - LUT)

LUT l khi logic c th thc hin bt k hm logic no t 4
u vo, kt qu ca hm ny ty thuc vo mc ch m gi
ra ngoi khi logic trc tip hay thng qua phn t nh flipflop
Flip-flop

Phan Hi Phong

3/10/15

Mt CLB phc tp
32

Phan Hi Phong

3/10/15

Khi I/O ti cu hnh

33

c s dng :
Chuyn cc tn hiu vo trong chip.
Gi tn hiu t trong chip ra ngoi.
C 2 nhim v trn (mt cch ng thi).

Phan Hi Phong

3/10/15

Kt ni kh trnh
34

Phan Hi Phong

3/10/15

Thit k chip trn FPGA

35

Phan Hi Phong

3/10/15

Ngn ng m t phn cng

VHDL
36

Phan Hi Phong

3/10/15

Gii thiu
37

VHDL: l mt ngn ng m t phn cng.

VHDL:VHSIC Hardware Description Language

(VHSIC: Very High Speed Integrated Circuits).

c B Quc Phng M a ra u tin vo nm

1980.

Phan Hi Phong

3/10/15

Gii thiu
38

T chc IEEE chnh thc ph chun chp nhn ngn ng VHDL

nh l mt chun ca h vo nm 1987, chun IEEE 1076

Ging nh cc chun kc ca IEEE, chun IEEE 1076 c
sa i theo chu k ti thiu l 5 nm
Sa i u tin c thc hin nm 1993, v VHDL-93 hin
nay c coi l phin bn chnh thc ca ngn ng ny, hin
nay bt u xut hin VHDL 200X
Tuy nhin, hu ht cc cng c (tool) u h tr phin bn u
tin (VHDL-87)
VHDL-2X
Cc b phn ca VHDL 200X
VHDL-93
c h tr bi mt s tool
VHDL-87
Phan Hi Phong

3/10/15

Gii thiu
39

L mt ngn ng chun, c lp vi cng ngh.

ng dng trong hai phng thc thit k vi mch

chnh:

Programmable Logic Devices:

CPLD: Complex Programmable Logic Devices

FPGA: Field Programmable Gate Arrays.

ASIC: Appliation Specic Integrated Circuits.

Phan Hi Phong

3/10/15

Lung thit k
40

Phan Hi Phong

3/10/15

Mc tru tng trong thit k

41

t chi tit hn,

thit k v m
phng nhanh
hn

Behavioral

RTL
AND_OR2

Chi tit hn, ph

thuc cng ngh,
thit k v m
phng chm hn

Phan Hi Phong

DFF

Logic

Layout

CLB_
R5C5

CLB_
R5C6

3/10/15

Cc cng c EDA
42

C nhiu cng c EDA khc nhau c s dng

thit k vi mch bng VHDL.

Cc cng c h tr theo 3 hng chnh: tng hp
(synthesis), thc thi phn cng (implementation),
m phng (simulation).
Cng c:

Quartus Altera
ISE suite Xilinx
Model Sim Mentor Graphic

Phan Hi Phong

3/10/15

Cng c hc VHDL???
43

Trnh son tho:

Notepad
Notepad++
Word

Chng trnh m phng:

Xillinx ISE, Quartus,
ModelSim

Phan Hi Phong

3/10/15

Cu trc chng trnh VHDL

44

LIBRARY: cha cc khai bo v nhng th vin

c dng trong chng trnh.

ENTITY: khai bo v cc cng vo ra ca mch in
ARCHITECTURE: cha m VHDL m t hnh vi
ca mch in (chc nng ca mch).

Phan Hi Phong

3/10/15

LIBRARY
45

Tp hp cc on code thng hay c s dng.

Cho php ti s dng v chia s cc on m trong

nhiu thit k khc nhau.

Cc thnh phn ca LIBRARY

PACKAGES
FUNCTIONS
PROCEDURES
COMPONENTS

Phan Hi Phong

3/10/15

LIBRARY
46

Khai bo:
LIBRARY library_name;
USE library_name.package_name.package_parts;
Cc th vin thng xuyn s dng:

IEEE
STD
WORK

Cc gi thng c s dng:
ieee.std_logic_1164 (ieee library)
standard (std library)
work (work library).
Phan Hi Phong

3/10/15

V d
47

LIBRARY ieee;
USE ieee.std_logic_1164.all
LIBRARY std;
USE std.standard.all;
LIBRARY work;
USE work.all;

Phan Hi Phong

3/10/15

Th vin IEEE
48

std_logic_1164 : STD_LOGIC (8 levels) and STD_ULOGIC (9

levels)
std_logic_arith : kiu d liu SIGNED v UNSIGNED,cc php

ton v so snh, cc hm chuyn i

std_logic_signed: cha cc hm cho php hot ng vi kiu

STD_LOGIC_VECTOR c du.
std_logic_unsigned : cha cc hm cho php hot ng vi

kiu STD_LOGIC_VECTOR khng du.

Phan Hi Phong

3/10/15

ENTITY
49

Ni cha cc m t v cc cng vo ra ca mch

in.
C php:
ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;

...);
END entity_name;

Phan Hi Phong

3/10/15

ENTITY
50

Cc mode ca tn hiu:
IN: tn hiu vo
OUT: tn hiu ra
INOUT: tn hiu vo ra hai hng
BUFFER: tn hiu ra c nh m
Cc kiu tn hiu:

BIT
STD_LOGIC, STD_LOGIC_VECTOR
INTEGER

Tn ca ENTITY khng c trng vi cc t kho trong

VHDL
Phan Hi Phong

3/10/15

V d: NAND GATE
51

ENTITY nand_gate IS
PORT (a, b : IN BIT;
x: OUT BIT);
END nand_gate;

Phan Hi Phong

3/10/15

ARCHITECTURE
52

Phn m m t hot ng (chc nng) ca mch

in.
C php:
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;

Khng c s dng cc t kho ca VHDL lm tn

ca ARCHITECTURE
C th trng tn vi ENTITY
Phan Hi Phong

3/10/15

V d: NAND GATE
53

ARCHITECTURE nand_arch OF nand_gate IS

BEGIN
x<=a NAND b;
END nand_arch;

Phan Hi Phong

3/10/15

Kiu d liu (Data Types)

54

BIT v BIT_VECTOR: kiu logic 2 mc ( 0 v 1)

STD_LOGIC (and STD_LOGIC_VECTOR): 8 gi tr logic

ca h thng c gii thiu trong chun IEEE1164

STD_ULOGIC (and STD_ULOGIC_VECTOR): 9 gi tr

logic ca h thng c gii thiu trong chun IEEE1164

SIGNED and UNSIGNED: tng t nh STD_LOGIC v

STD_LOGIC_VECTOR nhng cho php thc hin cc

php ton s hc
Cc kiu d liu ny cho php tng hp phn cng c.
Phan Hi Phong

3/10/15

Kiu d liu (Data Types)

55

BOOLEAN: True, False.

INTEGER: 32-bit s nguyn ( t -2,147,483, 647

n +2,147,483, 647).
NATURAL: 32-bit s nguyn khng m (t 0 n
2,147,483,64 7).
REAL: kiu s thc (t -1.0E38 n 1.0E38).

Phan Hi Phong

3/10/15

Kiu d liu (Data Types)

56

Kiu vt l: m t cc thng s vt l (thi gian, in

p, dng in). Ch s dng trong m phng,

khng th tng hp phn cng (synthesis).
Kiu k t: m t cc k t trong bng m ASCII.
Khng th tng hp phn cng.

Phan Hi Phong

3/10/15

BIT v BIT_VECTOR
57

Ch gm 2 gi tr: 0 v 1

5=> 0101 ( 3 downto 0 ) => 1010 ( 0 to 3 )

Phan Hi Phong

3/10/15

BIT v BIT_VECTOR
58

V d:

Gn gi tr.

Phan Hi Phong

3/10/15

STD_LOGIC v STD_LOGIC_VECTOR
59

8 gi tr logic

Mc yu k xc nh
Mc yu thp
Mc yu cao

Phan Hi Phong

3/10/15

STD_LOGIC v STD_LOGIC_VECTOR
60

V d

Gn cho bin
1 gi tr

Phan Hi Phong

3/10/15

STD_LOGIC v STD_LOGIC_VECTOR
61

Xung t logic

Phan Hi Phong

3/10/15

User-Dened Data Types

62

Kiu d liu do ngi dng nh ngha, cho php

to ra kiu d liu cho ring mnh.

C php:
TYPE name_type IS RANGE begin_poin TO end_poin
C hai dng d liu do ngi dng t nh ngha:

integer v enumerated;

Phan Hi Phong

3/10/15

User-Dened Data Types

63

Integer

Phan Hi Phong

3/10/15

User-Dened Data Types

64

enumerated

Phan Hi Phong

3/10/15

Kiu con - Subtypes

65

L kiu d liu c trch xut t mt kiu d liu

khc vi nhng iu kin rng buc c th.

L do s dng Subtype: mt s php ton khng
cho php s dng khi 2 kiu d liu l khc nhau
nhng c th cho php khi s dng kiu con.

Phan Hi Phong

3/10/15

Kiu con - Subtypes

66

V d

Phan Hi Phong

3/10/15

Kiu con - Subtypes

67

V d:

Phan Hi Phong

3/10/15

Mt s kiu d liu khc

68

Kiu mng Array: tp hp cc i tng c cng

kiu d liu.
TYPE type_name IS ARRAY (specification) OF
data_type;
Kiu bng ghi Record: cha cc i tng khc

kiu d liu
TYPE birthday IS RECORD
day: INTEGER RANGE 1 TO 31;
month: month_name;

END RECORD;
Kiu mng cng
Phan Hi Phong

Port Array:
3/10/15

Signed v Unsigned
69

V d:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
Khai bo tng t STD_LOGIC, khng phi theo

INTEGER.
Khai bo s dng gi std_logic_arith ca th vin IEEE
UNSIGNED: gi tr khng m
SIGNED: gi tr m
Cho php thc hin cc ton t s hc, nhng khng
cho php thc hin cc ton t logic.
Phan Hi Phong

3/10/15

Signed v Unsigned
70

V d:

Phan Hi Phong

3/10/15

Signed v Unsigned
71

V d:

Phan Hi Phong

3/10/15

How???
72

Hai gi: std_logic_signed and std_logic_unsigned

cho php s dng kiu STD_LOGIC_VECTOR

tng t nh vi SIGNED v UNSIGNED

Phan Hi Phong

3/10/15

Example
73

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; -- extra
package included
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v< = a+b;- - legal (arithmetic operation OK),
unsigned
w< =a AND b; -- legal (logical operation OK)
Phan Hi Phong

3/10/15

Operator
74

VHDL cung cp sn mt s loi ton t sau:

Ton t gn
Ton t logic
Ton t s hc
Ton t tng quan
Ton t dch

Phan Hi Phong

3/10/15

Ton t gn
75

c s dng gn gi tr cho tn hiu, bin v

hng s.

<= s dng gn gi tr cho SIGNAL.

:= s dng gn gi tr cho VARIABLE, CONSTANT,
GENERIC (thng l thit lp gi tr khi u)
=> s dng gn gi tr cho cc tn hiu trong vector hoc
gi tr OTHERS.

Phan Hi Phong

3/10/15

V d
76

SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR (0 TO 7);
x<= '1';
y:= "0000";
w<= "10000000";
w<=(0 =>'1', OTHERS =>'0');

Phan Hi Phong

3/10/15

Ton t logic
77

c s dng thc hin cc php ton logic

Ch p dng i vi cc loi d liu: BIT,

STD_LOGIC, STD _ULOGIC

Cc ton t c h tr

NOT
AND
OR
NAND
NOR
XOR
XNOR

Phan Hi Phong

3/10/15

V d
78

y <= NOT a AND b;

y <= NOT (a AND b);
y <= a NAND b;

Phan Hi Phong

Thc hin t tri qua phi

3/10/15

Ton t s hc
79

S dng thc hin cc php ton s hc

Ch p dng cho cc loi d liu: INTEGER,

SIGNED, UNSIGNED, hoc REAL

+ Addition
- Subtraction
* Multiplication
/ Division
** Exponentiation
MOD Modulus
REM Remainder
ABS Absolute value ( tr tuyt i )

Phan Hi Phong

3/10/15

Ton t so snh
80

c dng thc hin php ton so snh

C th p dng cho mi kiu d liu
= Bng
/= Khc
< Nh hn
> Ln hn
<= Nh hn hoc bng
>= Ln hn hoc bng

Phan Hi Phong

3/10/15

Ton t dch
81

c s dng dch d liu

C php:

<left operand> <shift operation> <right operand>

Left operand -> BIT_VECTOR
Right operand -> INTEGER

sll : Shift left logic v tr bn phi c lp bi gi

tr 0
srl : Shift right logic v tr bn tri c lp bi gi
tr 0

Phan Hi Phong

3/10/15

M song song v m tun t

82

M lnh ca VHDL c chia lm hai loi:

M song song (concurrent)
M tun t (sequential)
M lnh c phn chia da vo cu trc ca mch

in:

mch logic kt hp (combinational logic) -> m song song

mch logic tun t (sequential logic) -> m tun t

Phan Hi Phong

3/10/15

Combinational logic
83

Gi tr u ra ca mch in ch ph thuc vo gi

tr u vo hin ti
Mch in khng c thnh phn nh
C th c thc thi bng cc phn t cng logic

Phan Hi Phong

3/10/15

Sequential Logic
84

Gi tr u ra ph thuc khng ch gi tr u vo

hin ti m cn c gi tr u vo trc .
Mch in phi bao gm cc thnh phn nh.

Phan Hi Phong

3/10/15

M song song
85

Thng thng, m lnh ca VHDL thuc dng m

song song.
Ch cc m lnh nm trong PROCESS, FUNCTION,
PROCEDURE l m tun t.
Vi m song song, mch in c tng hp nh
nhau, bt chp th t ca cu lnh trong chng
trnh.

Phan Hi Phong

3/10/15

M song song
86

Cc loi m lnh thuc dng m song song

Cc ton t
Cu lnh WHEN

WHEN/ELSE
WITH/SELECT/WHEN

Cu lnh GENERATE
Cu lnh BLOCK

Phan Hi Phong

3/10/15

Ton t
87

Phan Hi Phong

3/10/15

Ton t
88

Cc ton t c th c s dng m t bt k

mch kt hp no.
Cc mch in phc tp c th c biu din d
dng hn vi m lnh tun t cho d khng cha
phn t logic tun t

Phan Hi Phong

3/10/15

B multiplexer
89

B MUX gm 4 u vo, 1 u ra
Tn hiu ra c chn t 4 u vo thng qua 2

chn s0 v s1
M t mch bng cc ton t logic

Phan Hi Phong

3/10/15

Code of MUX
90
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS

PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;

y: OUT STD_LOGIC);
END mux;

ARCHITECTURE pure_logic OF mux IS

BEGIN
y <= (a AND NOT s1 AND NOT s0) OR

(b AND NOT s1 AND s0) OR

(c AND s1 AND NOT s0) OR

(d AND s1 AND s0);

END pure_logic;

Phan Hi Phong

3/10/15

Cu lnh WHEN
91

C hai dng lnh:

WHEN/ELSE
assignment WHEN condition ELSE
assignment WHEN condition ELSE
...;
WITH/SELECT/WHEN
WITH identifier SELECT
assignment WHEN value,
assignment WHEN value,
...;
Lu 2 t kho: OTHERS
Phan Hi Phong

v UNAFFECTED
3/10/15

V d
92

Phan Hi Phong

3/10/15

MUX with WHEN/ELSE

93

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE mux1 OF mux IS
BEGIN
y <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel="10" ELSE
d;
END mux1;
Phan Hi Phong

3/10/15

MUX with WITH/SELECT/WHEN

94

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
y: OUT STD_LOGIC);
END mux;
ARCHITECTURE mux2 OF mux IS
BEGIN
WITH sel SELECT
y <= a WHEN "00", -- notice "," instead of ";"
b WHEN "01",
c WHEN "10",
d WHEN OTHERS;
END mux2;
Phan Hi Phong

3/10/15

Cu lnh GENERATE
95

FOR /GENERATE:
label: FOR identifier IN range GENERATE
(concurrent assignments)
END GENERATE;

Phan Hi Phong

3/10/15

M tun t
96

if/else
case
loop
Phi c vit bn

trong mt process,
function, procedure

Phan Hi Phong

architecture RTL of ENTITY_1 is

. . .
begin
concurrent statements ;
...
Cc process s
process
c thc hin
begin
case ( sel_a ) is
song song, cc
when
lnh trong
...
process c thc
end case ;
hin tun t
end process ;
...
process
begin
if (sel_b = 00) then
...
else.
end if ;
end process ;
...
end architecture RTL ;
3/10/15

Process
97

Process l mt vng m tun t bn trong m VHDL.

c trng bi cc lnh tun t v danh sch nhy

sensitivity list (hoc s dng lnh WAIT)

Mt process c pht sinh khi mt tn hiu trong danh
sch nhy thay i (hoc khi iu kin ca lnh WAIT
pht sinh).
C php:
[label:] PROCESS (sensitivity list) #ds nhy
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)

END PROCESS [label];

Phan Hi Phong

3/10/15

Cc cu lnh If/Else
98

Cu lnh if/else lm cho cc giao dch c thc

hin da trn nhng iu kin nht nh. C ba

dng lnh if/else c bn sau:
process
process
begin
begin
ifif (boolean
(boolean expression)
expression) then
then
sequential
sequential statements;
statements;
end
end ifif ;;
process
process
begin
begin
ifif (boolean
(boolean expression)
expression) then
then
sequential
sequential statements
statements ;;
else
else
sequential
sequential statements
statements ;;
end
end ifif ;;

Phan Hi Phong

process
process
begin
begin
ifif (boolean
(boolean expression
expression 1)
1) then
then
sequential
sequential statements
statements ;;
elsif
elsif (boolean
(boolean expression
expression 2)
2) then
then
sequential
sequential statements
statements ;;
elsif
elsif (boolean
(boolean expression
expression 3)
3) then
then
sequential
sequential statements
statements ;;
else
else
sequential
sequential statements
statements ;;
end
end ifif ;;

3/10/15

V d IF/THEN
99

1. iu kin u tin tho mn s

c thc hin ngay
2. Cc iu kin c th gi nhau
3. iu kin u tin ca lnh
if/elsif c u tin cao nht
process
process (A,
(A, B,
B, C,
C, D,
D, Sel)
Sel)
D
begin
begin
IfIf
(Sel
(Sel == 00)
00) then
then
C
ZZ <=
<= A
A ;;
elsif
elsif (Sel
(Sel == 01)
01) then
then
ZZ <=
<= B
B ;;
B
elsif
(Sel
=
10)
then
elsif (Sel = 10) then
ZZ <=
<= C
C ;;
elsif
elsif (Sel
(Sel == 11)
11) then
then
A
ZZ <=
<= D
D ;;
end
end if;
if;
end
end process
process ;;
Sufficient
Sufficient for
for std_logic?
std_logic?
Phan Hi Phong

A
B

C
D
Sel

Z
Late
Late arriving
arriving signal?
signal?
3/10/15

B m 1 s thp phn
100

Cha 1 u vo v 4 u ra
m 1 s thp phn, tng dn

t 0-9-0.
m khi c 1 xung clock c
kch vo.
BI TP V NH
HC LI SNG TH 7 h207

Phan Hi Phong

3/10/15

Thanh ghi dch 4 bit

101

Bit u ra q s nhn gi tr ca u vo d sau 4 xung

clock
C 1 tn hiu reset khng ng b, s a cc flipflop v 0 khi pht sinh.

Phan Hi Phong

3/10/15

Lnh WAIT
102

C th c s dng tng t lnh IF

Nu s dng trong process th process khng

cn n danh sch nhy.

C th khng c tng hp phn cng
WAIT UNTIL signal_condition;
WAIT ON signal1 [, signal2, ... ];
WAIT FOR time;

Phan Hi Phong

3/10/15

Cu lnh Case
103

Cu lnh case lm cho cc giao dch c thc hin

tu thuc vo gi tr ca biu thc chn

Lnh case c hai dng c bn:
process
process ()
()
begin
begin
case
case (( selector
selector expression
expression )) is
is
when
when ...
... =>
=>
sequential
sequential statements
statements ;;
when
when ...
... =>
=>
sequential
sequential statements
statements ;;
when
when ...
... =>
=>
sequential
sequential statements
statements ;;
end
end case
case ;;
.. .. ..
end
end process
process ;;
Phan Hi Phong

process
process (...)
(...)
begin
begin
case
case (( selector
selector expression
expression )) is
is
when
when ...
... =>
=>
sequential
sequential statements
statements ;;
.. .. ..
when
when others
others =>
=>
sequential
sequential statements
statements ;;
end
end case
case ;;
.. .. ..
end
end process
process ;;
3/10/15

V d lnh Case
104
Tt c cc gi tr c th c ca biu thc chn u phi c ch r

(specified) trong cu lnh

Cc iu kin khng c chng cho (gi) nhau

Gii cc gi tr c m t phi hu hn (discrete)
Lnh Case thch hp vi cc cu trc kiu LUT

Hu ht cc cng c tng hp mch

u to ra cu trc MUX t lnh case

A
B

C
D
Sel
Phan Hi Phong

process
process (A,
(A, B,
B, C,
C, D,
D, Sel
Sel ))
begin
begin
case
case Sel
Sel is
is
when
when 00
00 =>
=> ZZ <=
<= A
A ;;
when
when 01
01 =>
=> ZZ <=
<= B
B ;;
when
when 10
10 =>
=> ZZ <=
<= C
C ;;
when
when 11
11 =>
=> ZZ <=
<= D
D ;;
end
end case
case ;;
.. .. ..
end
end process
process ;;

Is this sufficient for std_logic?

3/10/15

Lnh LOOP
105

c s dng khi mun lp li mt s ln hu hn cc

on m trong chng trnh.

FOR / LOOP: vng lp c thc hin trong mt s ln.
[label:] FOR identifier IN range(khoang can lap) LOOP

(sequential statements)
END LOOP [label];
WHIL E / LOOP: vng lp c thc hin n khi iu kin
khng cn tha mn.
[label:] WHILE condition LOOP
(sequential statements)
END LOOP [label];
Phan Hi Phong

3/10/15

Tn hiu v bin
106

VHDL cung cp 2 kiu bin lu tm d liu

trong qu trnh tn ton:

SIGNAL (tn hiu)

VARIABLE (bin).

VHDL cng cung cp 2 kiu hng s lu cc d

liu c nh:

CONSTANT
GENERIC

Phan Hi Phong

3/10/15

Global v Local
107

Global:

CONSTANT v SIGNAL c truy cp t mi v tr trong

chng trnh.
c s dng trong c m tun t v m song song

Local:

VARIABLE ch c truy cp trong cc phn m tun t

Gi tr ca VARIABLE khng truyn c ra ngoi cc phn
m ny.

Phan Hi Phong

3/10/15

CONSTANT
108

CONSTANT name : type := value;

CONSTANT set_bit : BIT := '1';
CONSTANT datamemory : memory := (('0','0','0','0'),

('0','0','0','1'),
('0','0','1','1'));
CONSTANT c th c khai bo trong PACKAGE, ENTITY,

hoc ARCHITECTURE.

Nu khai bo trong PACKAGE th c th truy cp c bt k ENTITY no.

Nu khai bo trong ENTITY th c th truy cp c trong bt k
ARCHITECTURE no.
Nu khai bo trong ARCHITECTURE th c truy cp ch trong kin trc .

Phan Hi Phong

3/10/15

SIGNAL
109

SIGNAL c dng chuyn d liu vo v ra

khi mch in.

SIGNAL cng c dng nh nhng lin kt bn
trong mch (dy dn).
Cc PORT ca mch in l cc SIGNAL
SIGNAL name : type [range] [:= initial_value];

Trong PROCESS, gi tr ca SIGNAL khng c cp

nht ngay lp tc (gi tr ca SIGNAL cha c sn

sng cho dng m tip theo).
Phan Hi Phong

3/10/15

VARIABLE
110

Ch c truy cp cc b (Local)
Ch c dng trong m tun t (PROCESS,

FUNCTION, PROCEDURE)
Khng chuyn c gi tr ra khi on m (ch
chuyn c thng qua SIGNAL).
Gi tr ca VARIABLE c cp nht ngay lp tc
ti thi im thay i (sn sng cho dng m tip
theo)
C php: VARIABLE name : type [range]
[:= init_value];
Phan Hi Phong

3/10/15

111

q = d;
qbar = not q;

Phan Hi Phong

3/10/15