Chapter 7

Soft Processor Core for Accelerated

Embedded Design

The synergy of FPGA and soft processor cores has the budding potential to allow
the integration SoC into a single FPGA chip. Embedded engineers often fight with
the confront of improving performance. Discrete processors a.k.a. hard processors
pose the following most striking drawbacks when it comes to embedding them for
a particular application:
• Fixed selection of peripherals, most of them remain unutilized for the given
application.
• No possible customization in clock frequency, that drags the entire system slow
or too fast and ends in power inefficiency.
• Less life time of the processor family
• Incompatibility interms of package size when a particular processor is being
upgraded, posing difficulties in PCB designing.
• Speed and interface incompatibility when multiple heterogeneous processors are
required to work as coprocessors.
Programmable logic has reached such a state of advancement in terms of speed
and density that it became a truly attractive alternative to the above mentioned RISC
and CISC processors. It can form a ‘matrix’ within which processing, peripherals,
data path, and algorithms can be placed to create powerful, flexible, and upgrade-
able systems. It is now available in forms and sizes that range from the traditional
use as glue logic up to structured ASIC replacements and even further [103].
As a result of all the above mentioned advancements, ‘Soft Processor Cores’
have emerged as an ultimate remedy for addressing the pitfalls of hard RISC and
CISC processors. ‘A soft-core processor is a hardware description language (HDL)
model of a specific processor (CPU) that can be customized for a given application
and synthesized for an ASIC or FPGA target.’ The main advantages of the soft proc-
essor cores are as follows:
• Greater possibility of Design Reuse.
• Cost Effectiveness.
• Customization and Flexibility.
• Scalability.
• Possibility of Hardware-Software portioning at an early stage.

R.K. Kamat et al., Unleash the System on Chip using FPGAs and Handel C, 141
DOI 10.1007/978-1-4020-9362-3_7, © Springer Science+Business Media B.V. 2009