Rectangular pulses generated with AT89S52.

(Range 3rd Exercises)

Assignment:
1. Create a rectangular signal generator alternating with 1:1 (1s) duty with AT89S52 and
displays the result at the oscilloscope and at the LEDs without interruption and with
interruption of counters / timers.
Theory:
Circuits work with bus
Way can be called circuits that operate with multiple inputs and outputs, and each is subject to
the same operation. It is the drivers and multiple flip-flops D. This is actually a eight D flipflops whose clock respectively control inputs are combined into a single outlet and controlled
by edge or level. For a large number of inputs and outputs (8 inputs + 8 outputs + control
signal) these circuits usually contain only one control input. It is designed to control the
output of delimiter as is the case with circuits 74LS573, 74LS574, 74LS373 and 74LS374 or
reset (74LS273 circuit). Function is easily understandable from schematic (see Figure 1).

Fig. 1. Inputs and outputs of 74LS244, 74LS274, 74LS373 and 74LS374 circuits.

74LS244 - 4-bit unidirectional bus driver

74LS244 is a 4bit circuit with a pair of one-way bus drivers. Both
drivers are mutually independent. Inputs A0 to A3 have performanceenhanced exciters and they have adjusted signals connected to the outputs Y0 to Y3. While
tri-state outputs are controlled and activated G entry in the log. 0 (for G = 0 outputs are
activated, otherwise in a state of high impedance).
74LS245 - 8-bit bidirectional bus driver
74LS245 is an 8-bit circuit with bidirectional bus driver. Input G (active in the log. 0) is used
to control three-status driver. DIR input determines the direction of transmission (DIR = 1 for
moving data in the direction A to B, DIR = 0 in the direction B to A). Pins A0 to A7 and B0 to
B7, working either as inputs or outputs (that is determined by the above-mentioned signal
DIR).
74LS373 - 8-bit D flip-flop driven by three-status level of output
These circuits include 8 inputs (D0 to D7) and 8 outputs (Q0 to Q7) D flip-flops. Flip-flops
are controlled by levels. If is on input G log. 1, the latch is opened. For G = 0 the latch is
closed, the circuit "remembers" the previous state. Access OC is active in the log. 0 and is
used to control the output delimiter. When the OC = 0 are outputs Q0 to Q7 activated.

Otherwise, you are in a state of high impedance but it is still controlled by sensor of input G.
Thus only can be output in the high impedance state while we write to circuit.
74LS374 - 8-bit D flip-flop driven by leading edge of three-status output
These circuits include 8 inputs (D0 to D7) and 8 outputs (Q0 to Q7) D flip-flops. Flip-flops
are controlled by rising edge of signal CLK. Otherwise similar rules apply as for circuit
74LS373.
Interrupt
Interruption of the program is a reaction to external events. Running of program is locally
interrupted and begins run the programmed routine. After is programmed routine at the end
the program continues its work in the place where it was interrupted. AT89S52
microcontroller uses a total of 8 interrupt sources. Each interrupt source have assigned a fixed
address (see Table 1), to which the processor is transferred in the interruption.
Register
IP
PX0
PT0
PX1
PT1

Register
IE
EX0
ET0
EX1
ET1

PS

ES

0023h

PT2

ET2

002Bh

address

Source interruption

0003h
000Bh
0013h
001Bh

external interrupt 0 (input INT0)

counter / timer 0
external interrupt 1 (input INT1)
counter / timer 1
serial channel (receive / broadcast
character)
counter / timer 2 or external interrupt
T2EX

Tab. 1 Registry and address of the interrupt sources

Interrupts enable - the IE
After a reset of microcontroller AT89S52 is the income of any interruption prohibited. We
must the interruption enabled first. Bit EA = 0 disables all interrupts. To allow must be set EA
= 1 and set the corresponding bit desired interruption. To set the receive interrupt from the
input must be allowed INTO interrupt EA = 1 and set EX0 = 1. Individual bits of IE register
are bit-addressable, so we can enable and disable each interrupt independently.

Register IE
Counter / timers
Counter is a circuit that counts pulses of the external signal, such as rising or falling edge of
the external signal from the inductive or photoelectric sensors. The timer comprises fixed
frequency which is derived from the microcontroller clock signal. The AT89S52

microcontroller has counter / timer with 16bit length. Both counters and timers work as
ascending, i.e. contents of memory location to manage, always increments.
Their content is accessible via memory-mapped registers TH0, TL0 and TH1, TL1 which
determine the higher and lower syllable (8 bits) of the counters. The clock synchronization
signal to the counters can be derived from the oscillator processor or from an external source
at pins T0 and T1. If internal oscillator is a source of signal, then the counter is in the timer
function.
In the function counter of external events, the content of the counter (register) is increased by
one when the signal Tn changed from 1 to 0. Inputs T0 and T1 are being tested at the state of
each machine cycle. One microprocessor machine cycle consists of six states, time (clock
cycles - states) designated S1 to S6, each state is divided into two phases P1 and P2. Machine
cycle is thus made up a total of 12 stages, which indicates S1P1, S1P2, S2P1, S2P2, and
S6P2. Each stage has a length of one period stroking signal.
Duration of state:
T

2
f OSC

[ MHz ]

Duration of the machine cycle:

TM 6 T

12
[ MHz ]
f OSC

Machine cycle
Where is in one cycle log. 1 (high voltage) and in the next log. 0 (low voltage), the contents of
the counter is incremented. The new counter value is set during the next cycle. Because input
change detection Tn takes 2 machine cycles (24 oscillator periods), the maximum counting
frequency of the external signal 1 / 24 oscillator frequency microcomputers. Logic level of
signal must always remain unchanged at least full one machine cycle. Configuration of
counters/timers 0 and 1 we can set at the register TMOD. Start, stop or reset bits of custom
counters we can set in the Trn at the TCON register.
TCON Register - management Counter / timers (Timer / Counter Control)
TCON register is bit addressable, bit register used to program startup or indication timer
overflow.

Registr TCON
TF0, TF1 - indicate overflow of counter/timer 1, the overflow is automatically set after the
entry into interruption service is automatically reset
TR0, TR1 - allow counting pulse for counter/timer 1 and 0
IE0, IE1 - Adoption of the external interrupt. Responsible bit is set for falling edge or level
log.0 input external interrupt INTn depending on the state of the configuration bit ITN. After
the transition of the processor service to the interrupt subroutine, bit is automatically reset.
IT0, IT1 - Configuration to activate an external interrupt. If ITN = 1, the application is
activated on the external interrupt (falling edge) signal input INTn. If ITN = 0, the application
is activated levels log.0 input INTn.
Register TMOD - mode selection counter / timers
TMOD - Timer mode register / counter (Timer / Counter mode control) is not bit-addressable,
allowing the two modes to choose counters / timers. It is divided into two halves by 4 bits.
The lower 4 bits control the counter / timer 0 and the upper 4 bits control the counter / timer 1.

Registr TMOD
GATE (G) manages the control gate counters
GATE = 1 counter / timer is controlled by a programmed bit TRN and input INTn
GATE = 0 counter / timer is controlled by a programmed bit TRN
C / T (Counter / Timer) choose whether counter / timer will work as a counter or timer
C / T = 0 works as a timer clock signal is created from the internal microprocessor clock sync
signal derived as 1 / 12 clock signal
C / T = 1 works as a counter, clock input is Tn. The maximum frequency is 1 / 24 clock signal
M0, M1 (Mode) The combination of these bits are chosen one of four modes counters /
timers.
Mode 0 - the two counter / timers are 13bits THN has 8 bits and 5 bits TLN. Both counted up,
after the overflow is set TCON register in the TFN
Mode 1 - the two counter / timers are 16-bit and THN, TLN has 8 bits. Both counted up, after
the overflow is set TCON register in the TFN

Mode 2 - the two counter / timers are 8-bit function with RELOAD, this means that the
overflow is returned to its original value.
Mode 3 - In this mode the counter / timer 0 is divided into two separate 8bit counter TL0 and
Th0. Counter TL0 is controlled by bit Counter / Timer 0 uses the standard signal C / T, GATE,
TR0, INT0, and TF0. Th0 counter is controlled by bit counter / timer 1 is dominated by only
control bit TR1. Overflow sets TF1 flag. Works to counter / timer 0 in mode 3, then the
counter / timer 1 can only generate a baud rate for serial channel or may be used when we use
the break. Because TR1 bit is used for managing counter/timer 0 is stopping or running
counter/timer 1 controlled set-up mode to mode 3 or cancellation 3rd
Schematic diagram of connection of the eight LEDs

Schematic diagram of the eight LEDs includes an integrated circuit IO1 74HCT245
commonly known as a power driver (power bus). Inputs are A1 to A8, B1 to B8 outputs are
involved LED. Because non-inverting driver 74HCT245 and LED diodes are connected to the
anode supply voltage, LED lights up when the input for one of A1 to A8 introduced log. 0.
When connecting the product to the developmental kit to port P3, off LED connected to bits
P1.5, P1.6 and P1.7 these bits are used for the serial download.