library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compteur is
port ( Hl,raz : in std_logic;
s : out std_logic_vector(2 downto 0));end compteur;
architecture arch of compteur is
signal etat : std_logic_vector(2 downto 0);
begin
process
begin
if raz='0' then
etat <= "000";
elsif (Hl='1' and Hl'event) then etat <= etat+1;
end if;
end process ;
s <= etat;