11.

Input-Output Organization

 1
Isolated I/O
1) MM access address line I/O address line
2) I/O instruction
Memory-Mapped I/O
1) MM access address line I/O address line
2) I/O instruction
Read Input Write Output

Asynchronous data transfer

CPU

MM

Write

Destination
Data
CPU MM Write

Asynchronous data transfer

MM

CPU
Read

Destination
Data
CPU MM Read

Asynchronous
data transfer
CPU

Write

MM

Asynchronous
data transfer
MM

CPU
Read

Asynchronous
data transfer

Asynchronous
data transfer

Clock

 1
Whenever Fi = 1 and Fi+1 = 0
R(I+1) accepts R(I) by a clock.
Fi+1 1, Fi 0
Control flag moves right

0
0
0
1

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

1
0

5 4 3 2 1

1
0
1

0
1

0
0

0
1

0
0

0
1

0
0

0
1

0
0
1
0

0
0
0
1

0
0
0
0

0
0
0
0

0
0
0
0

1
0

5 4 3 2 1

0
1
0

1
0

1
0

0
1

0
0

0
1

0
0

0
1

0
0
1
0

0
0
0
1

0
0
0
1

0
0
0
0

0
0
0
0

1
0

5 4 3 2 1

1
0
1

0
1

0
1

1
0

1
0

0
1

0
0

0
1

0
0
1
1

0
0
1
0

0
0
0
1

0
0
0
1

0
0
0
0

1
1

5 4 3 2 1

0
1
0

1
0

1
0

0
1

0
1

1
0

1
0

0
1

0
0
1
1

0
0
1
0

0
0
1
0

0
0
0
1

0
0
0
1

1
0

5 4 3 2 1

1
0
1

0
1

0
1

1
0

1
0

0
1

0
0

1
0

0
1
0
0

0
0
1
1

0
0
1
0

0
0
1
0

0
0
0
1

1
0

5 4 3 2 1

0
1
0

1
0

1
0

0
1

0
0

1
0

0
0

1
0

0
1
0
0

0
0
1
1

0
0
1
1

0
0
1
0

0
0
0
1

1
0

6 5 4 3 2 1

1
0
1

0
1

0
0

1
0

0
0

1
0

0
0

1
0

0
1
0
1

0
1
0
0

0
0
1
1

0
0
1
0

0
0
0
1

1
0

7 6 5 4 3 2 1

0
0
0

1
0

0
0

1
0

0
0

1
0

0
0

1
0

0
1
0
1

0
1
0
0

0
0
1
1

0
0
1
0

0
0
0
1

1
0

7 6 5 4 3 2 1

0
0
0

1
0

0
0

1
0

0
0

1
0

0
1

1
0

0
1
0
1

0
1
0
0

0
0
1
1

0
0
1
0

0
0
0
1

1
1

8 7 6 5 4 3 2 1

0
0
0

1
0

0
0

1
0

0
1

1
0

1
0

0
1

0
1
0
1

0
1
0
0

0
0
1
1

0
0
1
0

0
0
1
0

1
0

9 7 6 5 4 3 2 1

0
0
0

1
0

0
0

1
0

0
0

0
1

0
0

1
0

0
0
1
1

0
0
1
0

0
0
1
0

0
0
0
1

0
0
0
1

1
0

5 4 3 2 1

1
0
1

0
1

0
1

1
0

1
0

0
1

0
1

1
0

0
1
0
0

0
0
1
1

0
0
1
0

0
0
1
0

0
0
0
1

1
1

5 4 3 2 1

0
1
0

1
0

1
0

0
1

0
1

1
0

1
0

0
1

1 0
0

0 0
0

Wire-AND

0 0
1
0
Wire-AND

PI PO
0 0 device Interrupt
0 1
10 device Interrupt ,
Interrupt
1 1

 1
1

0
0
1

0
0
1

1) device

 1
1

1
10
0

10
01
0 1

2) device
( )

 1
0

0
1
0

1
0
0

3) device

0
1)

0
1
1
1

1
0

6)

1
2)
5)
3)
4)

Interrupt Status

 1
I/O
1) Program controlled I/O
: AC I/O device
2) Interrupt initiated I/O
: AC I/O device
3) DMA(Direct Memory Access) : Memory I/O device
contiguous memory access
4) I/O processor
: Memory I/O device
noncontiguous memory access

word

MM

1
word 1

2
word 2

MM

MM
CPU

I/O word

1) Initialize address and count through the Data Bus

and Start the DMA

5)

word

RAM

6) DMA controller puts current value of address

on address bus , initiates RD or WR signal an

sends a DMA acknowledge to the peripheral de

2) DMA controller
starts transfer

4)
8) When the DMA completes,
DMA interrupt to CPU

6)

3)

If BG = 0
CPU sends address to
DMA
If BG = 1
DMA sends address to
7) Puts a word in the Data bus
RAM
or Receives a word
from the data bus
When device is ready, goto

 1
MM
1
word 1

2
word 2

 1
Start I/O, test I/O, halt I/O

.Protection mechanism
.The address
of last command word
.The conditions
.The residual count
.Write, read, sense
.
.Data chaining
Command chaining

MM
1
word 1

2
word 2

 1
Channel Command Word

To poll a secondary station to reques

by the primary station
To indicate the final transmitted fram
by the secondary station