Bai 005 VXL Pic Timer Libre

BI 5
GI I THIU
KH O ST TIMER/COUNTER
KH O ST TIMER/COUNTER T0
KH O ST TIMER/COUNTER T1
KH O ST TIMER T2
TP LNH C CHO CC TIMER

L nh SETUP_TIMER_X()
L nh SET_TIMER_X()
L nh SETUP_COUNTERS()
L nh SETUP_WDT()
L nh RESTART_WDT()
L nh GET_TIMER_X()
CC CH NG TRNH
NG D NG TIMER /COUNTER
NG D NG M XUNG NGO I HI N TH TRN LED 7 O N TR C TI P

NG D NG M XUNG NGO I HI N TH TRN LED 7 O N QUT
NG D NG M XUNG N I - NH TH I
CC TON T
FILE DEVICE
ai hoc s pham ky thuat tp HCM
I.
Khoa ien ien t
Nguyen nh Phu
GI I THIU
Vi i u khi n PIC h 16F877A c 3 timer T0, T1 v T2. T0 l timer/counter 8 bit, T1 l timer/counter

16 bit, c 2 u c b chia tr c. T2 ch l timer 8 bit c b chia tr c v chia sau ph c v cho cc ng d ng
c bi t.
Phn ti p s kh o st chi ti t tng timer/counter.
II. KH O ST CC TIMER/COUNTER
1.
KH O ST TIMER0
B timer0/counter0 c nh ng c i m sau:
o
L timer/counter 8 bit.
o
C th c v ghi gi tr m c a timer/counter.
o
C b chia tr c 8 bit cho php lp trnh bng phn m m.
o
Cho php l a chn ngu n xung clock bn trong hoc bn ngoi.
o
Pht sinh ngt khi b trn t FFH n 00H.
o
Cho php l a chn tc ng c nh ln hoc c nh xu ng.
S kh i c a timer0 v b chia tr c v i WDT nh hnh 5-1:
Hnh 5-1: S ki a timr0.

s d ng timer0 th ph i kh o st ch c nng c a thanh ghi i u khi n timer l OPTION_REG.
Cu hnh thanh ghi v ch c nng cc bit nh sau:
44
Bai 5: Timer/counter cua PIC va lap trnh C.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2-0
Khoa ien ien t
Nguyen nh Phu
RBPU : bit i u khi n i n tr treo c a portb.

INTEDG
T0CS: bit l a chn ngu n xung cho TMR0 - TMR0 Clock Source Select bit.
1= s m xung ngo i a n chn T0CKI.
0= s m xung clock n i bn trong.
T0SE: bit l a chn c nh tch c c T0SE - TMR0 Source Edge Select bit.
1= tch c c c nh ln chn T0CKI.
0= tch c c c nh xu ng chn T0CKI.
PSA: bit gn b chia tr c - prescaler assigment.
1= gn b chia cho WDT.
0= gn b chia Timer0.
PS2:PS0: cc bit l a chn t l b chia tr c - prescaler rate select bits:
Bit l a chn
000
001
010
011
100
101
110
111
T l TMR0
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
T l WDT
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
N u bit T0CS (OPTION_REG<5>) bng 1 th chn ch m xung ngoi Counter. Trong ch

m xung ngo i th b m s tng gi tr m i khi c xung tc ng c nh ln hoc c nh xu ng chn
RA4/T0CKI. C nh tc ng c a xung c chn l a b i bit T0SE (OPTION_REG<4>): T0SE = 0 th chn
c nh ln, ng c l i th chn c nh xu ng.
B chia tr
a.
c khng th c/ghi v c m i quan h v i Timer0 v Watchdog Timer.
Ng t c a Timer0:
Khi gi tr m trong thanh ghi TMR0 trn t FFh v 00h th pht sinh ngt, c bo ngt TMR0IF
(INTCON<2>) i tr ng thi t 0 ln 1. Ngt c th ngn bng cch xa bit cho php ngt TMR0IE
(INTCON<5>).
Trong ch ng trnh con ph c v ngt Timer0 ph i xa c bo ngt TMR0IF. Ngt c a TMR0 khng
th kch CPU thot kh i ch ng v b nh th i s ngng khi CPU ch ng .
b.
Timer0 v i ngun xung m t bn ngoi:
Khi khng s d ng b chia tr c th ng vo xung clock bn ngoi gi ng nh ng ra b chia tr c.

Vi c ng b ha c a T0CKI v i cc xung clock bn trong c th c hi n bng cch ly mu ng ra b chia
45
Khoa ien ien t
Nguyen nh Phu
nh ng chu k Q2 v Q4 c a xung clock bn trong. Do , n rt cn thi t cho T0CKI

t nht 2 TOSC v tr ng thi m c thp t nht 2 TOSC.
B chia tr
c.
tr ng thi m c cao
c:
B chia tr c c th gn cho Timer0 hoc gn cho Watchdog Timer. B chia tr c th khng th c

hoc ghi. Cc bit PSA v PS2:PS0 (OPTION_REG<3:0>) quy t nh i t ng gn v t l chia.
Khi c gn cho Timer0 th tt c cc l nh ghi cho thanh ghi TMR0 (v d CLRF 1, MOVWF 1,
BSF 1, ) s xo b chia tr c.
Khi
c gn cho WDT th l nh CLRWDT s xo b chia tr
c cng v i Watchdog Timer.
Hnh 5-2: B ia tr n o timr.
Hnh 5-3: B ia tr n o WDT.

2.
NH TH I TIMER1:
L b nh th i/ m 16 bit g m 2 thanh ghi 8 bit (TMR1H v TMR1L) c th c v ghi. Hai thanh

ghi ny tng t 0000h n FFFFh v quay tr l i 0000h.
Khi b trn th Timer1 s pht sinh ngt, c bo ngt TMR1IF (PIR1<0>) ln m c 1. Timer1 c bit
cho php/cm l TMRIE (PIE1<1>).
46
Khoa ien ien t
Nguyen nh Phu
Cu trc c a Timer1:
Hnh 5-4: Cu tr timr T1.

Kh o st thanh ghi i u khi n Timer1:
Bit 7-6
Bit 5-4
Bit 3
Bit 2
Ch a s d ng n u c s c gi tr 0.
T1CKPS1:T1CKPS0: cc bit l a chn b chia - Timer1 input Clock Prescale Select bits
11=1:8 gi tr chia.
10=1:4 gi tr chia.
01=1:2 gi tr chia.
00=1:1 gi tr chia.
T1OSCEN: bit K cho php b dao ng Timer1 - Timer1 Oscillator Enable Control bit
1= b dao ng c php.
0= Tt b dao ng.
T1SYNC: bit K ng b ng vo xung clock bn ngoi c a timer1
Khi TMR1CS = 1
1= khng th ng b ng vo clock t bn ngoi.
47
Khoa ien ien t
Bit 1
Bit 0
a.
Nguyen nh Phu
0= ng b ng vo clock t bn ngoi.
Khi TMR1CS = 0
Bit ny b b qua. Timer1 dng xung clock bn trong khi TMR1CS = 0.
TMR1CS: bit l a chn ngu n xung clock c a timer1
1= Chn ngu n xung clock t bn ngoi chn RC0/T1OSO/T1CKI (c nh ln).
0= Chn xung n i bn trong (FOSC/4).
TMR1ON: bit i u khi n Timer14
1= Cho php Timer1 m.
0= Timer1 ngng m.
Timer1
ch nh th i:
N u bit TMR1CS bng 0 th T1 ho t ng nh th i m xung n i c tn s bng FOSC/4. Bit i u

khi n ng b T1SYNC khng b nh h ng do xung clock bn trong lun ng b .
Hnh 5-5. T1 o t n n t i.
b.
Timer1
ch m xung ngo i:
N u bit TMR1CS bng 1 th T1 ho t ng m xung ngo i. Xung ngo i c 2 ngu n xung ph thu c
vo bit T1OSCEN:
N u bit T1OSCEN bng 1 th T1 m xung ngo i t m ch dao ng c a T1 - xem hnh 5-6.
N u bit T1OSCEN bng 0 th T1 m xung ngo i a n ng vo T1CKI - xem hnh 5-7.
48
Khoa ien ien t
Nguyen nh Phu
Hnh 5-6. T1 o t n m xun no i t m ao n T1.
Hnh 5-7. T1 o t n m xun no i a n n vo T1CKI.
Timer1 tng gi tr khi c xung c nh ln. Counter ch tng gi tr m sau khi nhn 1 xung c nh xu ng
c minh ho hnh 5-8.
Hnh 5-8. Gin t i ian xun m a Countr1.

Hnh trn th ng vo ang
m c 1, counter s m khi c xung c nh ln.
Hnh d i th ng vo ang m c thp, xung c nh ln th nht th m ch vn ch a m, xung xu ng

m c thp v khi c c nh ln th 2 th counter bt u m.
c.
Ho t ng c a Timer1
ch Counter ng b :
Khi bit TMR1CS bng 1 th T1 ho t ng
ch Counter:
N u bit T1OSCEN bng 1 th m xung t m ch dao ng c a T1.
N u bit T1OSCEN bng 1 th m xung c nh ln a n ng vo RC0/T1OSO/T1CKI.
N u bit T1SYNC bng 0 th ng vo xung ngo i c ng b v i xung bn trong.

n u CPU ch ng th Timer1 s khng m v m ch ng b ngng ho t ng.
d.
Ho t ng c a Timer1
ch ng b ,
ch Counter b t ng b :
N u bit T1SYNC bng 1 th xung ng vo t bn ngoi khng c ng b . B m ti p t c tng bt

ng b v i xung bn trong. B m vn m khi CPU trong ch ng v khi trn s pht sinh ngt v
nh th c CPU. Ngt T1 c th ngn c.
e.
c v ghi Timer1 trong ch m khng ng b :
Timer T1 cho php c gi tr cc thanh ghi TMR1H hoc TMR1L khi timer ang m xung bt ng
b bn ngoi.
Khi ghi th nn ngng timer l i r i m i ghi gi tr mong mu n vo cc thanh ghi. N u ghi m timer
ang m vn c nh ng c th t o ra m t gi tr m khng d on c hay khng chnh xc.
f.
B dao ng c a Timer1:
49
Khoa ien ien t
Nguyen nh Phu
M ch dao ng c tch h p bn trong v t th ch anh n i gi a 2 chn T1OSI v T1OSO t o dao

ng - xem hnh 5-9. B dao ng c php ho t ng khi bit T1OSCEN bng 1.
Hnh 5-9. K t ni t an t o ao n.
B dao ng l dao ng cng sut thp, t c 200 kHz. B dao ng vn ti p t c ch y khi CPU
ch ng . B dao ng ch dng v i t th ch anh 32 kHz. B ng sau trnh by cch l a chn t cho b dao
ng Timer1.
Reset Timer1 s d ng ng ra CCP Trigger:
g.
N u kh i CCP1 v CCP2 c nh cu hnh

(CCP1M3:CCP1M0 = 1011), tn hi u ny s reset Timer1.
ch
so snh
t o ra xung kch
Ch : xung kch t kh i CCP1 v CCP2 s khng lm bit c ngt TMR1IF (PIR1<0>) bng 1.
Timer1 ph i nh cu hnh ch nh th i hoc b m ng b t o ti n ch cho cu trc ny.
N u Timer1 ang ho t ng ch m bt ng b th ho t ng Reset khng th th c hi n c.
Reset cp thanh ghi TMR1H, TMR1L c a Timer1:
h.
Ho t ng reset lc cp ngu n POR (Power On Reset) hoc bt k reset no khc khng nh h ng

n hai thanh ghi TMR1H v TMR1L, ngo i tr khi x y ra xung kch c a CCP1 v CCP2 th xa hai
thanh ghi v 00H.
Thanh ghi T1CON
c reset v 00h
Reset lc cp ngu n POR hoc khi Brown-out Reset s xa thanh ghi T1CON v timer T1
ngng (OFF) v h s chia tr c l 1:1. Cc reset khc th thanh ghi khng b nh h ng.
tr ng thi
Cc thanh ghi c a Timer1 nh b ng sau:
3.
50
NH TH I TIMER2:
Khoa ien ien t
Nguyen nh Phu
Timer2 l timer 8 bit c b chia tr c (prescaler) v c b chia sau (postscaler).

Timer2 c s d ng i u ch xung khi kh i CCP ho t ng
ch PWM (pulse width
modulation). Thanh ghi TMR2 c th c/ghi v xo khi b reset.
Xung n i (FOSC/4) qua b chia tr c c h s chia: 1:1, 1:4 hoc 1:16 c l a chn bng cc
bit i u khi n T2CKPS1:T2CKPS0 (T2CON<1:0>).
PR2 l thanh ghi chu k 8 bit dng so snh. Timer2 tng gi tr t 00h cho n khi bng gi tr l u
trong thanh ghi PR2 th reset v 00h r i lp l i.
PR2 l thanh ghi c th c/ghi, khi h th ng b reset th thanh ghi PR
c kh i t o gi tr FFH.
Ng ra c a TMR2 i qua b chia sau (postscaler) 4 bit tr c khi pht sinh yu cu ngt lm c
TMR2IF (PIR1<1>) ln 1. Khi bit TMR2ON bng 0 th tt Timer2 gi m cng sut tiu th .
Hnh 5-10. S ki a Timr2.

Thanh ghi i u khi n timer2:
Bit 7
Bit 6-3
Bit 2
Bit 1-0
Ch a s d ng n u c s c gi tr 0.
TOUTPS3:TOUTPS0: cc bit l a chn ng ra b chia sau (Postscaler) c a Timer2
0000=1:1
0001=1:2
0010=1:3
.
.
1111=1:16
TMR2ON: Bit i u khi n cho php/cm Timer2
1= cho php timer2 m.
0= Timer2 ngng m.
T2CKPS1:T2CKPS0: bit l a chn h s chia tr c cho ngu n xung clock c a timer2
00= h s chia l 1.
01= h s chia l 4.
51
Khoa ien ien t
Nguyen nh Phu
1x= h s chia l 16.

B chia tr
a.
B m chia tr
TMR2 khng b
c v chia sau c a Timer2:

c v b chia sau s b xa khi x y ra m t trong cc s ki n sau:
Th c hi n ghi d li u vo thanh ghi TMR2.
Th c hi n ghi d li u vo thanh ghi T2CON.
Bt k Reset no tc ng.
xa khi ghi d li u vo thanh ghi T2CON.
Ng ra c a TMR2:
b.
Ng ra c a TMR2
III.
c n i t i kh i SSP kh i ny c th ty chn t o ra xung nh p.
TP LNH C CHO TIMER /COUNTER

Cc l nh c a ngn ng lp trnh C lin quan n TIMER/COUNTER bao g m:
L nh
SETUP_TIMER_X()
L nh
SET_TIMER_X()
L nh
SETUP_COUNTERS()
L nh
SETUP_WDT()
L nh
RESTART_WDT()
L nh
GET_TIMER_X()
LNH SETUP_TIMER_0(MODE) - LNH NH C U HNH CHO TIMER_0
1.
C php:
setup_timer_0(mode)
Thng s :
mode c th l 1 hoc 2 hng s nh ngha trong file device.h. Cc thng s g m

RTCC_INTERNAL, RTCC_EXT_L_TO_H hoc RTCC_EXT_H_TO_L
RTCC_DIV_2, RTCC_DIV_4, RTCC_DIV_8,
RTCC_DIV_64, RTCC_DIV_128, RTCC_DIV_256.
RTCC_DIV_16,
RTCC_DIV_32,
Cc hng s t nhi u nhm khc nhau th c th or v i nhau.

Ch c nng:
nh cu hnh cho TIMER0.
C hi u l c: cho tt c cc vi i u khi n PIC.

V d :
SETUP_TIMER_0 (RTCC_DIV_2|RTCC_EXT_L_TO_H);
SETUP_TIMER_0(RTCC_EXT_L_TO_H | RTCC_DIV_2);// KHOI TAO COUNTER

SETUP_TIMER_0(RTCC_EXT_L_TO_H);
// MAC NHIEN DIV_2
SET_TIMER0(0);
DEM=GET_TIMER0();
SETUP_COUNTERS(RTCC_EXT_L_TO_H,WDT_18MS);
52
// GIA TRI BAT DAU
// COUNTER
Khoa ien ien t
SET_TIMER0(0);
DEM=GET_TIMER0();
Nguyen nh Phu
// GIA TRI BAT DAU
2.
C php:
setup_timer_1(mode)
Thng s :
mode c th l 1 hoc 2 hng s nh ngha trong file device.h. Cc thng s g m

T1_DISABLED, T1_INTERNAL, T1_EXTERNAL, T1_EXTERNAL_SYNC
TC_CLK_OUT
T1_DIV_BY_1, T1_DIV_BY_2, T1_DIV_BY_4, T1_DIV_BY_8.
Cc hng s t nhi u nhm khc nhau th c th or v i nhau.
V i tn s th ch anh l 20MHz v kh i t o T1_DIV_BY_8 th timer s tng gi tr sau m i
kho ng th i gian 1.6s. Timer s trn sau 104.8576 ms.
Ch c nng:
kh i t o cho TIMER1.
V i tn s th ch anh l 20MHz v kh i t o T1_DIV_BY_8 th timer s tng gi tr sau m i
kho ng th i gian 1.6s. Timer s trn sau 104.8576 ms.
C hi u l c: cho tt c cc vi i u khi n PIC c timer 1.

V d :
SETUP_TIMER_1 (T1_DISABLED);
SETUP_TIMER_1 (T1_INTERNAL|T1_DIV_BY_4);
SETUP_TIMER_1 (T1_INTERNAL|T1_DIV_BY_8);
SETUP_TIMER_1(T1_EXTERNAL | T1_DIV_BY_1);
SET_TIMER1(0);
DEM=GET_TIMER1();
3.
// KHOI TAO COUNTER

// GIA TRI BAT DAU
C php:
setup_timer_2(mode, period, postscale)
Thng s :
mode c th l 1 trong cc thng s : T2_DISABLED, T2_DIV_BY_1, T2_DIV_BY_4,

T2_DIV_BY_16
Period l s nguyn c gi tr t 0 n 255 dng xc nh khi no gi tr clock b reset.
postscale l s nguyn c gi tr t 1 n 16 dng xc nh timer trn bao nhiu ln tr
khi pht sinh tn hi u ngt.
Ch c nng:
kh i t o cho TIMER2.
Mode ch nh ki u b chia c a timer t tn s c a m ch dao ng.
Gi tr c a timer c th c hoc ghi dng l nh GET_TIMER2() v SET_TIMER2().
TIMER2 l timer 8 bit.
C hi u l c: cho tt c cc vi i u khi n PIC c timer 2.

V d :
SETUP_TIMER_2 (T1_ DIV_BY_4,0XC0,2);

V i l nh kh i t o ny th timer2 s tng gi tr sau m i kho ng th i gian 800ns, s trn sau
kho ng th i gian 154.4s v pht sinh yuc cu ngt sau 308.8 s.
m i
4.
LNH SET_TIMERx(value) - LNH THI T LP GI TR B T U CHO TIMER
C php:
set_timerX(value)
; x l 0, 1, 2
Thng s :
value l hng s nguyn 8 hoc 16 bit dng thi t lp gi tr m i cho timer.
53
Khoa ien ien t
Ch c nng:
Nguyen nh Phu
thi t lp gi tr bt u cho TIMER.
C hi u l c: cho tt c cc vi i u khi n PIC c timer.

V d :
5.
SET_TIMER2 (0);
//reset timer2
LNH GET_TIMERx() - LNH C GI TR C A TIMER
C php:
value = get_timerX() ; x l 0, 1, 2
Thng s :
khng c.
Ch c nng:
c gi tr c a TIMER/COUNTER.
C hi u l c: cho tt c cc vi i u khi n PIC c timer.

V d :
6.
DEM=GET_TIMER0();
LNH SETUP_WDT() - LNH THI T LP CHO WDT
C php:
Thng s :
Ch c nng:
C hi u l c:
Yu cu:
V d :
7.
setup_wdt (mode)
For PCB/PCM parts: WDT_18MS, WDT_36MS, WDT_72MS,
WDT_144MS,WDT_288MS, WDT_576MS, WDT_1152MS, WDT_2304MS
For PIC18 parts: WDT_ON, WDT_OFF
Thi t lp cho b nh th i watchdog.
B nh th i watchdog c s d ng reset phn c ng n u phn m m lp trnh b sa ly
nh ng vng lp v tn hoc m t s ki n no ch chng x y ra nh ng chng l i khng
bao gi x y ra, chm d t vi c ch i ny th ta ph i s d ng b nh th i watchdog.
Tr c khi ti n hnh vo vng lp th ta ph i cho php b nh th i watchdog m v i
kho ng th i gian lp trnh tr c v n u s ki n khng x y ra th b nh th i watchdog
s h t th i gian lp trnh s reset phn c ng thot kh i vng lp.
PCB/PCM
PCH
Enable/Disable
#fuses
setup_wdt()
Timeout time
setup_wdt()
#fuses
Restart
restart_wdt()
restart_wdt()
Cho tt c cc thi t b
#fuses, hng s c nh ngha trong file devices .h
#fuses WDT1 // PIC18 example, See restart_wdt for a PIC18 example
main() {
// WDT1 means 18ms*1 for old PIC18s and 4ms*1 for new PIC18s
// setup_wdt(WDT_ON);
while (TRUE) {
restart_wdt();
perform_activity();
}
}
LNH RESTART_WDT() - LNH KH I NG L I CHO WDT
C php:
Thng s :
Ch c nng:
54
//c gi tr c a timer0
restart_wdt()
Khng c
Kh i t o l i b nh th i watchdog. N u b nh th i watchdog c cho php th l nh ny
s kh i t o l i gi tr nh th i ngn chn khng cho b nh th i reset CPU v s ki n ch
i x y ra.
PCB/PCM
PCH
Enable/Disable #fuses
setup_wdt()
Timeout time setup_wdt()
#fuses
restart
restart_wdt() restart_wdt()
Khoa ien ien t
Availability: All devices

Requires:
#fuses
Examples:
#fuses WDT
Nguyen nh Phu
// PCB/PCM example
// See setup_wdt for a PIC18 example
main() {
setup_wdt(WDT_2304MS);
while (TRUE) {
restart_wdt();
perform_activity();
}
}
IV. CC CH NG TRNH NG D NG TIMER /COUNTER

1. NG D NG M XUNG NGO I HI N TH LED 7 O N TR C TI P
BI 5-1 M XUNG NGOI DNG COUNTER0, GI TR T 00 N 99 HIN TH
TRN 2 LED 7 ON NI TRC TIP VI PORTB V PORTC
S M CH I N
Hnh 5-11. M m i n t trn 2 led.

CHNG TRNH
#INCLUDE <16F877A.H>
55
Khoa ien ien t
Nguyen nh Phu
#FUSES NOWDT,PUT,HS,NOPROTECT,NOLVP
#USE DELAY(CLOCK=20000000)
CONST UNSIGNED CHAR
MALED7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80, 0x90};
INT
UNSIGNED CHAR
DONVI, CHUC, DEM;

MDONVI,MCHUC;
VOID DIV_DECODE (INT TAM)

{
CHUC = TAM/10;
//LAY HANG CHUC
DONVI= TAM %10;
//LAY DONVI
MCHUC = MALED7DOAN[CHUC];
MDONVI= MALED7DOAN[DONVI];
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_C(MCHUC);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_C(0x00);
// PORTC OUT
SETUP_TIMER_0 (RTCC_EXT_L_TO_H | RTCC_DIV_1);// KHOITAOTIMER
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
DISPLAY();
}
}
BI 5-2. M XUNG NGOI DNG COUNTER0, GI TR T 000 N 255 HIN TH
TRN 3 LED 7 ON NI TRC TIP VI 3 PORTB, PORTC V PORTD.
S M CH I N
56
Khoa ien ien t
Nguyen nh Phu

CHNG TRNH
CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DEM, TRAM, CHUC, DONVI;

MTRAM, MCHUC, MDONVI;

{
TRAM = TAM/100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
MTRAM = MALED7DOAN[TRAM];
}
VOID DISPLAY ()
//TAM=123
//LAY HANG TRAM=1
//LAY HANG VA DONVI =23
//LAY HANG CHUC=2
//LAY DONVI=3
57
Khoa ien ien t
Nguyen nh Phu
OUTPUT_B(MDONVI);
OUTPUT_D(MCHUC);
OUTPUT_C(MTRAM);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
SET_TRIS_C(0x00);
//PORTB OUT
// PORTD OUT
// PORTC OUT

SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
DISPLAY();
}
}
BI 5-3. M XUNG NGOI DNG COUNTER0, GI TR T 00 N 99 HIN TH
TRN 2 LED 7 ON NI TRC TIP VI 2 PORTB, PORTC.
S M CH I N GI NG BI 5-1.
CH NG TRNH CNG GI NG BI 5-1
CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DONVI, CHUC, DEM;

MDONVI,MCHUC;

{
CHUC = TAM/10;
//LAY HANG CHUC
DONVI= TAM %10;
//LAY DONVI
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_C(MCHUC);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_C(0x00);
// PORTC OUT
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
IF (DEM==100) SET_TIMER0(1);
58
Khoa ien ien t
Nguyen nh Phu
DISPLAY();
}
}
BI 5-4. M XUNG NGOI DNG COUNTER1, GI TR T 00 N 99 HIN TH TRN 2 LED 7

ON NI TRC TIP VI 2 PORTB, PORTD. CH KHI BNG 100 TH QUAY V 1
S O MACH IEN

CH
NG TRNH
CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DONVI, CHUC, DEM;

MDONVI, MCHUC;

59
Khoa ien ien t
Nguyen nh Phu
{
CHUC = TAM/10;
DONVI= TAM %10;
//LAY HANG CHUC

//LAY DONVI
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_D(MCHUC);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
SETUP_TIMER_1 (T1_EXTERNAL | T1_DIV_BY_1);
SET_TIMER1(0);
//PORTB OUT
// PORTD OUT
// KHOITAOTIMER
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER1();
DIV_DECODE(DEM);
IF (DEM==100) SET_TIMER1(1);
DISPLAY();
}
}
2.
NG D NG M XUNG NGO I HI N TH LED 7 O N QUT
S M CH GIAO TI P PIC V I 8 LED 7 O N DNG PORTB V PORTB
60
Khoa ien ien t
Nguyen nh Phu
Hnh 5-14. Vi i u ki n PIC iao ti p v i 8 l 7 o n.
BI 5-5: IU KHIN 8 LED 7 ON QUT HIN TH 8 S T 0 N 7 TRN 8 LED

DNG PORTB IU KHIN CC ON A,B,C,D,E,F,G,DP.
PORTD IU KHIN CC TRANSISTOR TT M LED
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
OUTPUT_B(0xC0); OUTPUT_D(0B11111110);
OUTPUT_B(0XF9); OUTPUT_D(0B11111101);
OUTPUT_B(0XA4); OUTPUT_D(0B11111011);
OUTPUT_B(0XB0); OUTPUT_D(0B11110111);
OUTPUT_B(0x99); OUTPUT_D(0B11101111);
OUTPUT_B(0X92); OUTPUT_D(0B11011111);
OUTPUT_B(0X82); OUTPUT_D(0B10111111);
OUTPUT_B(0XF8); OUTPUT_D(0B01111111);
}
}
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
BI 5-6: CHNG TRNH M T 00 N 99 HIN TH LED 7 ON QUT

PORTD IU KHIN CC TRANSISTOR TT M LED
CONST UNSIGNED CHAR
MALED7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};
INT
DEM, DONVI, CHUC, I;
UNSIGNED CHAR MDONVI, MCHUC;
VOID DIV_BCD(INT TAM)
//CH TR CON TACH CHUC VA DON VI GIAI MA
{
CHUC
=
TAM /10;
// CHUC BANG TAM CHIA CHO 10
DONVI
=
TAM%10;
MCHUC
=
MALED7DOAN[CHUC];
MDONVI
=
MALED7DOAN[DONVI];
61
Khoa ien ien t
Nguyen nh Phu
}
VOID DELAY_HIENTHI()
{
FOR (I=0; I<250;I++)
{
OUTPUT_B(MDONVI);
OUTPUT_D(0xFE);
OUTPUT_B(MCHUC);
OUTPUT_D(0xFD);
}
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
FOR (DEM=0; DEM<100; DEM++)
{
DIV_BCD(DEM);
DELAY_HIENTHI();
}
}
}
DELAY_MS(1);
DELAY_MS(1);
BI 5-7: IU KHIN LED 7 ON QUT M T 00 N 99 HIN TH LED QUT V HIN

TH GI TR M DNG NH PHN
PORTD IU KHIN CC TRANS
CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DEM, DONVI, CHUC, I;

MDONVI, MCHUC;
VOID DIV_BCD(INT TAM)

//CH TR CON TACH CHUC VA DON VI GIAI MA
{
CHUC
=
TAM /10;
// CHUC BANG TAM CHIA CHO 10
DONVI
=
TAM%10;
MCHUC
=
MALED7DOAN[CHUC];
MDONVI
=
MALED7DOAN[DONVI];
}
VOID HIENTHI()
{
FOR (I=0; I<250;I++)
{
OUTPUT_B(MDONVI);
OUTPUT_D(0xFE);
DELAY_MS(1);
OUTPUT_B(MCHUC);
OUTPUT_D(0xFD);
DELAY_MS(1);
}
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
SET_TRIS_C(0x00);
WHILE(1)
{
FOR (DEM=0;DEM<100;DEM++)
{
62
Khoa ien ien t
Nguyen nh Phu
OUTPUT_C(DEM);
DIV_BCD(DEM);
HIENTHI();
}
}
}
BI 5-8: IU KHIN LED 7 ON QUT M T 0000 N 9999 HIN TH LED QUT
DNG PB IU KHIN CC ON A,B,C,D,E,F,G,DP. PD IU KHIN CC TRANS
CONST UNSIGNED CHAR
INT16
DEM;
INT
DONVI, CHUC, TRAM, NGAN, I;
UNSIGNED CHAR MDONVI, MCHUC, MTRAM, MNGAN;
VOID DIV_BCD (INT16 TAM)
{
NGAN
=
TAM/1000;
TAM
=
TAM%1000;
TRAM
=
TAM/100;
TAM
=
TAM%100;
CHUC
=
TAM /10;
DONVI
=
TAM%10;
MNGAN
MTRAM
MCHUC
MDONVI
=
=
=
=
//VI DU TAM = 3567

//NGAN =3
//TAM = 567
//TRAM = 5
//TAM = 67
//CHUC = 6
//DONVI = 7
MALED7DOAN[NGAN];
MALED7DOAN[TRAM];
MALED7DOAN[CHUC];
MALED7DOAN[DONVI];
}
VOID HIENTHI()
{
FOR (I=0; I<2;I++)
{
OUTPUT_B(MDONVI);
OUTPUT_B(MCHUC);
OUTPUT_B(MTRAM);
OUTPUT_B(MNGAN);
}
}
OUTPUT_D(0B11111110);
OUTPUT_D(0B11111101);
OUTPUT_D(0B11111011);
OUTPUT_D(0B11110111);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
{
DIV_BCD(DEM);
HIENTHI();
}
}
}
63
Khoa ien ien t
Nguyen nh Phu
BI 5-9: IU KHIN LED 7 ON QUT M T 0000 N 9999 HIN TH LED QUT

DNG PB IU KHIN CC ON A,B,C,D,E,F,G,DP. PD IU KHIN CC TRANS XA S 0
V NGHA
CONST UNSIGNED CHAR
INT16
DEM;
INT
DONVI, CHUC, TRAM, NGAN, I;
UNSIGNED CHAR MDONVI, MCHUC, MTRAM, MNGAN;
VOID DIV_BCD (INT16 TAM)
{
NGAN
=
TAM/1000;
TAM
=
TAM%1000;
TRAM
=
TAM/100;
TAM
=
TAM%100;
CHUC
=
TAM /10;
DONVI
=
TAM%10;
//VI DU TAM = 3567

//NGAN =3
//TAM = 567
//TRAM = 5
//TAM = 67
//CHUC = 6
//DONVI = 7
MNGAN
=
MALED7DOAN[NGAN];
MTRAM
=
MALED7DOAN[TRAM];
MCHUC
=
MALED7DOAN[CHUC];
MDONVI
=
MALED7DOAN[DONVI];
IF
(MNGAN == 0XC0)
{
MNGAN=0XFF;
IF (MTRAM ==0XC0)
{MTRAM=0XFF;
IF (MCHUC == 0XC0)
{MCHUC =0XFF;
}
}
}
}
VOID HIENTHI()
{
FOR (I=0; I<2;I++)
{
OUTPUT_B(MDONVI);
OUTPUT_B(MCHUC);
OUTPUT_B(MTRAM);
OUTPUT_B(MNGAN);
}
}
OUTPUT_D(0B11111110);
OUTPUT_D(0B11111101);
OUTPUT_D(0B11111011);
OUTPUT_D(0B11110111);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
{
DIV_BCD(DEM);
64
Khoa ien ien t
Nguyen nh Phu
HIENTHI();
}
}
}
65
Khoa ien ien t
Nguyen nh Phu
BI 5-10: IU KHIN LED 7 ON QUT M T 000 N 200 LED QUT

CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DEM,DONVI,CHUC,I,TRAM;
MDONVI,MCHUC,MTRAM;

{
TRAM = TAM / 100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_B(MCHUC);
OUTPUT_B(MTRAM);
// BIEN DEM
// BIEN CHUA MA 7 DOAN
//LAY HANG TRAM

/LAY CHUC VA DON VI
//LAY HANG CHUC
//LAY DONVI
//LAY MA 7 D
//LAY MA 7 D
//LAY MA 7 D
OUTPUT_D(0B11111110);
OUTPUT_D(0B11111101);
OUTPUT_D(0B11111011);
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_D(0x00);
// PORTD OUT
WHILE(1)
{
{
DIV_DECODE(DEM);
FOR (I=0;I<50;I++)
{
DISPLAY();
}
}
}
}
BI 5-11: IU KHIN LED 7 ON QUT M T 000 N 300 V XA S 0 V NGHA
CONST UNSIGNED CHAR
INT16
INT
66
DEM;
DONVI,CHUC,I,TRAM;
// BIEN DEM 16 BIT

// BIEN 8 BIT
UNSIGNED CHAR
Khoa ien ien t
MDONVI,MCHUC,MTRAM;
VOID DIV_DECODE (INT16 TAM)

{
TRAM = TAM / 100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
Nguyen nh Phu
// BIEN CHUA MA 7 DOAN
//LAY HANG TRAM

//LAY CHUC VA DON VI
//LAY HANG CHUC
//LAY DONVI
IF (TRAM == 0)
{
MTRAM=0XFF;
IF (CHUC == 0 )
{ MCHUC=0XFF;
}
}
// XOA SO 0 VO NGHIA
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_D(0B11111110);
OUTPUT_B(MCHUC);
OUTPUT_D(0B11111101);
OUTPUT_B(MTRAM);
OUTPUT_D(0B11111011);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_D(0x00);
// PORTD OUT
WHILE(1)
{
{
DIV_DECODE(DEM);
FOR (I=0;I<20;I++)
{
DISPLAY();
}
}
}
}
DELAY_MS(1);
DELAY_MS(1);
DELAY_MS(1);
BI 5-12: IU KHIN LED 7 ON QUT M PHT GIY

CONST UNSIGNED CHAR
INT
PHUT,GIAY,DVPHUT,CHPHUT,DVGIAY,CHGIAY,I;
UNSIGNED CHAR MCHPHUT, MDVPHUT,MCHGIAY, MDVGIAY;
VOID DIV_BCD_PHUT (INT TAMP)
{
CHPHUT
=
TAMP/10;
DVPHUT
=
TAMP%10;
MCHPHUT =
MALED7DOAN[CHPHUT];
MDVPHUT =
MALED7DOAN[DVPHUT];
}
VOID DIV_BCD_GIAY (INT TAMG)
67
Khoa ien ien t
Nguyen nh Phu
{
CHGIAY
DVGIAY
MCHGIAY
MDVGIAY
=
=
=
=
TAMG/10;
TAMG%10;
MALED7DOAN[CHGIAY];
MALED7DOAN[DVGIAY];
}
VOID HIENTHI()
{
FOR (I=0; I<2;I++)
{
OUTPUT_B(MDVGIAY);
OUTPUT_B(MCHGIAY);
OUTPUT_D(0B11111110);
OUTPUT_D(0B11111101);
DELAY_MS(1);
DELAY_MS(1);
OUTPUT_B(MDVPHUT);
OUTPUT_B(MCHPHUT);
OUTPUT_D(0B11110111);
OUTPUT_D(0B11101111);
DELAY_MS(1);
DELAY_MS(1);
}
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
FOR (PHUT=0;PHUT<60;PHUT++)
{
FOR (GIAY=0; GIAY <60; GIAY ++)
{
DIV_BCD_PHUT(PHUT);
DIV_BCD_GIAY(GIAY);
HIENTHI();
}
}
}
}
BI 5-13: I U KHI N LD 7 O N QUT M GI PHT GIY
CONST UNSIGNED CHAR
INT
PHUT,GIAY ,DVPHUT,CHPHUT,DVGIAY,CHGIAY,I;
UNSIGNED CHAR MCHPHUT, MDVPHUT,MCHGIAY, MDVGIAY;
INT
GIO ,DVGIO,CHGIO;
UNSIGNED CHAR MCHGIO, MDVGIO;
VOID DIV_BCD_GIO (INT TAMGIO)
{
CHGIO
=
TAMGIO/10;
DVGIO
=
TAMGIO%10;
MCHGIO
=
MALED7DOAN[CHGIO];
MDVGIO
=
MALED7DOAN[DVGIO];
}
VOID DIV_BCD_PHUT (INT TAMP)
{
CHPHUT
=
TAMP/10;
DVPHUT
=
TAMP%10;
68
Khoa ien ien t
MCHPHUT
MDVPHUT
=
=
Nguyen nh Phu
MALED7DOAN[CHPHUT];
MALED7DOAN[DVPHUT];
}
VOID DIV_BCD_GIAY (INT TAMG)
{
CHGIAY
=
TAMG/10;
DVGIAY
=
TAMG%10;
MCHGIAY =
MALED7DOAN[CHGIAY];
MDVGIAY =
MALED7DOAN[DVGIAY];
}
VOID HIENTHI()
{
FOR (I=0; I<2;I++)
{
OUTPUT_B(MDVGIAY); OUTPUT_D(0B11111110);
OUTPUT_B(MCHGIAY); OUTPUT_D(0B11111101);
DELAY_MS(1);
DELAY_MS(1);
OUTPUT_B(MDVPHUT);
OUTPUT_B(MCHPHUT);
OUTPUT_D(0B11110111);
OUTPUT_D(0B11101111);
DELAY_MS(1);
DELAY_MS(1);
OUTPUT_B(MDVGIO);
OUTPUT_B(MCHGIO);
OUTPUT_D(0B10111111);
OUTPUT_D(0B01111111);
DELAY_MS(1);
DELAY_MS(1);
}
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
WHILE(1)
{
FOR(GIO=0;GIO<24;GIO++)
{
FOR (PHUT=0;PHUT<60;PHUT++)
{
FOR (GIAY=0; GIAY <60; GIAY ++)
{
DIV_BCD_GIO(GIO);
DIV_BCD_PHUT(PHUT);
DIV_BCD_GIAY(GIAY);
HIENTHI();
}
}
}
}
}
BI 5-14: TIMER0 M XUNG NGOI COUNTER0 T 000 N 255
HIN TH TRN 3 LED QUET
CONST UNSIGNED CHAR MALED7DOAN[10]={0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,
0x90};
INT
UNSIGNED CHAR MTRAM, MCHUC, MDONVI;
69
Khoa ien ien t

{
TRAM = TAM/100;
CHUC = TAM/10;
DONVI= TAM %10;
Nguyen nh Phu
TAM = TAM %100;

//LAY HANG CHUC
//LAY DONVI
IF (TRAM == 0)
{
MTRAM=0XFF;
IF (CHUC == 0)
{ MCHUC=0XFF;
}
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
DELAY_MS(1);
OUTPUT_LOW(PIN_D0);
OUTPUT_HIGH(PIN_D0);
OUTPUT_B(MCHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MTRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
OUTPUT_D(0XFF);
SETUP_TIMER_0(RTCC_EXT_H_TO_L | RTCC_DIV_1);// KHOITAOTIMER
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
DISPLAY();
}
}
BI 5-15: TIMER0 M S VNG QUAY 4 XUNG L 1 VNG COUNTER0 T 000 N 255
HIN TH TRN 3 LED QUET
CONST UNSIGNED CHAR
INT
{
TRAM = TAM/100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
70
//LAY HANG CHUC

//LAY DONVI
Khoa ien ien t
Nguyen nh Phu
IF (TRAM == 0)
{
MTRAM=0XFF;
IF (CHUC == 0 )
{ MCHUC=0XFF;
}
}
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
DELAY_MS(1);
OUTPUT_LOW(PIN_D0);
OUTPUT_B(MCHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MTRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_D(0x00);
// PORTD OUT
OUTPUT_D(0XFF);
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
DISPLAY();
}
}
BI 5-16: TIMER0 M 0 N 100 HIN TH TRN 3 LED QUET
CONST UNSIGNED CHAR
INT
{
TRAM = TAM/100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
//LAY HANG CHUC

//LAY DONVI
71
Khoa ien ien t
IF (TRAM == 0)
{
MTRAM=0XFF;
IF (CHUC == 0 )
{ MCHUC=0XFF;
}
}
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
DELAY_MS(1);
Nguyen nh Phu
OUTPUT_LOW(PIN_D0);
OUTPUT_B(MCHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MTRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_D(0x00);
// PORTD OUT
OUTPUT_D(0XFF);
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
IF (DEM==101)
{SET_TIMER0(1);
}
DIV_DECODE(DEM);
DISPLAY();
}
}
THAY DOI
VOID MAIN()
{
SET_TRIS_B(0x00);
SET_TRIS_D(0x00);
//PORTB OUT
// PORTD OUT
SETUP_COUNTERS(RTCC_EXT_L_TO_H,WDT_18MS);// KHOITAOTIMER
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
DISPLAY();
}
}
BI 5-17: TIMER0 M XUNG NGOI COUNTER0 T 000 N 255 V XA S 0 V NGHA
72
Khoa ien ien t
Nguyen nh Phu
CONST UNSIGNED CHAR
INT
UNSIGNED CHAR
DONVI,CHUC, TRAM, I,DEM;

MDONVI,MCHUC,MTRAM;

{
TRAM = TAM / 100;
TAM = TAM %100;
CHUC = TAM/10;
DONVI= TAM %10;
//LAY HANG TRAM

//LAY CHUC VA DON VI
//LAY HANG CHUC
//LAY DONVI
IF (TRAM == 0)
{
MTRAM=0XFF;
IF (CHUC == 0 )
{ MCHUC=0XFF;
}
}
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
DELAY_MS(1);
OUTPUT_LOW(PIN_D0);
OUTPUT_B(MCHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MTRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
//PORTB OUT
SET_TRIS_D(0x00);
// PORTD OUT
SET_TRIS_C(0x00);
SETUP_COUNTERS(RTCC_EXT_L_TO_H,WDT_18MS);// KHOITAOTIMER
SET_TIMER0(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER0();
DIV_DECODE(DEM);
FOR (I=0;I<20;I++)
{
DISPLAY();
}
}
}
BI 5-18: TIMER1 M XUNG NGOI COUNTER T 00000 N 65535 V XA S 0 V
NGHA
73
Khoa ien ien t
Nguyen nh Phu
CONST UNSIGNED CHAR
INT16 DEM;
INT
UNSIGNED CHAR
DONVI,CHUC, TRAM, NGAN,CNGAN,I;

MDONVI,MCHUC,MTRAM,MNGAN,MCNGAN;
VOID DIV_DECODE (INT16 TAM)

{ CNGAN = TAM / 10000;
//LAY CHUC NGAN
TAM
= TAM % 10000;
NGAN = TAM / 1000;
//LAY NGAN
TAM = TAM % 1000;
TRAM = TAM / 100;
//LAY HANG TRAM
TAM = TAM %100;
CHUC = TAM/10;
//LAY HANG CHUC
DONVI= TAM %10;
//LAY DONVI
MCNGAN = MALED7DOAN[CNGAN];
MNGAN = MALED7DOAN[NGAN];
IF (CNGAN == 0)
{MCNGAN=0XFF;
IF (NGAN == 0)
{ MNGAN=0XFF;
IF (TRAM == 0)
{ MTRAM=0XFF;
IF (CHUC == 0 )
{ MCHUC=0XFF;
}
}
}
}
}
VOID DISPLAY ()
{
OUTPUT_B(MDONVI);
OUTPUT_LOW(PIN_D0);
DELAY_MS(1);
OUTPUT_B(MCHUC);
DELAY_MS(1);
OUTPUT_LOW(PIN_D1);
OUTPUT_B(MTRAM);
DELAY_MS(1);
OUTPUT_LOW(PIN_D2);
OUTPUT_B(MNGAN);
DELAY_MS(1);
OUTPUT_LOW(PIN_D3);
OUTPUT_B(MCNGAN);
DELAY_MS(1);
OUTPUT_LOW(PIN_D4);
}
VOID MAIN()
{
SET_TRIS_B(0x00);
74
//PORTB OUT
Khoa ien ien t
Nguyen nh Phu
SET_TRIS_D(0x00);
//PORTD OUT
SETUP_TIMER_1(T1_EXTERNAL | T1_DIV_BY_1);
// KHOITAOTIMER
SET_TIMER1(0);
// GIA TRI BAT DAU
WHILE(1)
{
DEM=GET_TIMER1();
DIV_DECODE(DEM);
DISPLAY();
}
}
NG D NG M XUNG N I - NH TH I
3.
BI 5-19 IU KHIN LED CHP TT THEO THI GIAN DNG TIMER1 M XUNG NI
#USE DELAY(CLOCK=16M)
INT16 DEM;
VOID MAIN()
{ SET_TRIS_A(0x00);
//PORTB OUT
SETUP_TIMER_1(T1_INTERNAL | T1_DIV_BY_8); // KHOITAOTIMER
SET_TIMER1(0);
// GIA TRI BAT DAU
WHILE(1)
{ DEM=GET_TIMER1();
IF (DEM <35000)
OUTPUT_A(0X00);
ELSE
OUTPUT_A(0XFF);
}
}
BI 5-20: IU KHIN LED CHP TT THEO THI GIAN DNG TIMER1 M XUNG NI
DNG PHNG PHP KIM TRA C TRN TIMER1
#include <DEF_16F877A.h>
INT16 DEM;
VOID MAIN()
{ SET_TRIS_A(0x00);
//PORTB OUT
DEM=0X0;
SET_TIMER1(0);
// GIA TRI BAT DAU
75
Khoa ien ien t
Nguyen nh Phu
WHILE(1)
{ IF (tmr1if==1)
{
OUTPUT_A(DEM); DEM=0XFF-DEM;
tmr1if=0;
}
}
}
S DNG NGT TIMER1
INT16 DEM;
#int_timer1
void interrupt_timer1()
{
OUTPUT_TOGGLE(PIN_A0);
}
VOID MAIN()
{
SET_TRIS_A(0x00);
SET_TIMER1(0);
// GIA TRI BAT DAU
enable_interrupts(GLOBAL);
enable_interrupts(int_timer1);
WHILE(1)
{
}
}
BI 5-22 IU KHIN LED CHP TT THEO THI GIAN DNG TIMER1 M XUNG NI
DNG NGT NH THI 100MS
INT16 DEM;
#int_timer1
{
OUTPUT_TOGGLE(PIN_A0); SET_TIMER1(15536);
}
VOID MAIN()
{
SET_TRIS_A(0x00);
76
SET_TIMER1(15536);
WHILE(1)
{
}
Khoa ien ien t
Nguyen nh Phu
// GIA TRI BAT DAU
}
DNG NGT NH THI 1S
INT DEM;
#int_timer1
{ DEM++;
SET_TIMER1(15536);
IF (DEM==10)
{ DEM=0;
OUTPUT_TOGGLE(PIN_A0);}
}
VOID MAIN()
{
SET_TRIS_A(0x00);
SET_TIMER1(15536);
// GIA TRI BAT DAU
DEM=0;
WHILE(1)
{
}
}
V.
+
+=
&=
&
&
^=
^
l=
CC TON T
Addition Operator
Addition assignment operator, x+=y,
is the same as x=x+y
Bitwise and assignment operator,
x&=y, is the same as x=x&y
Address operator
Bitwise and operator
Bitwise exclusive or assignment
operator, x^=y, is the same as x=x^y
Bitwise exclusive or operator
Bitwise inclusive or assignment
77
l
?:
-/=
/
==
>
>=
++
*
!=
<<=
<
<<
<=
&&
!
ll
%=
%
*=
*
~
>>=
>>
->
-=
sizeof
VI.
Khoa ien ien t
Nguyen nh Phu
operator, xl=y, is the same as x=xly

Bitwise inclusive or operator
Conditional Expression operator
Decrement
Division assignment operator, x/=y,
is the same as x=x/y
Division operator
Equality
Greater than operator
Greater than or equal to operator
Increment
Indirection operator
Inequality
Left shift assignment operator,
x<<=y, is the same as x=x<<y
Less than operator
Left Shift operator
Less than or equal to operator
Logical AND operator
Logical negation operator
Logical OR operator
Modules assignment operator x%=y,
is the same as x=x%y
Modules operator
Multiplication assignment operator,
x*=y, is the same as x=x*y
Multiplication operator
One's complement operator
Right shift assignment, x>>=y, is the
same as x=x>>y
Right shift operator
Structure Pointer operation
Subtraction assignment operator
Subtraction operator
Determines size in bytes of operand
FIL DEVICE
//////// Standard Header file for the PIC16F877A device ////////////////

#device PIC16F877A
#nolist
//////// Program memory: 8192x14 Data RAM: 367 Stack: 8
//////// I/O: 33 Analog Pins: 8
//////// Data EEPROM: 256
//////// C Scratch area: 77 ID Location: 2000
//////// Fuses: LP,XT,HS,RC,NOWDT,WDT,NOPUT,PUT,PROTECT,DEBUG,NODEBUG
//////// Fuses: NOPROTECT,NOBROWNOUT,BROWNOUT,LVP,NOLVP,CPD,NOCPD,WRT_50%
//////// Fuses: NOWRT,WRT_5%,WRT_25%
////////
////////////////////////////////////////////////////////////////// I/O
// Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
78
Khoa ien ien t
Nguyen nh Phu
//
PORT_x_PULLUPS(), INPUT(),
//
OUTPUT_LOW(), OUTPUT_HIGH(),
//
OUTPUT_FLOAT(), OUTPUT_BIT()
// Constants used to identify pins in the above are:
#define PIN_A0
#define PIN_A1
#define PIN_A2
#define PIN_A3
#define PIN_A4
#define PIN_A5
40
41
42
43
44
45
#define PIN_B0
#define PIN_B1
#define PIN_B2
#define PIN_B3
#define PIN_B4
#define PIN_B5
#define PIN_B6
#define PIN_B7
48
49
50
51
52
53
54
55
#define PIN_C0
#define PIN_C1
#define PIN_C2
#define PIN_C3
#define PIN_C4
#define PIN_C5
#define PIN_C6
#define PIN_C7
56
57
58
59
60
61
62
63
#define PIN_D0
#define PIN_D1
#define PIN_D2
#define PIN_D3
#define PIN_D4
#define PIN_D5
#define PIN_D6
#define PIN_D7
64
65
66
67
68
69
70
71
#define PIN_E0 72
#define PIN_E1 73
#define PIN_E2 74
////////////////////////////////////////////////////////////////// Useful defines
#define FALSE 0
#define TRUE 1
#define BYTE int
#define BOOLEAN short int
#define getc getch
#define fgetc getch
#define getchar getch
#define putc putchar
#define fputc putchar
#define fgets gets
79
Khoa ien ien t
Nguyen nh Phu
#define fputs puts

////////////////////////////////////////////////////////////////// Control
// Control Functions: RESET_CPU(), SLEEP(), RESTART_CAUSE()
// Constants returned from RESTART_CAUSE() are:
#define WDT_FROM_SLEEP 3
#define WDT_TIMEOUT 11
#define MCLR_FROM_SLEEP 19
#define MCLR_FROM_RUN 27
#define NORMAL_POWER_UP 24
#define BROWNOUT_RESTART 26
////////////////////////////////////////////////////////////////// Timer 0
// Timer 0 (AKA RTCC)Functions: SETUP_COUNTERS() or SETUP_TIMER_0(),
//
SET_TIMER0() or SET_RTCC(),
//
GET_TIMER0() or GET_RTCC()
// Constants used for SETUP_TIMER_0() are:
#define RTCC_INTERNAL 0
#define RTCC_EXT_L_TO_H 32
#define RTCC_EXT_H_TO_L 48
#define RTCC_DIV_1
#define RTCC_DIV_2
#define RTCC_DIV_4
#define RTCC_DIV_8
#define RTCC_DIV_16
#define RTCC_DIV_32
#define RTCC_DIV_64
#define RTCC_DIV_128
#define RTCC_DIV_256
8
0
1
2
3
4
5
6
7
#define RTCC_8_BIT
// Constants used for SETUP_COUNTERS() are the above

// constants for the 1st param and the following for
// the 2nd param:
////////////////////////////////////////////////////////////////// WDT
// Watch Dog Timer Functions: SETUP_WDT() or SETUP_COUNTERS() (see above)
//
RESTART_WDT()
//
#define WDT_18MS
8
#define WDT_36MS
9
#define WDT_72MS
10
#define WDT_144MS
11
#define WDT_288MS
12
#define WDT_576MS
13
#define WDT_1152MS 14
#define WDT_2304MS 15
////////////////////////////////////////////////////////////////// Timer 1
// Timer 1 Functions: SETUP_TIMER_1, GET_TIMER1, SET_TIMER1
//
(or (via |) together constants from each group)
80
Khoa ien ien t
Nguyen nh Phu
#define T1_DISABLED
0
#define T1_INTERNAL
0x85
#define T1_EXTERNAL
0x87
#define T1_EXTERNAL_SYNC 0x83
#define T1_CLK_OUT
#define T1_DIV_BY_1
#define T1_DIV_BY_2
#define T1_DIV_BY_4
#define T1_DIV_BY_8
0
0x10
0x20
0x30
////////////////////////////////////////////////////////////////// Timer 2
// Timer 2 Functions: SETUP_TIMER_2, GET_TIMER2, SET_TIMER2
#define T2_DISABLED
0
#define T2_DIV_BY_1
4
#define T2_DIV_BY_4
5
#define T2_DIV_BY_16
6
////////////////////////////////////////////////////////////////// CCP
// CCP Functions: SETUP_CCPx, SET_PWMx_DUTY
// CCP Variables: CCP_x, CCP_x_LOW, CCP_x_HIGH
// Constants used for SETUP_CCPx() are:
#define CCP_OFF
0
#define CCP_CAPTURE_FE
4
#define CCP_CAPTURE_RE
5
#define CCP_CAPTURE_DIV_4
6
#define CCP_CAPTURE_DIV_16
7
#define CCP_COMPARE_SET_ON_MATCH
8
#define CCP_COMPARE_CLR_ON_MATCH
9
#define CCP_COMPARE_INT
0xA
#define CCP_COMPARE_RESET_TIMER
0xB
#define CCP_PWM
0xC
#define CCP_PWM_PLUS_1
0x1c
0x2c
0x3c
long CCP_1;
#byte CCP_1 =
0x15
#byte CCP_1_LOW=
0x15
#byte CCP_1_HIGH=
0x16
long CCP_2;
#byte CCP_2 =
0x1B
#byte CCP_2_LOW=
0x1B
#byte CCP_2_HIGH=
0x1C
////////////////////////////////////////////////////////////////// PSP
// PSP Functions: SETUP_PSP, PSP_INPUT_FULL(), PSP_OUTPUT_FULL(),
//
PSP_OVERFLOW(), INPUT_D(), OUTPUT_D()
// PSP Variables: PSP_DATA
// Constants used in SETUP_PSP() are:
#define PSP_ENABLED
0x10
#define PSP_DISABLED
0
#byte PSP_DATA=
////////////////////////////////////////////////////////////////// SPI
81
Khoa ien ien t
Nguyen nh Phu
// SPI Functions: SETUP_SPI, SPI_WRITE, SPI_READ, SPI_DATA_IN

// Constants used in SETUP_SPI() are:
#define SPI_MASTER
0x20
#define SPI_SLAVE
0x24
#define SPI_L_TO_H
0
#define SPI_H_TO_L
0x10
#define SPI_CLK_DIV_4 0
#define SPI_CLK_T2
3
#define SPI_SS_DISABLED 1
#define SPI_SAMPLE_AT_END 0x8000
#define SPI_XMIT_L_TO_H 0x4000
////////////////////////////////////////////////////////////////// UART
// Constants used in setup_uart() are:
// FALSE - Turn UART off
// TRUE - Turn UART on
#define UART_ADDRESS
2
#define UART_DATA
4
////////////////////////////////////////////////////////////////// COMP
// Comparator Variables: C1OUT, C2OUT
// Constants used in setup_comparator() are:
#define A0_A3_A1_A3 0xfff04
#define A0_A3_A1_A2_OUT_ON_A4_A5 0xfcf03
#define A0_A3_A1_A3_OUT_ON_A4_A5 0xbcf05
#define NC_NC_NC_NC 0x0ff07
#define A0_A3_A1_A2 0xfff02
#define A0_A3_NC_NC_OUT_ON_A4 0x9ef01
#define A0_VR_A1_VR 0x3ff06
#define A3_VR_A2_VR 0xcff0e
#bit C1OUT = 0x9c.6
#bit C2OUT = 0x9c.7
////////////////////////////////////////////////////////////////// VREF
// Constants used in setup_vref() are:
//
#define VREF_LOW 0xa0
#define VREF_HIGH 0x80
// Or (with |) the above with a number 0-15
#define VREF_A2 0x40
////////////////////////////////////////////////////////////////// ADC
// ADC Functions: SETUP_ADC(), SETUP_ADC_PORTS() (aka SETUP_PORT_A),
//
SET_ADC_CHANNEL(), READ_ADC()
// Constants used for SETUP_ADC() are:
#define ADC_OFF
0
// ADC Off
#define ADC_CLOCK_DIV_2 0x10000
82
Khoa ien ien t

#define ADC_CLOCK_INTERNAL 0x00c0
Nguyen nh Phu
// Internal 2-6us
// Constants used in SETUP_ADC_PORTS() are:

#define NO_ANALOGS
7 // None
#define ALL_ANALOG
0 // A0 A1 A2 A3 A5 E0 E1 E2
#define AN0_AN1_AN2_AN4_AN5_AN6_AN7_VSS_VREF 1 // A0 A1 A2 A5 E0 E1 E2 VRefh=A3
#define AN0_AN1_AN2_AN3_AN4
2 // A0 A1 A2 A3 A5
#define AN0_AN1_AN2_AN4_VSS_VREF
3 // A0 A1 A2 A5 VRefh=A3
#define AN0_AN1_AN3
4 // A0 A1 A3
#define AN0_AN1_VSS_VREF
5 // A0 A1 VRefh=A3
#define AN0_AN1_AN4_AN5_AN6_AN7_VREF_VREF 0x08 // A0 A1 A5 E0 E1 E2 VRefh=A3
VRefl=A2
#define AN0_AN1_AN2_AN3_AN4_AN5
0x09 // A0 A1 A2 A3 A5 E0
#define AN0_AN1_AN2_AN4_AN5_VSS_VREF 0x0A // A0 A1 A2 A5 E0 VRefh=A3
#define AN0_AN1_AN4_AN5_VREF_VREF
0x0B // A0 A1 A5 E0 VRefh=A3 VRefl=A2
#define AN0_AN1_AN4_VREF_VREF
0x0C // A0 A1 A5 VRefh=A3 VRefl=A2
#define AN0_AN1_VREF_VREF
0x0D // A0 A1 VRefh=A3 VRefl=A2
#define AN0
0x0E // A0
#define AN0_VREF_VREF
0x0F // A0 VRefh=A3 VRefl=A2
#define ANALOG_RA3_REF
0x1
//!old only provided for compatibility
#define A_ANALOG
0x2
#define A_ANALOG_RA3_REF
0x3
#define RA0_RA1_RA3_ANALOG 0x4
#define RA0_RA1_ANALOG_RA3_REF 0x5
#define ANALOG_RA3_RA2_REF
0x8 //!old only provided for compatibility
#define ANALOG_NOT_RE1_RE2
0x9 //!old only provided for compatibility
#define ANALOG_NOT_RE1_RE2_REF_RA3
0xA //!old only provided for compatibility
#define ANALOG_NOT_RE1_RE2_REF_RA3_RA2 0xB //!old only provided for compatibility
#define A_ANALOG_RA3_RA2_REF
0xC //!old only provided for compatibility
#define RA0_RA1_ANALOG_RA3_RA2_REF
0xD //!old only provided for compatibility
#define RA0_ANALOG
0xE //!old only provided for compatibility
#define RA0_ANALOG_RA3_RA2_REF
0xF //!old only provided for compatibility
// Constants used in READ_ADC() are:

#define ADC_START_AND_READ 7 // This is the default if nothing is specified
#define ADC_START_ONLY
1
#define ADC_READ_ONLY
6
////////////////////////////////////////////////////////////////// INT
// Interrupt Functions: ENABLE_INTERRUPTS(), DISABLE_INTERRUPTS(),
//
EXT_INT_EDGE()
//
// Constants used in EXT_INT_EDGE() are:
#define L_TO_H
0x40
#define H_TO_L
0
// Constants used in ENABLE/DISABLE_INTERRUPTS() are:
#define GLOBAL
0x0BC0
#define INT_RTCC
0x0B20
#define INT_RB
0xFF0B08
#define INT_EXT
0x0B10
#define INT_AD
0x8C40
#define INT_TBE
0x8C10
83
#define INT_RDA
#define INT_TIMER1
#define INT_TIMER2
#define INT_CCP1
#define INT_CCP2
#define INT_SSP
#define INT_PSP
#define INT_BUSCOL
#define INT_EEPROM
#define INT_TIMER0
#define INT_COMP
84
Khoa ien ien t
Nguyen nh Phu
0x8C20
0x8C01
0x8C02
0x8C04
0x8D01
0x8C08
0x8C80
0x8D08
0x8D10
0x0B20
0x8D40

Bai 005 VXL Pic Timer Libre

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BI 5

TP LNH C CHO CC TIMER

NG D NG M XUNG NGO I HI N TH TRN LED 7 O N TR C TI P

ai hoc s pham ky thuat tp HCM

Khoa ien ien t

Vi i u khi n PIC h 16F877A c 3 timer T0, T1 v T2. T0 l timer/counter 8 bit, T1 l timer/counter

Hnh 5-1: S ki a timr0.

Bai 5: Timer/counter cua PIC va lap trnh C.

ai hoc s pham ky thuat tp HCM

Khoa ien ien t

RBPU : bit i u khi n i n tr treo c a portb.

N u bit T0CS (OPTION_REG<5>) bng 1 th chn ch m xung ngoi Counter. Trong ch

c khng th c/ghi v c m i quan h v i Timer0 v Watchdog Timer.

Timer0 v i ngun xung m t bn ngoi:

Khi khng s d ng b chia tr c th ng vo xung clock bn ngoi gi ng nh ng ra b chia tr c.

Khoa ien ien t

ai hoc s pham ky thuat tp HCM

nh ng chu k Q2 v Q4 c a xung clock bn trong. Do , n rt cn thi t cho T0CKI

B chia tr c c th gn cho Timer0 hoc gn cho Watchdog Timer. B chia tr c th khng th c

c gn cho WDT th l nh CLRWDT s xo b chia tr

c cng v i Watchdog Timer.

Hnh 5-2: B ia tr n o timr.

Hnh 5-3: B ia tr n o WDT.

L b nh th i/ m 16 bit g m 2 thanh ghi 8 bit (TMR1H v TMR1L) c th c v ghi. Hai thanh

Bai 5: Timer/counter cua PIC va lap trnh C.

ai hoc s pham ky thuat tp HCM

Khoa ien ien t

Hnh 5-4: Cu tr timr T1.

Bai 5: Timer/counter cua PIC va lap trnh C.

Khoa ien ien t

ai hoc s pham ky thuat tp HCM

N u bit TMR1CS bng 0 th T1 ho t ng nh th i m xung n i c tn s bng FOSC/4. Bit i u

Bai 5: Timer/counter cua PIC va lap trnh C.

Khoa ien ien t

ai hoc s pham ky thuat tp HCM

Hnh 5-6. T1 o t n m xun no i t m ao n T1.

Hnh 5-7. T1 o t n m xun no i a n n vo T1CKI.

Hnh 5-8. Gin t i ian xun m a Countr1.

m c 1, counter s m khi c xung c nh ln.

Hnh d i th ng vo ang m c thp, xung c nh ln th nht th m ch vn ch a m, xung xu ng

Khi bit TMR1CS bng 1 th T1 ho t ng

N u bit T1OSCEN bng 1 th m xung t m ch dao ng c a T1.

N u bit T1OSCEN bng 1 th m xung c nh ln a n ng vo RC0/T1OSO/T1CKI.

N u bit T1SYNC bng 0 th ng vo xung ngo i c ng b v i xung bn trong.

N u bit T1SYNC bng 1 th xung ng vo t bn ngoi khng c ng b . B m ti p t c tng bt

c v ghi Timer1 trong ch m khng ng b :

Bai 5: Timer/counter cua PIC va lap trnh C.

Khoa ien ien t

ai hoc s pham ky thuat tp HCM

M ch dao ng c tch h p bn trong v t th ch anh n i gi a 2 chn T1OSI v T1OSO t o dao

Reset Timer1 s d ng ng ra CCP Trigger:

N u kh i CCP1 v CCP2 c nh cu hnh

Ho t ng reset lc cp ngu n POR (Power On Reset) hoc bt k reset no khc khng nh h ng

Cc thanh ghi c a Timer1 nh b ng sau:

Khoa ien ien t

ai hoc s pham ky thuat tp HCM

Timer2 l timer 8 bit c b chia tr c (prescaler) v c b chia sau (postscaler).

Hnh 5-10. S ki a Timr2.

Bai 5: Timer/counter cua PIC va lap trnh C.

ai hoc s pham ky thuat tp HCM

Khoa ien ien t

1x= h s chia l 16.

c v chia sau c a Timer2: