1.

Gii thiu
2. S khi v chn
3. T chc b nh
4. Cc thanh ghi chc nng c bit
5. Dao ng v hot ng reset
6. Tp lnh
7. Cc mode nh a ch
8. Lp trnh IO (IO Port Programming)
9. To tr
10.Lp trnh Timer/Counter
11.Lp trnh giao tip ni tip
12.Lp trnh ngt
13.Lp trnh hp ng
Xung & Hoi

8-1. Cng 1 (Port 1)

Port 1 (chn 1- 8)
Port 1 c k hiu P1
Cc chn: P1.0 - P1.7
S dng P1 trong cc v d sau y ch ra hot ng
ca chng
P1 l cng ra output (ghi d liu CPU ra cc chn
bn ngoi)
P1 l cng vo input (c d liu t cc chn bn
ngoi vo CPU bus)

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8-2. Cu trc phn cng ca P1.x

Read DFF

TB2

Vcc

Ti
Bus ni

P1.x

P1.x
Write to DFF

Clk

M1

TB1
Read pin

Xung & Hoi

8051 IC

a. Bus ni: giao tip vi CPU

b. B cht d liu DFF: lu tr gi tr ca chn. Khi
Write to DFF = 1: ghi d liu vo DFF
c. Hai b m 3 trng thi (tri-state buffers):
- TB1: iu khin bi Read pin. Khi Read pin = 1:
c gi tr ti chn ngoi
- TB2: iu khin bi Read DFF. Khi Read DFF =
1: c gi tr t DFF ni
d. Transistor M1

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B m 3 trng thi (Tri-state Buffer)

Output

Input

Tr khng cao
(h mch)

Tri-state control
(kch hot
mc cao)
0

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8-3. Ghi ra cng output

Vd:
BACK:

MOV

A, #55H

MOV

P1, A

ACALL

DELAY

CPL

SJMP

BACK

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8-3-1. Ghi 1 ra chn output P1.x

Read DFF

Vcc

TB2

1. ghi 1
Bus ni

Ti

P1.x

P1.x
Write to DFF

Clk

2. Chn ra l
Vcc

M1

output 1

TB1
Read pin

Xung & Hoi

8051 IC

8-3-2. Ghi 0 ra chn output P1.x

Read DFF

Vcc

TB2

1. ghi 0
Bus ni

Ti

P1.x

P1.X
Write to DFF

Clk

2. Chn ra
ni t

M1

output 0

TB1
Read pin

Xung & Hoi

8051 IC

8-4. c t chn input & b cht

Khi c chn, c hai kh nng sau:
c trng thi ca chn input (bn ngoi)
MOV A,Px
JNB

P2.1,Label

JB

P2.1,Label

c d liu b cht ca chn output (bn trong)

ANL P1,A
ORL

P1,A

INC

P1

c-Sa i-Ghi

Xung & Hoi

8-4-1. c t chn input

P1 l input, P1 phi c lp trnh bng cch ghi 1
vo tt c cc bit ca P1
MOV P1,#0FFH

; P1=11111111B
; P1 l input

BACK:

MOV A,P1
MOV P2,A
SJMP BACK

E tng t cho P0, P2, P3

Xung & Hoi

10

c 1 ti chn input

Read DFF

Bus ni

Vcc

TB2

1. ghi 1
MOV P1,#0FFH

2. MOV A,P1
Chn ngoi=1
Ti

P1.x

P1.x

Write to DFF
3. Read pin=1
Read DFF=0
Write to DFF=0

Clk

M1

TB1

Read pin
8051 IC
Xung & Hoi

11

c 0 ti chn input

Read DFF

Vcc

TB2

1. Ghi 1
MOV P1,#0FFH

Bus ni

Ti

2. MOV A,P1
Chn ngoi=0
0

P1.x

P1.x

Write to DFF
3. Read pin=1
Read DFF=0
Write to DFF=0

Clk

M1

TB1

Read pin
8051 IC
Xung & Hoi

12

Cc lnh c chn input

Lnh
MOV A,PX

V d
MOV A,P2

M t
c P2 vo A

JNB PX.Y,..

JNB P2.1,TARGET

Nhy nu P2.1 = 0

JB PX.Y,..

JB P1.3,TARGET

Nhy nu P1.3 = 1

MOV C,PX.Y

MOV C,P2.4

Copy trng thi chn

P2.4 vo CY

Xung & Hoi

13

8-4-2. c chn ouput tc c b cht

MOV P1,#55H;

P1=01010101

ORL

P1=11110101

P1,#0F0H;

Read DFF kch hot TB2 v chuyn d liu t Q ca

DFF vo CPU c c P1.7 = 0
CPU thc hin OR d liu ny vi bit 1 c 1
D ca DFF b thay i thnh 1
Ghi KQ ra chn P1.7 = 1

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14

c b cht
1. Read pin = 0
Read DFF = 1
Write to DFF = 0 (ban u P1.7=0)

Read DFF

Vcc

TB2

Ti

2. CPU tnh (P1.7 OR 1 )

Bus ni

D
1

Write to DFF
3. Ghi KQ vo DFF
Read pin=0
Read DFF=0
Write to DFF=1

4. P1.7 = 1

10

P1.7

P1.7
0

Clk

M1

TB1

Read pin
8051 IC
Xung & Hoi

15

c-Sa i-Ghi
c im ny bao gm 3 hnh ng trong 1 lnh n:
1. CPU c b cht
2. CPU thc hin tnh ton sa i b cht
3. Ghi ra chn
Ch : 8 chn ca Port lm vic c lp nhau

Xung & Hoi

16

Cc lnh c c im c-Sa i-Ghi

Lnh

V d

ANL

ANL P1,A

ORL

ORL P1,A

XRL

XRL P1,A

JBC PX.Y, TARGET

JBC P1.1, TARGET

CPL

CPL P1.2

INC

INC

DEC

DEC P1

DJNZ PX, TARGET

DJNZ P1,TARGET

MOV PX.Y,C

MOV P1.2,C

CLR PX.Y

CLR P1.3

SETB PX.Y

SETB P1.4

P1

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17

Tm li
1 chn l output th c th ghi d liu trc tip ra chn
1 chn l output th c trng thi ca chn ngha l c
b cht tng ng ca chn
1 chn l input th set n ln 1 trc khi thao tc
1 chn l input th c trng thi trc tip t chn

Xung & Hoi

18

Cu hi gi nh
Cch ghi d liu ra chn?
Cch c d liu t chn?
c gi tr t chn bn ngoi
Ti sao phi set chn trc khi tin hnh c?
c gi tr t b cht
Lnh nh th no gi l c tnh cht c-Sa i-Ghi?

Xung & Hoi

19

Bi ton 1: thao tc bit

Bi ton:
1. Theo di bit P1.2 cho n khi nhn c 1
2. Khi nhn c 1, ghi 45H ra P0
3. & gi xung High-to-Low ra chn P2.3

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20

Gii p:

AGAIN:

SETB
MOV
JNB
MOV
SETB
CLR

P1.2
A,#45H
P1.2,AGAIN
P0,A
P2.3
P2.3

;P1.2 l input
;A=45H
;lp li n khi P1.2=1
;xut A ra P0
;P2.3 = High
;P2.3 = Low for H-to-L

Trong
1. JNB: jump if no bit (jump if P1.2 = 0)
2. Xung H-to-L c to bi chui lnh SETB & CLR

Xung & Hoi

21

Bi ton 2: u im khi s dng cu lnh c c

im c-Sa i-Ghi
AC ba cch nhy cc bit ca Port 1 lin tc
Cch 1: Gi d liu ti P1 qua thanh cha A
BACK: MOV
A,#55H
;A=01010101B
MOV
P1,A
ACALL
DELAY
MOV
A,#0AAH
;A=10101010B
MOV
P1,A
ACALL
DELAY
SJMP
BACK
Xung & Hoi

22

 Cch 2: Xut d liu trc tip

BACK: MOV
P1,#55H
;P1=01010101B
ACALL
DELAY
MOV
P1,#0AAH ;P1=10101010B
ACALL
DELAY
SJMP
BACK
Cch 3: Dng lnh vi c im c-Sa i-Ghi
MOV
P1,#55H
;P1=01010101B
AGAIN: XRL
P1,#0FFH
ACALL
DELAY
SJMP
AGAIN

Xung & Hoi

23

8-5. Cc cng (port) cn li

P1, P2, P3 c in tr ti ni
P0 khng c in tr ti ni
Pha ngi lp trnh: khng c s khc bit no gia cc
cng
Tt c cc cng l output v mc logic cao khi Reset

Xung & Hoi

24

Cu trc phn cng P0.x

Read DFF

Bus ni

TB2

P0.X

P1.X
Write to DFF

Clk

M1

TB1
Read pin

Xung & Hoi

25

Port 0
Khi P0 c dng xut hay nhp d liu, phi c cc in tr
ko ln bn ngoi (10K hoc 4,7K)
V vi cc in tr ko ln bn ngoi ny, khi reset hay khi
bt ngun, P0 mc nh l output.
Vcc
10 K

Port

8051

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

Xung & Hoi

26

8-6. Vai tr kp ca P0
Khi ni 8051 ti b nh ngoi th n s dng cc port
gi a ch v c cc lnh
8051 c kh nng truy xut 64K bytes b nh ngoi
a ch 16-bit: P0 cung cp cc ng a ch A0-A7, P2
cung cp A8-A15
ng thi, P0 cung cp cc ng d liu D0-D7

Khi P0 c s dng a hp a ch/d liu, n c

kt ni ti 74LS373 cht a ch
Khi ny khng cn cc in tr ko ln bn ngoi

Xung & Hoi

27

8-6-1. B cht 74LS373

8051
A15 - A8

PORT2

ROM(S)
ADDRESS

ALE
PORT0

AD7 - AD0

LATCH
A7 - A0
D7 - D0

PSEN

ADDRESS
INPUTS
DATA
OUTPUTS
OE

Chn ALE c dng gii a hp (de-multiplexing) a ch

v d liu bng cch ni ti chn G ca b cht 74LS373
Khi ALE=0, P0 cung cp d liu D0-D7
Khi ALE=1, P0 cung cp a ch A0-A7
Xung & Hoi

28

PSEN
ALE
P0.0

OE

74LS373

G
D

P0.7

A0
A7
D0
D7

EA
P2.0

A8

P2.7

A15

8051

ROM
Xung & Hoi

29

State 1

State 2 State 3

State 4 State 5

State 6 State 1

State 2

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
XTAL2

ALE
_____
PSEN

P0

P2

PCL out

PCL out

PCL out

Data
sampled

Data
sampled

Data
sampled

PCH out

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PCH out

30

8-6-2. c ROM ngoi (1/2)

PSEN
ALE
P0.0

1. Gi a ch
ti ROM

2. 74373 cht a
ch & gi ti ROM
OE

74LS373

G
D

P0.7

A0
A7

Address
D0
D7

/EA
P2.0

A8

P2.7

A12

8051

Xung & Hoi

ROM

31

c ROM ngoi (2/2)

PSEN
ALE
P0.0
P0.7

2. 74373 cht a
ch & gi ti ROM

OE

74LS373

G
D

Address

A0
A7
D0
D7

/EA

3. ROM gi lnh
tr li
P2.0

A8

P2.7

A12

8051

Xung & Hoi

ROM

32

8-6-3. c ghi RAM ngoi

RAM(S) or
I/O

8051
DECODE

PORT 2
ALE
PORT 0

ADDRESS
LATCH

CE
ADDRESS
INPUTS
DATA
OUTPUTS
R/W
OE

WR
RD

Khng gian ti a 64KB. Truy xut a ch gin tip qua 2

thang ghi R0 v R1, con tr d liu.

Xung & Hoi

33

8-7. Port 3
Port 3 khng cn cc in tr ko ln bn ngoi
Mc du Port 3 cng c cu hnh nh ouput khi reset nhng
n thng dng cho cc chc nng ring nu di y

P3 Bit

Function Pin

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RxD
TxD
INT0
INT1
T0
T1
WR
RD
Xung & Hoi

10
11
12
13
14
15
16
17

34

Xung & Hoi

35