Professional Documents
Culture Documents
Mc lc
M u........................................................................................................................................1
Chng 1.....................................................................................................................................2
TNG QUAN V FPGA.........................................................................................................2
1.1 FPGA L G?.................................................................................................................2
1.2. LCH S RA I FPGA...............................................................................................3
1.3. NG DNG...................................................................................................................3
1.4. CU TRC MT FPGA...............................................................................................4
1.4.1 Khi logic FPGA......................................................................................................4
1.4.2 Cc phn t tch hp sn...........................................................................................5
1.4.3 Quy trnh thit k FPGA tng qut...........................................................................5
1.4.3.1 M t ban u v thit k...................................................................................6
1.4.3.2 Thc thi.............................................................................................................8
1.4.3.3 Qu trnh Np (download) v lp trnh (program)........................................10
1.5 TNG QUAN V VHDL..............................................................................................10
1.5.1 Gii thiu v ngn ng m t phn cng VHDL....................................................10
1.5.2 Cu trc mt m hnh h thng m t bng VHDL................................................12
1.5.2.1 Thc th (entity) ca m hnh .........................................................................12
1.5.2.2 Kin trc ca m hnh.....................................................................................13
TNG QUAN V OSCILLOSCOP........................................................................................14
2.1 . DAO NG K IN T...........................................................................................14
2.2 PHN LOI OSCILLOSCOP......................................................................................15
2.3 CU TRC CA OSCILLOSCOP IN T TNG T......................................16
2.3 CU TRC CA OSCILLOSCOP IN T S.......................................................17
CC BC THIT K MT OSCILLOSCOP S C NH...............................................22
3.1 CC THNH PHN TRONG THIT K...................................................................23
3.1.1.B nh.....................................................................................................................23
3.1.2 B bin i tng t - s ADC..............................................................................25
..........................................................................................................................................25
3.1.3 B khuch i m .................................................................................................27
3.1.4 iu khin logic......................................................................................................29
3.2 THIT K CHI TIT....................................................................................................32
3.2.1 Cu hnh np vo FPGA....................................................................................32
3.2.2 Ch tin trigger...................................................................................................33
3.2.3 D im trigger.......................................................................................................34
3.3.4 B to xung.............................................................................................................36
3.3.6 Giao din logic cng song song..............................................................................37
3.3.7 iu khin ADC .....................................................................................................38
Chng 4...................................................................................................................................39
CHNG TRNH V M PHNG TRN KIT DE2...........................................................39
4.1 TNG QUAN V KIT DE2 V CHIP CYCLONE II.................................................39
Nguyn Vn Thng K49B
ii
iii
CC T VIT TT
ADC
ASIC
CPLD
DAC
: Digital-to-Analog Converter
DRAM
DSO
DSP
E2
: EEPROM.
EEPROM
FIFO
FPGA
HDL
I/O
: Input/Output
LAB
LE
: logic Element.
LUT
: Look Up Table
MAC
PC
: Personal Computer
PLA
RAM
ROM
: Read-Only Memory
SPLD
SRAM
iv
VHDL
VHSIC
WCLK
: Write Clock.
WE
: Write Enable.
WRST
: Write Reset.
Li cm n
Li u tin em xin gi li cm n n ton th cc thy, c gio khoa in t Vin thng trng i hc Cng Ngh- HQG H Ni, nhng ngi tn tnh dy
d, ch bo em trong sut bn nm hc va qua ti nh trng.
Tip theo em xin gi li cm n su sc n TS Nguyn Thng Long v
CN Phan Vn Minh , nhng ngi trc tip hng dn em trong sut qu trnh hc
tp v nghin cu ti trng, cc thy truyn cho em cch t duy c h thng,
phng php nghin cu, tip cn thc t - nhng iu rt qu bu vi em khi ra
trng lm vic thc t.
Em xin cm n ti ton th cn b b mn Vi c in t - vi h thng nhng
ngi dn dt v nh hng nghin cu cho em trong sut hai nm qua.
Em xin gi li cm n ti Ths. Nguyn Kim Hng cng ton th cn b lm
vic trong phng cc h thng tch hp thng minh ch bo v to in kin cho
em trong sut qu trnh hc tp v nghin cu FPGA trong phng.
Em xin t lng bit n chn thnh ti cha m, gia nh em nhng ngi sinh
thnh, nui nng, tin tng ng vin em. Xin gi li cm n ti tt c bn b, c bit
l tp th lp K49B, nhng ngi c v, ng vin, chia s vi em trong sut
nhng nm qua.
H ni, ngy 27 thng 5 nm 2008
vi
M u
Dao ng k (Oscilloscop) l mt thit b o lng in t ph bin nht hin
nay, khng ging nh cc loi my o khc ch cho ta cc thng s ca tn hiu,
Oscilloscop cn cho php ta quan st tc thi dng ca tn hiu. Nhim v chnh ca
mt Oscilloscop l hin th mt cch tht chnh xc, chi tit dng tn hiu di dng
hm s ca in p v thi gian. Ngoi ra mt nhim v khng km phn quan trng
khc ca oscilloscop l so snh cc dng sng khc nhau v o lng mi quan h v
thi gian v pha gia chng.
C th ni qu trnh pht trin ca oscillscop gn lin vi qu trnh pht trin ca
k thut in t. M u l oscilloscop tng t, mt vi thp nin gn y l
oscilloscop s, gn y nht l mt s cng ty o lng hng u th gii va cho ra
i oscilloscop hn hp gia s v tng t c tnh hp vi cc tnh nng mnh m
nht tha hng t ngnh cng nghip my tnh.
Th k 21 l th k ca thng tin v k thut s vi s pht trin v ng dng rng
ri ca cc b vi x l. Bng vic a sc mnh k thut s vo thc tin, cc b vi x
l ngy mt thay i cch sng ca x hi loi ngi. Kha in t, my in thoi,
ni cm in..ca chng ta ang ngy mt thng minh hn, mnh m v nhanh nh
cc b vi x l. Tt c cc ngnh cng nghip ln nh: vin thng, iu khin cng
nghip, sn xut hng tiu dng u thc c v s dng trit cng ngh mi
v h cng vp phi nhng vn mi cn gii quyt l cc vn lin quan ti
tn hiu v iu khin s v tng t ca th gii thc. Oscilloscop vi vai tr l mt
thit b gim st, o kim phi p ng c cc yu cu ngy cng kht khe do cc
ngnh cng nghip ny t ra.
Vi mc ch l tm hiu v thit k mt oscilloscop s, kha lun ny trnh by
v phn tnh cu to, nguyn l hot ng ca cc loi oscilloscop, cc tnh nng tin
tin ca chng, c bit l cch thit k mt oscilloscop k thut s c nh dng chip
FPGA lm trung tm iu khin.
Chng 1
1.1 FPGA L G?
FPGA (Field-Programmable Gate Array) l vi mch dng cu trc mng phn t
logic m ngi dng c th lp trnh c. Vi mch FPGA c cu thnh t cc b
phn:
Cc khi logic c bn lp trnh c (logic block)
H thng mch lin kt lp trnh c
Khi vo/ra (IO Pads)
Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...
So snh FPGA vi ASIC v cc vi mch bn dn khc:
ASIC (Application-Specific Integrated Circuit) l mt vi mch IC c thit k
dnh cho mt ng dng c th.
FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng
nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin
logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong
kh nng thc hin nhng tc v c bit phc tp, tuy vy FPGA u vit hn ch
c th ti cu trc li khi ang s dng, cng on thit k n gin do vy chi ph
gim, rt ngn thi gian a sn phm vo s dng.
Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc
mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn cc im:
Kin trc ca FPGA cho php n c kh nng cha khi lng ln cng
logic (logic gate), so vi cc vi mch bn dn lp trnh c c trc n.
Hnh 5: S gn chn
Placing
Hnh 6: S khng gian gn bn trong FPGA
Routin
Hnh 7: S nh tuyn
Program
10
VHDL cho php thit k bng nhiu phng php v d phng php thit
k t trn xung, hay t di ln da vo cc th vin sn c. VHDL cng
h tr cho nhiu loi cng c xy dng mch nh s dng cng ngh
ng b hay khng ng b, s dng ma trn lp trnh c hay s
dng mng ngu nhin.
Th ba l tnh c lp vi cng ngh: VHDL hon ton c lp vi cng
11
12
13
Chng 2
2.1
. DAO NG K IN T
14
15
16
hn rt nhiu thi gian qut ngc trong mt chu k qut, di tn s qut, tc bin
i ca in p theo thi gian v hiu sut to bin in p qut.
Trn hnh v, khng ng thng l t s ca khong bin thin tc in
p qut trong thi gian qut thun (Tth) trn gi tr tc trung bnh:
dU
dU
) max (
) min
dT
y % = dT
dU
(
)tb
dT
(
% =
Uq
Eng
Tq = nTth ( Tth=
fth
17
18
Hnh di c phn khc hnh trn ch: B giao ng qut thc s l b bin
i DAC knh X, c iu khin t s liu ca Microprocessor. u ra b bin i
DAC to ra in p nhy bc, sao cho s nhy bc thang khng khc bit qu nhiu so
vi in p bc thang c to ra t b dao ng qut tng t.
Vi DAC loi 8 bit, s bc nhy l 28=256. Ton b on in p ra c chia
thnh 255 bc ring bit, v s lch ngang ca tia in t thc t l t l theo thi
gian. Tc bin i DAC v b iu khin qut quyt nh tc qut cc i, tc
qut c th iu khin bng vic thay i s n u vo s ca b DAC.
Cn t hp cc b pha trn gm: ADC, B nh, DAC ca knh Y cho php kh
nng thay i tr ca tn hiu vo ca h thng lm lch y trong mt gii hn rng,
19
20
----------------------------------
21
Chng 3
CC BC THIT K MT OSCILLOSCOP S C NH
22
bus, v vy n chn 1 trong 2 l thuc dng logic tng t hay logic dng s. Sau
d liu c a ln bus v c a vo b nh chnh lu tr d liu. Lgic iu
khin s ng thi theo di d liu quan st im trig. Cch tip cn ny loi tr
mch in b sung m bnh thng trig cn phi c, v thu hp ng tn hiu tng
t, do gim bt nhiu. iu ny cng cung cp kh nng gy nn tn hiu dng s
khi dng my phn tch logic. Ngoi tm im trig, logic iu khin cng thc hin
mi chc nng Glue logic v phng thc tin trig. Khi b nh y, d liu dng
ghi v c chuyn vo PC thng qua cng song song.
V 2 knh hon ton ring bit nn chng hot ng mt cch c lp. V d:
knh A l trong ch phn tch logic (logic analyser), knh B li trong ch
tng t (analogue). Hiu qu ca tc ly mu c th tng gp i bng cch kt
ni 2 u ra tng t vi nhau v i pha knh th 2 i 180 0. Sau khi d liu c a
vo PC, n c xen vo bi phn mm v dng sng c thit k li. Mc d tn
hiu c th 2 ln tn s thng, di ca bn ghi vn ko gim v c hai b nh
ang c dng lu tr dng sng n.
3.1 CC THNH PHN TRONG THIT K
3.1.1.B nh
T c im k thut ca DSO dng chip FPGA m ta thit k th b nh cn
nhng iu kin cn thit sau:
D liu bus rng 8bit.
C th cha 3Mbit.
Tc truyn d liu 40Mbytes/giy.
Cng c v ghi ring.
23
dng chnh trong cc ng dng video nh thi gian da trn s hiu chnh v hnh nh
trong phim. Chng l loi b nh hi t nhng yu cu ca ng dng ca ta .Bi v
n c cng sut cha ln, tc truyn d liu nhanh v cng c v ghi ring.
Hn na chng c hp nht mc cao, lm n gin vic thit k bn mch.
Sau khi nghin cu v tm hiu cc thit b c sn trn th trng Vit Nam th
em chn b nh ca hng Averlogic l AL422. N l mt b nh hnh nh v cng
ging nh hu ht cc b nh hnh nh khc, n c thit k v ch to da trn cng
ngh DRAM. Mc d bus d liu bn ngoi ch rng 8 Bit, phn ln b nh hnh nh
s dng bus bn trong c chiu rng hn. Iu ny lm tng tc hiu qu nh tnh
tng ng. Logic tc cao c dng chia tch bus bn trong thnh nhiu phn
8 bit,m sau ny n c t trn bus d liu u ra. Thm vo b iu khin
DRAM v address , n to ra logic c gi trong AL 422.V tr d liu c ghi vo
c nh vo mt thanh ghi a ch. Gi tr ca thanh ny c th l ln ln hoc v 0
(im bt u ca b nh). Tuy nhin n ko th c dch chuyn ti 1 v tr ngu
nhin no m phi c tng hay gim mt cch tun t v qu trnh ghi phi din
ra lin tc. Nhng b nh hnh nh chy ging nh nhng b m trong m khi thanh
ghi tin ti on cui ca b nh, n s t ng reset v im bt u v li bt u
ghi ln im c trc . Qu trnh c s dng thanh ghi c tng t. V th
nhng b nh hnh nh thng c gi l First In First Out Buffers (FIFO).
24
25
ADC c dng bin i dng sng tng t sang dng xung PAM. V bn cht
t nhin ring bit ca tn hiu s, dng sng tng t s c lng t ho n mc
tng ng s gn nht v chuyn thnh tn hiu s. S chuyn ADC cng ln th sai
s s lng t ho c a vo cng nh. Ta thy c rt nhiu loi ADC trn th
trng nhng tha mn nhng t c nhng yu cu v l do dng FPGA lm
b iu khin cho dao ng s c nh em tm hiu trn th trng th em thy
TDA8703 l ph hp nht.Bi v n c tc ly mu rt cao (c th t c tc
ti a l 140MHz). Tuy nhin ta cng c th thay th bi cc ADC khc c sn trn th
trng.
Phn ln ADC tc cao dng phng thc Flash Conversion, ci ny s dng
theo cc mng song song ca 2n-1 b so snh (n l phn gii ca ADC trong cc
bit). iu ny c ngha l c mi 8bit, my i in li yu cu 255 b so snh. Mc
phc tp ny khng ch lm tng chi ph m cn lm hn ch tc ti a m b
bin i c th hot ng. TDA8703 s dng phng thc Flash Conversion truyn
li, trong ADC ny th b bin i c chia tch thnh 7 cp vi mi cp dng 1
trnh chuyn i cc nhanh 2 bit. Chnh iu ny lm gim s b so snh c yu cu
xung cn 28 v y cng l mt u im ca b bin i ADC nhanh dng phng
thc bit i Flash Conversion. Mc d n a ra mt gc tr 7 chu k ng h gia
tn hiu tng t c a vo v d liu xut hin trn cc u ra. i vi chng
trnh ng dng ny th iu l c th chp nhn c.
26
3.1.3 B khuch i m
Khi tn hiu tng t c a vo m DSO ang hot ng ch xen k
gia tn hiu alnalog v logic analyser, th tn hiu tng t c a vo 2 ADC
thng qua mt b khuch i m. Khi b trung gian ny s va c chc nng lm
mt b khuch i tn hiu va c chc nng l mt b m tn hiu. C 2 chc nng
ny c th t c vi 1 b khuch i m ( y em dng Elantec EL4332C). Bi
v n tha mn nhng yu cu t ra ca thit k.
27
28
29
30
31
32
th lp trnh li chng trnh iu khin cho FPGA trong khi chng trnh c vn
trong bn mch v DSO vn ang hot ng. u vo c chn ti b hp knh
c y mnh bi 1K in tr v c kt ni ti ISP header. Khi ta np li chng
trnh vo E2 th khi chn c t ng ni t trong thi gian np li vo trong E2
v c y vo chip FPGA trong thi gian sau khi khi ng li. Vic ny lm
chuyn E2 t ch c kt ni ti Altera thnh c kt ni ti programmer. Sau khi
vic lp trnh hon tt, ngi s dng ch phi np li hay reset li DSO np li v
bo mch l c th s dng li DSO vi nhng tnh nng c cp nht d liu cu
hnh mi t chip b nh.
3.2.2 Ch tin trigger
Vic ghi d liu trc im trigger rt hu ch khi chng ta d li h thng. thc
hin vic ny bng cch ta cho DSO ghi nhng tn hiu lin tc i vo, tin trnh
ghi d liu ny c kt thc khi 1 xung (pulse) trigger c d thy trong h thng.
Ni dung d liu s c ghi vo b nh ti thi im trc ca im trigger c d
thy. Qu trnh ny c thc hin bng cch iu khin thi gian ca c hai tin trnh
d tm im trigger v khi s kt thc vic ghi d liu khi im trigger c d
thy trong tin trnh.
Vic ny c thc hin cng vi 1 b m (counter) 19bit l mt kha t tn
hiu mu ging nh FIFO, v vy khi gi tr ca counter bng ln a ch ca b
nh th vic ghi c dng li.Gi tr ca nhng sn trc trigger c th c thit
t bi pre-loading gi tr counter l mt gi tr gia 0 (khng tin trigger) v
393216 (c ca b nh v l ln nht ca pre-trigger). S 393216 l 0x60000 trong h
HEX, iu c ngha l s logic duy nht l 2bit u tin ca counter c dng
dng vic ghi.
D liu c bt u ghi ti bt k a ch no ca b nh m thang ghi a ch
tr ti nhng khi bt u ghi ti im ny ta phi ghi tun t k t . Khi thc hin
m tip counter 19bit ln th hai .N c s dng nhn dng qu trnh tip theo
v li bt u ghi vo b nh t a ch nh u tin, d liu s c ghi ln
nhng d liu c trong b nh trc . B counter c reset li ti cng mt thi
im ging nh im bt u ghi ti FIFO v chy t tn hiu ly mu u tin, v vy
gi tr c lu tr nu counter c gi tr nh hn khng gian ca b nh nu bng th
n s c reset v im bt u v sau l bt u im ghi li ti im u ca b
33
Bt u
ghi
Kt thc
Bt u
ca b
nh
Bt u
Start
im
trigger
Bt u
Gia
Trc khi sp xp
Kt thc
End
Gia
End
Kt thc
ca b
nh
End
Sau khi sp xp
Hnh 21: S sp xp ca b nh
3.2.3 D im trigger
Trigger unit l n v thc hin bn trong chip FPGA n c nhim v, gim st
c hai knh cho gi tr im trigger (ging nh hnh di y) . Tt c nhng s t
c lu tr l ln hn, bng hay nh hn gi tr ca mi thanh ghi n m bo rng
mi thanh ghi khng b trn khi lu tr. Bng cch thay i gi tr ca mi thanh ghi
c ngi s dng c th thay i mc ca trigger. Di y l bng chn l
thc hin mi trigger unit
34
N c th xut hin khi mt sn trigger. Gii php cho vic ny l xung clock
phi ng b d li v vy u ra t trigger unit c chn l mu duy nht khi d liu
trn bus.Chng ta thc hin bng cch t mt trigger D ngay ti u ra ca
mch trigger ng b xung nhp h thng ny v thu c mt tn hiu ra l ng
b..
Trng thi cui cng trong n v d im trigger chuyn i cp trigger di
hn bnh thng bng trng thi u tin trong sn trigger.Cng vic hon thnh
bng cch duy nht l chuyn tip 1 nu ng trigger c gi tr 0, v vy m u ra
duy nht mc cao khi trong c s truyn t thp ti cao v xut hin sn. Bng
35
cch thit t ti trig-sel bus ti 0x3 c ngi s dng khng cho php trigger v
bt u qu trnh ghi trc tip.
3.3.4 B to xung
Vic to ra xung clock rt hu ch bi n c th thay i tn s ly mu, cho
php ngi s dng ti vic chuyn i di qu trnh ghi li tn s ly mu. Trong
h thng chnh xung clock cung cp bi tn s 50MHz TTL ca my to xung, n
c dng bng tinh th thch anh. l c cu hnh bn trong chip FPGA ni n
c chi tn. y ta c th chia tn theo bng cch dung mt b m counter 5bit
khi ta s thu c tn s mi c t l l l ,1/4,1/8,1/26,1/32 so vi tn s h
thng.Chng ta s dng mt b hp knh chn tn s thch hp cho xung clock ca
DSO, ta c th thy trng hnh.
cung cp cng tn s ly mu cho hai knh ta phi cung cp cho chng lch
nhau 1800 m bo c tn hiu ly mu tt, v vy ta c th dng mt mch not
cung cp cho mt thanh ghi dch.
Rt nhiu thit b trong FPGA v c hai FIFOs cn truyn d liu ti PC v vy
thc hin iu ny ta cn s dng bus ba trng thi(tri-state bus), n c biu din
di hnh sau:
Cng song
song
FPGA
FIFO A
FIFO B
36
ca n thp hn cng song song m y chng ta dng cng song song giao tip
vi my tnh. Ging nh l chip m cc chn ca n cng c th thay i d dng nu
n b h.
Bus ba trng thi gia ADCs v m logic th c kt ni cng c nhng tnh
cht iu khin nh bus ca cng song song, trong u ra mt ADC v m logic ti
mt bus m c hai FPGA v FIFO cng kim sot.
37
38
Chng 4
Hnh 24: S khi ghp ni gia Cyclone II vi cc thnh phn trn KIT
39
element). Mi LE (Logic Element) c th c cu hnh thnh mt FipFlop D,T,JK hay RS. Mi mt thnh phn ny cng c cc u v l data,
clock, enable,clear v u ra cng l data. Chng cung c th cu hnh
thnh cc thnh phn c bn khc trong mi ng dng. chng cng c th
40
41
42
N c ng gi vi 672 chn.
Chng trnh c th c np trc tip t phn mm QUATUS II xung chp qua
mt cp USB.
Ngoi ra trong KIT ny cn c rt nhiu ti nguyn na nh:
C 512 KB SRAM trong c 256 KB a ch v c th cha d liu
vi di 16 bit.
C 8MB b nh SDRAM trong trong c th c ti 1 MB a ch
v c th cha d liu ln ti 16 bt v c 4 banks tt c.
C 8MB b nh Flash v c th cha d liu c rng bt ti a l
8bits
Ni chung trn KIT ny thc hnh nghin cu v pht tin th rt hu ch.
43
44
Hnh trn l s m phng dng xung khi thc hin chy m phng trn phn
mm Quatus II da trn device l chip Cyclone II.
Trong cc tn hin clk l tn hiu clock a vo b chia tn, control l tn hiu
u vo c dng iu khin logic cng song song, EXT_TRG l tn hiu a vo
iu khin ng b, cc tn hiu LOGIC_INPUTH, LOGIC_INPUTL l cc ng
vo ca ng logic m. Cc tn hiu ra cn li l cc tn hiu iu khin vic chn
knh.
45
46
47
48
4.2.4 Chng trnh to dng xung chia theo t l 1/2, 1/4, 1/8, 1/16, 1/32
49
50
51
Kt lun
Vi kt qu ny, em bc u xy dng mt b iu khin s dng trong my
dao ng s c nh da trn cng ngh FPGA. c bit qua qu trnh nghin cu v
thc hin ti em tch lu c nhiu kin thc b ch:
Bc u nm c kin thc c bn v FPGA v ngn ng m t phn
cng VHDL.
Hiu c nguyn tc hot ng v cu to ca mt my dao ng s c
hiu cch np v chy mt chng trnh trn kit pht trin DE2.
Hiu c t tng ca lung thit k trn cng ngh FPGA.
Xy dng cho bn thn mnh tnh k lut v cch hc tp nghin cu
khoa hc, cch t duy h thng khi thc hin mt ti.
Nhng iu cn hn ch v hng pht trin ca ti.
Do thi gian thc hin ti c hn nn em mi ch lm c b iu
52
PH LC
-----Chng trnh chnh iu khin DSO
library ieee;
use ieee.std_logic_1164.all;
entity main is
port(
clk
:IN
CONTROL
STD_LOGIC;
:IN
LOGIC_INPUTL
:IN
LOGIC_INPUTH
:IN
EXT_TRIG
:IN
STATUE
:OUT
FIFO_A_W_CLK
:OUT
STD_LOGIC;
FIFO_B_W_CLK
:OUT
STD_LOGIC;
FIFO_W_EN
:OUT
STD_LOGIC;
FIFO_W_RST
STD_LOGIC;
STD_LOGIC_VECTOR(4 DOWNTO 0);
:OUT
STD_LOGIC;
FIFO_A_OE
:OUT
STD_LOGIC;
FIFO_B_OE
:OUT
STD_LOGIC;
FIFO_R_CLK
:OUT
STD_LOGIC;
FIFO_R_RST
:OUT
STD_LOGIC;
BUF_DIr
:OUT
STD_LOGIC;
AB_CHANEL_MEGA :OUT
STD_LOGIC;
LOGIC_BUT_H_OE
:OUT
STD_LOGIC;
ADC_B_OE
:OUT
STD_LOGIC;
LOGIC_BUT_L_OE
:OUT
STD_LOGIC;
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ADC_A_OE
DATA
:OUT
:INOUT
STD_LOGIC;
STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;
ARCHITECTURE CHON OF MAIN IS
signal poit1
: std_logic;
component giaotiep
port (
dieukhien
:in
poit
:in
std_logic_vector(18downto 0);
data
data_output
pre_trig_load
trig_sel
trig_load
clkdiv
buf_dir
:out std_logic;
fifo_r_clk
:out std_logic;
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rec_en
:out std_logic;
init
:out std_logic;
fifo_r_rst
:out std_logic;
fifo_a_oe
:out std_logic;
fifo_b_oe
:out std_logic;
high_speed
:out std_logic;
fifo_a_logic
:out std_logic;
trig_falling
:out std_logic;
fifo_b_logic
:out std_logic
);
End component
COMPONENT coltron_fifo
port(
trig
trig_load
:in
:in
trigger
:in
std_logic;
rec_en
:in
std_logic;
init
:in
std_logic;
clk
:in
std_logic;
mem_full
:out
std_logic;
fifo_w_en
:out std_logic;
fifo_w_rst
:out std_logic;
fifo_w_clk
:out std_logic;
poit
);
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END COMPONENT;
---------COMPONENT trigger_unit
port (
trig_load
:in
trig_value
:in
:in
std_logic;
fifo_a_logic
:in
std_logic;
fifo_b_logic
:in
std_logic;
high_speed
:in
std_logic;
ext_trigger
:in
std_logic;
clk
:in
std_logic;
rec_en
:in
std_logic;
trig_sel
:in
std_logic_vector(1downto 0);
trigger_output
:out std_logic
);
END COMPONENT;
-------COMPONENT xungnhip
port (
CLOCK_50,clear
sel
Nguyn Vn Thng K49B
:in
std_logic;
clk
:out std_logic
);
END COMPONENT;
--------begin
t1:giaotiep
port map
(control(3downto0),
57
end chon;
58
port (
dieukhien
:in
poit
:in
std_logic_vector(18downto 0);
data
data_output
pre_trig_load
trig_sel
trig_load
clkdiv
buf_dir
:out std_logic;
fifo_r_clk
:out std_logic;
rec_en
:out std_logic;
init
:out std_logic;
fifo_r_rst
:out std_logic;
fifo_a_oe
:out std_logic;
fifo_b_oe
:out std_logic;
high_speed
:out std_logic;
fifo_a_logic
:out std_logic;
trig_falling
:out
fifo_b_logic
:out std_logic
std_logic;
);
end ;
architecture chon of giaotiep is
signal
outmux,outtribus,q1,q2,q3,q4:std_logic_vector(7downto 0);
signal t1:std_logic_vector(1 downto 0);
signal a1,a2,a3,a4,a5,a6,a7:std_logic;
signal out1:std_logic_vector(2 downto 0);
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59
-------------component hopkenh
port(
a,b,c
:in
sel
:in
:out
std_logic_vector(7 downto 0)
);
end component;
----------component giaima
PORT
(
data
eq1
: OUT STD_LOGIC ;
eq2
: OUT STD_LOGIC ;
eq3
: OUT STD_LOGIC ;
eq4
: OUT STD_LOGIC ;
eq5
: OUT STD_LOGIC ;
eq6
: OUT STD_LOGIC ;
eq7
: OUT STD_LOGIC
);
end component;
----------component reg3
port (
a
en
:in
:IN
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std_logic;
);
end component;
----------
component reg
port (
en
:in
std_logic;
:in
);
end component;
-----------------component tri3
port (
a
:in
en
:in
:inout std_logic_vector(7downto 0)
std_logic;
);
end component;
---------begin
mux1:
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gm:
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data <=outtribus;
fifo_r_clk<=a1;
end chon;
-------Chng trnh iu khin FIFO
library ieee;
use ieee.std_logic_1164.all;
entity coltron_fifo is
port(
trig
:in
trig_load
:in
trigger
:in
std_logic;
rec_en
:in
std_logic;
init
:in
std_logic;
clk
:in
std_logic;
mem_full
:out
std_logic;
fifo_w_en
:out
std_logic;
fifo_w_rst
:out
std_logic;
fifo_w_clk
:out
std_logic;
poit
);
end;
architecture chon of coltron_fifo is
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63
:in
clk
:in
counter_en
load
:in
:in
mem_full
std_logic;
std_logic;
std_logic
);
end component;
-----------component counter19
PORT
(
clock
: IN STD_LOGIC ;
cnt_en
: IN STD_LOGIC ;
sset
: IN STD_LOGIC ;
);
end component;
-----------begin
t4<=(trigger and rec_en) or(rec_en and t3);
t2<=t4 and (not t1);
t3<=(a(17)
and
a(17)) or (init);
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t1;
fifo_w_rst<=not init;
fifo_w_clk<=clk;
end chon;
-----Chng trnh b to xung
library ieee;
use ieee.std_logic_1164.all;
entity xungnhip is
port (
CLOCK_50,clear :
sel
:
clk
in
in
std_logic;
std_logic
);
end xungnhip;
architecture chon of xungnhip is
signal div0,div1,div2,div3,div4
signal clk1,clk2,clk4,clk8,clk16,clk32
std_logic;
std_logic;
:
:in
std_logic;
65
);
end component;
------hop kenh------component hopkenhtaoxung
port (
clk1,clk2,clk4,clk8,clk16,clk32
sel
in
clock_out
:in
std_logic;
std_logic
);
end component;
begin
t1:taoxung
port map(CLOCK_50,'1',div0,div1,div2,div3,div4);
t2:hopkenhtaoxung
port map(CLOCK_50,div0,div1,div2,div3,div4,
sel(2 downto 0),clk);
end chon;
:in
trig_value
:in
logic_inputL
:in
logic_inputH
:in
trig_falling
Nguyn Vn Thng K49B
:in
std_logic;
66
fifo_a_logic
:in
std_logic;
fifo_b_logic
:in
std_logic;
high_speed
:in
std_logic;
ext_trigger
:in
std_logic;
clk
:in
rec_en
std_logic;
:in
trig_sel
:in
trigger_output
std_logic;
std_logic_vector(1 downto 0);
:out
std_logic
);
end;
architecture chon of trigger_unit is
signal chotout1,chotout2:std_logic_vector(7 downto 0);
signal a1,a2,a3,b1,b2,b3,q11,q12,q13,q14,q2,q3,s:std_logic;
signal outmux21,outmux22,outmux3,outtrigD:std_logic;
-------------component mux2
port(
a,b
:in
std_logic;
sel
:in
:out std_logic
a,b,c
:in
std_logic;
);
end component;
-------component mux3
port(
sel
Nguyn Vn Thng K49B
:in
std_logic;
:out std_logic
);
end component;
------component reg
port (
en
:in
std_logic;
:in
);
end component;
------component trigD
port (
a
:in
clk,clear :in
q
:out
std_logic;
std_logic;
std_logic
);
end component;
------component sosanh
PORT
(
dataa
:IN
datab
:IN
STD_LOGIC_VECTOR(7 DOWNTO
AeB
: OUT STD_LOGIC ;
AgB
: OUT STD_LOGIC ;
68
);
end component;
-------begin
chot1
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and
s)or(trig_sel(0)and
end chon;
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