BERBER EERE EERE ERR E EEE EE Produced By: Commodore International Spare Parts GmbH Braunschweig, West Germany SERVICE MANUAL A500 PLUS INCLUDES A501 PLUS RAM EXPANDER OCTOBER, 1991 PN-400420-01 INTERNATIONAL EDITION SERVICE POLICY AND PART NUMBER INFORMATION MAY VARY ACCORDING TO COUNTRY. SOME PARTS MAY NOT BE AVAILABLE IN ALL COUNTRIES. Commodore Business Machines, Inc. 1200 Wilson Drive, West Chester, Pennsylvania 19380 U.S.A. ‘Commodore makes no express or implied warranties with regard to the information contained herein. The infor- ‘mation is made available solely on an asis basis, and the entire risk as to completeness, reliability, and accuracy is with the user. Commodore shall not be liable for any damages in connection with the use of the information contained herein. The listing of any available replacement part herein does not constitute in any case a recommenda tion, warranty or guaranty as to quality or suitability of such replacement part. Reproduction or use without ex- press permission, of editorial or pictorial content, in any ‘matter is prohibited. ‘This manual contains copyrighted and proprietary information. No part Of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, copying, recording or otherwise, without the prior written permission ‘of Commodore Electronics Limited, Copyright © 1991 by Commodore Electronics Limited. Al rights reserved. Printed in U.S.A. Reprinted with permission of North American Philips1 SGC a &. A500 PLUS SERVICE MANUAL TABLE OF CONTEN' SECTION 1 — SPECIFICATIONS ‘S00 PLUS SPECIFICATIONS. ASO1 PLUS SPECIFICATIONS. ret 12 SECTION 2 — THEORY OF OPERATIONS AMIGA 500 PLUS MEMORY MAP. 2 S00 PLUS BLOCK DIAGRAM 22 THEORY OF OPERATION. con 23 8375 AGNUS 2MEG S : —s : : 27 8373 DENISE HI RES. : coon 2a 8364 PAULA.......-. coco S fe 22 GARY. ..sssssssessesesseseesreerseeeneegrenenserscnineertesenssent i SECTION 3 — TROUBLESHOOTING MAIN ASSEMBLY DIAGRAM. Bl SECTION 4 — PARTS ‘AS00 PLUS PCB ASSEMBLY 312812........20:202008+ eeceeeroe 4d AS00 PLUS SHIPPING ASSEMBLIES 5 eoouood 42 A500 PLUS MAJOR ASSEMBLIES. coed 43 AS00 PLUS PCB COMPONENTS. . poceocuandocsoct eoonnogc 44 AS01 PLUS SHIPPING ASSEMBLIES —— 45 ‘A501 PLUS MAJOR ASSEMBLIES. 46 S01 PLUS PCB COMPONENTS. . 47 SECTION § — SCHEMATICS ‘A$00 PLUS SCHEMATIC #312813, REV. 1 51 ASO1 PLUS SCHEMATIC #363835, REV. 0. Sell cm +A500 PLUS SERVICE MANUAL A500 PLUS SPECIFICATIONS INTRODUCTION ‘The A500 Plus is a feature enhanced version of the A500 personal computer. FEATURES CPU: 7.16 MHz 68000 NTSC; 7.09 MHz 68000 PAL ‘Memory: 1 Megabyte standard expandable to 2 MB with addition of ASO! Plus Kickstart ROM: 512K (V2.04) ‘Mass Storage Memory: Internal, 3.5 inch FDD mounted on the right side, the same as the ASO0. Additional Features: Real Time Clock (on-board) with battery backup. APPEARANCE ‘The A500 Plus appearance shall be the same as the A500. A new logo plate has been added to distinguish “‘ASO0” from ‘AS00 Plus”. The color is the same light beige as the current ASO0. WHAT'S ADDED : 1 Meg on-board memory expandable to 2 Meg. 8375 FAT AGNUS which supports 2 Meg. of Chip RAM On-board Real Time Clock 8373 ECS Denise Full ECS support 2.04 in ROM CUSTOM CHIPS ‘The A500 Plus shall contain the same custom chip set as the ASO0, except for the 8375 2Meg. FAT AGNUS and 8373 ECS Denise. SYSTEM 1/0 EXTERNAL SYSTEM 1/0 External floppy, Serial, Parallel, Mouse, Joystick, Stereo Audio Ports ‘These Ports remain unchanged from their AS0O counterparts. MEMORY MAP ‘The A500 Plus Memory Map is the same as the AS0O Memory Map.A500 PLUS SERVICE MANUAL A501 PLUS SPECIFICATIONS DESCRIPTION ‘The ASO1 Plus is a memory expansion board for the Amiga $00 Plus personal computer. It has 1 MB of “‘chip"” memory. and interfaces directly to the A500 Plus memory expansion slot. Unlike the A501, the A501 Plus doesn’t have a Real Time Clock (RTC), the AS00 Plus has a built-in RTC. ‘The ASOI can be used in either the ASO0 or A500 Plus personal computer, has 512K of memory and includes a Real ‘Time Clock. The A500 maps the ASOI into pseudo-fast memory while the ASO0 Plus maps it into chip memory. In addition, when used in an AS0O Plus system, the internal (built-in) RTC is selected. Both the ASO1 and ASO1 Plus uses the same printed circuit board (PCB). In the A501 Plus, the RTC and refresh feature components are not loaded. MEMORY TYPE ‘The ASO1 Plus shall use 256K x 4 120ns DRAMs. PIN DESCRIPTIONS PIN SIGNAL : PIN NAME NUMBER DIRECTION _ DESCRIPTION +5 12,5182 +5 Volts GND 3-4, 21-22, Signal Ground 53-54 XDRD (0-15) 5-20 vo Memory Data Bus XDRA (0-8) 23-31 1 Memory Address Bus /EXTICK 32 ° ‘Active low. When this signal is asserted, it allows the AS00to detect the presence of an ASO1. The AS01 Plus does not use this signal, XCLKS 3 1 ‘Active low. When this signal is asserted, the external RTC is selected. This signal is not used in the ASO1 Plus. /XOE 34 1 ‘Active low. When this signal is asserted, data can be read from the expansion memory. /XCASL 35 1 ‘Active low. This signal strobes the column address into DRAMS and corresponds to the low byte of the data word, /XCASU 36 1 Active low. This signal strobes the column address into the DRAMs and corresponds to the high byte of the data word. /XRASI 37 1 Active low. This signal strobes the row address into the DRAMS and corresponds to the upper 512K of the expansion RAM. /XRASO 38 1 Active low. This signal strobes the row address into the DRAMs and corresponds to the lower 512K of the expansion RAM. /XWE 39 1 Active low. When this signal is asserted, data is written into the expansion memory. NC 40, 56 Not connected. XD 03) 41-44 vo RTC Data bus. These lines are not used in the ASO1 Plus XA (2-5) 45-48 1 RTC Address Bus. These lines are not used in the ASO1 Plus. /XCLKRD 49 1 ‘Active low. When this signal is asserted, data can be read from the RTC. This signal is not used in the ASO1 Plus. /XCLEWR 50 1 Active low. This signal strobes the data and address into the RTC. This signal is not used in the ASOI Plus. +1V 55 1 +12 Volts. This is used on the ASOI to charge the battery. This line is not used on the ASO1 Plus.A500 PLUS SERVICE MANUAL A501 PLUS SPECIFICATIONS (Continued) FACTORY DEFAULT JUMPER SETTINGS ASOL ASOI Plus Jumper SPI SP2A, JP2B JP3 JP9 DIMENSIONS Length: width: POWER +5VDC +12VDC ENVIRONMENT IPL JP2A IPB JP3 Py. 1-2 shorted 1-2 open 1-2 open 1-2 shorted 1-2 open 2.3 shorted 23 shorted 1-2 shorted 1-1 open, 2-2 open 1.2 shorted 1-2 shorted 1-2 shorted 1-2 shorted 1-2 open 2-3 open 23 open 1-2 shorted 1-1 open. 2:2 open, Function ‘When 1-2 are shorted, /EXTICK detection is enabled. This jumper has no effect on the ASOI Plus, because it does not use /EXTICK detection. When 2-3 are shorted (I-2 open), it enables the refresh feature in the ASO1. Refresh components U11-U13 must be loaded in the A$01. The refresh feature is only required on the ASO1 to compen- sate for refresh deficiencies in older revs of the A$00. ‘Swaps upper and lower bank DRAMs. When 1-2 are shorted (1-1 and 2-2 open), /XRASO and ZXRASI selects the lower and upper banks respectively. Conversely, when 1-1 and 2-2 are shorted, /XRASO selects the upper bank while /XRASI selects the lower bank RAMs. Overwrites /XCLKS, When 1-2 are shorted, /XCLKS is permanently enabled and the ASOI (exter- nal) RTC is always selected. This jumper is normally open. Selection of internal or external RTC is done by the A500 or A500 Plus via the /XCLKS line. RTC components U9, UlI-U13, C9, C1I-C13, C911, C913, R9L1-R91S, D11-D9123, BT9, TC9 and Y9 must be loaded in the ASOL. 3.5 in, 3.5 in. @330 mA MAX for ASO1 Plus @280 mA MAX for ASOL @15 mA MAX for ASOL Not Used on ASO1 Plus Operating Temperature 0 to +55°C Humidity Up to 90% without condensationAMIGA 500 PLUS MEMORY MAP OVERLAY ——_— ZZ o 100 ss20 ere000 BF0000 ar expansion | 2000, veel EAL TIME CLOCK Bee (OPTIONAL) L. (CROSS=RESERVED DISPLAY RAM EXPANSION EXPANSION A500 PLUS SERVICE MANUAL 512K 2MEG 8 MEG 2MEG 2MEG 12 MEG 12 MEG 1/2MEG s12K 172MEG ee 23 WVUDVIC XOOTE SNTd 00SV a 5 g = on 8 ae Wa z a (91) sng weg 3 < rE ‘wooed 7 ali po seeded na 2/38 aie aa Ly wea wenby nwo Ul oe a suse we viva 3siNaq ava envoy Auvo ea tome (=e ¥ 7 J fi 32019, ain’. ssappy meg vou 1 [crsean o3am] i ‘arte wo 01 én) Sm i ®sanocese Soa wOtouveea | we ae 2 pieEBERREREEDCEE ST & | ane A500 PLUS SERVICE MANUAL THEORY OF OPERATION The AMIGA $00 Plus computer is a high-performance system with advanced graphics and audio features. The prin- cipal hardware features consist of the 68000 microprocessor which runs at 7.2 MHz, IMB RAM, expandable to 2MB, and configurable to 8MB, 2 parallel I/O chips, one control chip (GARY) and 3 custom VLSI chips that provide the unique capabilities for animation, graphics and sound. 68000 MICROPROCESSOR ‘The 68000 is the CPU of the system. All other resources are under software control via control data issued from it. All 3 custom chips have control registers that are written by the 68000. ‘The 68000 communicates with the rest of the computer via its address bus, data bus and control lines. Notice that in the block diagram the 3 custom chips do not reside directly on the 68000 buses. When the 68000 starts a bus cycle that is intended for the custom chips or the display RAM, the bus control chip detects whether or not the display RAM buses are available. The control chip will not assert the acknowledge signal (/DTACK) back to the 68000 ur the display RAM buses are available. Once the 68000 receives /DTACK it completes the bus cycle. Connecting the display RAM buses to the 68000 buses is discussed further in the section on bus control. Because the display RAM is capable of approximately twice the bandwidth of the 68000, the 68000 is usually not delayed by waiting for the display buses to become available. ‘The 68000 can fetch instructions from: Display RAM ROM ‘The 68000 can read and write data directly to: Display RAM Parallel I/O Chips 3 Custom 1.C.s ROM ‘The 68000 transmits data and control to and from the peripherals via the parallel 1/O and the 3 custom chips. ‘7M is the processor clock to the 68000. C1, C3 and CDAC are used to clock the custom chips and determine the timing of signals to the memory arrays. ROM ‘The ROM contains the kernel and DOS routines; it is 128K x 16. PARALLEL 1/0 ‘The 2 multipurpose 8520 1/0 chips provide the following: 1/0 to and from the parallel port connector Control lines to and from the joystick/mouse ports A control line to the front panel LED Internal control lines Keyboard control lines, clock and data Serial port control lines Floppy disk interface control lines Internal timers ‘These 2 chips reside on the 68000 buses and are read and written by the 68000.A500 PLUS SERVICE MANUAL THEORY OF OPERATION (Continued) CPU SIGNAL SUMMARY So 2 $4 $8 $0 $2 6 Su Ov Ou Su Su Su Sw Su Su 50 58 0 $2 SL Su Su Su ON Sy SBF 3D nvazs 1s ws tos 99 r at reo2 X xe x a “of Normal cycle fe — — ~ ~~68000 Peripheral Read Cyc ‘Machine Cycle Signa Name Macmonie fnpu/Output_— Active State Tre State dies us AAS uu th Yes Daa Bs pedis pwvOupt High Ye Aes Srobe 78 Output tow Yes ead Wee ww oun EH Upper and Lower Data Strobes ‘UDS, LDS ‘Output Low Yes Data Transfer Acknowledge DTACK Input Low No. Bus Request BR Input Low No ‘Bus Grant BG Output Low No Bus Grant Acknowledge BGACK Input Low No Interrupt Priority Level IPLO, IPLT, IPLZ Input Low No Bus Error BERR Input Low No Reset RESET Input/Output Low No* Halt HALT Input/Output Low No* Enable E Output fun (No Valid Memory Address VMA ‘Output Low Yes Valid Peripheral Address VPA Input Low No Fonction Code Out Fon, FCI FC2 Outpt Hin Ye Clk ck taut High No Powe input vee tet = Ground Gxp tnt a 2 ternal to 68000 *0pen Drain Ao 24A500 PLUS SERVICE MANUAL THEORY OF OPERATION (Continued) . CLOCKS GENERATOR The entire computer board is run synchronously to the 3.$79S4Mhz color clock (C1). This is accomplished by generating a number of sub-multiple frequencies from our master 28.63636Mhz crystal oscillator. The following are the primary locks on the board: Name Description ca ‘The 3.57954SMhz Color Clock ce CI shifted 45 degrees later C3 CI shifted 90 degrees later 4 CI shifted 135 degrees later ™ C1 XORed with C3* (7.15909Mhz) Dac 7M shifted 90 degrees later 7M is the processor clock for the 68000 microprocessor. C1-C4 and DAC are used to clock the custom chips and for determining the timing of signals to the memory arrays. ‘The above frequencies are true for NTSC Amigas. A PAL Amiga will operate slightly slower, with a main clock of 28.37516Mhz. This is divided down to get 7M = 7.09379Mhz and Cl = 3.54689SMhz. A special circuit is required to take five fourths of Cl to derive the PAL colorburst frequency of 4.43361875Mhz. ‘The following clocks are available at the edge connector: Pin Description 14 C3 inverted 15 DAC equivalent 16 Cl inverted Note that 7M (the processor clock) is not available at the connector; it can be easily generated by: C3* XNOR CI* = 7M equivalent If you need a 14.31818Mhz synchronous clock, you can generate it by: (7Mequiv) XOR (CDAC) = 14M equivalent 1M ™ SynedS2 139s ——>| coac L al IstQrtl = cs ce oe Amiga System ClocksA500 PLUS SERVICE MANUAL THEORY OF OPERATION (Continued) THE 3 CUSTOM CHIPS ‘The 3 custom chips provide very fast manipulation of graphics and audio data in the display RAM. Alll the major functions in the chips are DMA driven; that is, streams of data are moved between the custom chips and display RAM under DMA control. These streams of data are acted upon by the custom chips. Fat Agnus, custom chip #1, contains 25 dedicated purpose DMA counters. The 3 chips have control registers which are usually loaded by the 68000. However, Fat Agnus also has the capability of loading control registers in the other 2 custom chips. When Fat Agnus performs a bus cycle, it outputs a code on the Register Address Bus telling the other 2 chips the nature of the bus cycle. This is necessary because many of the bus cycles provide data to or from the other 2 chips, thus they must cooperate appropriately. In addition to manipulating data in the display RAM, the custom chips output streams of data to the video output circuits and audio output circuits, and they move data to and from the floppy disks and serial port. Note that the display RAM buses can be completely isolated from the 68000 buses by Fat Agnus and Data Bus drivers. ‘Thus, Fat Agnus can be performing a bus cycle on the display buses simultaneously with the 68000 performing a bus cycle on its buses. This parallelism increases throughout. BUS CONTROL, ADDRESS/DATA MUX, ADDRESS DRIVER ‘The bus control logic resides in the control chip (GARY) and Fat Agnus. They provide 3 major functions, they: ‘Synchronize the 68000 to the current phase of C1 Arbitrate between the 68000 and Fat Agnus for the display buses Generate DRAM timing for the video RAM bus drivers appropriate to the current cycle ‘Synchronizing the 68000 to C1 is straightforward, since the 68000 is clocked by 7M which is twice the frequency and synchronous to Cl. If the 68000 starts @ bus cycle in the wrong phase of C1, the bus control chip merely delays /DTACK ong enough so that the 68000 will complete the bus cycle in the desired phase relationship to Cl. This phase relation- ship is necessary because the custom chips and the display RAM are clocked by Cl. Arbitration is very simple. Fat Agnus tells the bus control prior to taking the display RAM buses by asserting an input to the control chip (GARY) called /DBR. Whenever Fat Agnus has the display buses and the 68000 wants them, the £68000 is held off by not giving it /DTACK. In this state the 68000 has no effect on the display buses until the bus ‘controller enables the bus drivers. Fat Agnus generates the DRAM timings and does all address multiplexing. If the 68000 is running a video memory cycle, its addresses are routed through Fat Agnus onto the multiplexed address lines. If the custom chips are running ‘a memory cycle the addresses are routed to the multiplexed address lines from internal address register. DISPLAY RAM The display RAM is a 512K read/write memory that resides on the RAM address and RAM data buses. Its expandable to IM bytes by the addition of the RAM expansion module. It is implemented using standard 256K x 1 dynamic RAMs, refreshed by Fat Agnus. ‘The display RAM is really used for much more than just holding graphics data. It also stores code and data for the 68000. CUSTOM CONTROL CHIPS ‘The Amiga’s animation, graphics and sound are produced by three custom chips. Fat Agnus (8375), High Res Denise (8373) and Paula (8364). A fourth custom chip, Gary serves as the control chip. The following pages include feature lists, and block diagrams for these chips.A500 PLUS SERVICE MANUAL 8375 AGNUS 2MEG GENERAL This device is an address generator type IC. Its main function is as a RAM address generator and register address encoder that shall produce all DMA addresses for 25 channels. ‘The block diagram for this device shows the DMA control and address bus logic. The output of each controller in- dicates the number of DMA channels driving the Register Address Encoder and RAM Address Generator. ‘The RAM Address Generator contains an 20 bit pointer register for each of the 25 DMA channels and also it contains er restart (backup) registers and jump registers for six (6) of the channels. A full 20 bit adder carries out the pointer increments and adds for jumps. ‘The priority control logic looks at the pipe-lined DMA request from each controller and stages the DMA cycles based upon their programmed priority and sync counter time slot. Then it signals the processor to get off the bus by asserting, the DBR line. The following is a brief description of the device's major operational modes. A control register determines which 256 possible logic operations is to be performed as the source images are combined. ‘and how far they are to be moved (Barrel shifted). In addition to the image combining and movement powers, the Blitter can be programmed to do line drawing or area fill between ei A tr (ite ser ct 1 sci Agnus 8375 Block Diagram BLITTER ‘The procedure for moving and combining bit mapped images in memory received the name Bit Blit from a computer instruction that did block transfers of data on bit boundaries. These routines became known as Bit Blitters or Blitters. The Blitter DMA Controller is preloaded with the address and size of three (3) source images (A,B, and C) and one (1) destination (D) in the dynamic RAM. These images can be as small as a single character or as large as twice the screen size, They can be full images or smaller windows of a larger image. The actual pixel resolution is controlled by the BLTSIZE (BLTSIZH and BLTSIZV) registers which contain up to 15 bits for the image height (15 bits = 32K dots max.) and up to 11 bits for the image width (11 bits = 2k words = 32K pixels max.). After one word of each source image is sequentially loaded into the source buffer (A, B, C) they are shifted and then combined together in the logic unit to perform image movement overlay, masking, and replacements. The result is captured in the destination, buffer (D) and sent back to the RAM memory destination address. This operation is repeated until the complete image has been processed. The unit has extensive pipelining to allow for shifter and logic unit propagation time, while the next set of source words is being fetched. 27A500 PLUS SERVICE MANUAL 8375 AGNUS (Continued) BITPLANE ADDRESSING ‘Some computer bitmap displays are organized so that the bitplanes for each pixel are all located within the same ad- dress. This is called pixel addressing. If the entire data word of one address is used for a single pixel with 8 bit planes, the data word will look like this. (numbers are bitplanes): 12345678—- ‘The data compression can be improved by packing more than one pixel into a single address like this: 1234567812345678 oo like this, if there are only 4 bitplanes: 1234123412341234 ‘The IC device, uses a bitmap technique called Bitplane Addressing. This separates the bitplanes in memory. To create a 4 plane (16 color) image, the bitplane display DMA channels fetch from 4 separate areas of memory like this: MN 2222222222222222 3333333333333333 aaaaaaaaaaaaaad ‘These are held in buffer register and are used together as pixels, one bit at a time, by the display (left to right) This technique allows reduced odd numbers of bitplanes (such as 3 or 5) while maintaining packing efficiency and speed. It also allows grouping bitplanes into 2 separate images, each with independent hardware high speed image manipulation, line draw, and area fill. DMA CHANNEL FUNCTIONS Each channel has an 20 bit RAM address pointer that is placed on the MA memory address bus, and is used to select the location of the DMA data transfer from anywhere in IM words (2M bytes) of RAM. ‘An eight (8) bit destination address is simultaneously placed on the register address bus (RGA), sending the data to the corresponding register. In a typical DMA channel, almost all channels have DRAM as source and chip registers as destination. ‘The pointer must be preloaded and is automatically incremented cach time a data transfer occurs. Each controller utilizes one or more of these DMA channels for its own purposes. The following is a brief summary of these controllers and the DMA channels they use. A-Blitter (four (4) channels) ‘The Blitter uses four (4) DMA channels, Three source and one (1) destination as previously described. Once the Blitter has been started, the four (4) DMA channels are synchronized and pipelined to automatically handle the data transfers without further processor intervention. The images manipulated in memory, independent of the display (bitplane DMA). -Bitplane (six (6) channels) The bitplane controller continuously (during display) transfers display data from memory to display buffer registers. ‘There are six (6) DMA channels to handle the data from six (6) independent bit planes. The buffers convert this bitplane data into pixel data for the display. C-Copper (one (1) channel) ‘The Copper is a co-processor that uses one of the DMA channels to fetch its instructions. The DMA pointer is the instruction counter and must be preloaded with the starting address of the Copper’s instructions. The Copper can move (write) data into chip registers. It can skip, jump, and wait (halt). These simple instructions ‘give great power and flexibility because of the following features. ‘When Copper is halted, itis off the data bus, using no bus cycles until the wait is over. The programmed wait value is ‘compared to a counter that keeps track of the TV beam position (beam counter) and when they are equal, the Copper will resume fetching instructions. It can cause interrupts, reload the color registers, start the Blitter or service the audio. It can modify almost any register inside or outside the IC device, based on the TV screen coordinates given by the Beam Counter and the actual address encoded on the RGA Bus. 28naan ee ee A500 PLUS SERVICE MANUAL 8375 AGNUS (Continued) DMA CHANNEL FUNCTIONS (Continued) D-Audio (four (4) channels) There are four (4) audio channels, all of which are located outside of the audio DMA Controller section of Agnus. Each controller is independent and uses one DMA channel from the DMA Controller and fetches its data during a dedicated timing slot within horizontal blanking. This is accomplished by a controller asserting the DMAL input on the DMA Controller. E-Sprites (eight (8) channels) ‘There are eight (8) independent S for DMA data transfer. Sprites are hardware registers and comparators. Each sprite has two (2) sixteen bit data registers that define a 16 pixel wide Sprite with 4 colors. Each has a horizontal position register, a vertical start position register and a vertical stop position register. This allows variable vertical size sprites. ‘The Sprite DMA controller fetches image and position data automatically from anywhere in 2 Megabytes of memory depending on device pin configuration. Sprites can be run automatically in DMA mode or they can be loaded and controlled by the microprocessor. Each Sprite can be re-used vertically as often as desired. Horizontal re-using is also allowed with microprocessor control. controllers, each with its own DMA channel and its own dedicated time slot e buffered objects that can move very fast because their positions are controlled F-Disk (one (1) channel) The disk controller, which is located outside of the DMA, uses a single DMA channel from the device. The controller uses the DMA time slot for data transfer and can read or write a block of data up to 128K anywhere in 2 Megabytes of memory depending on device pin configuration. G-Memory Refresh (one (1) channel) The refresh controller uses a single DMA channel with its own time slots. It places RAS addresses on the memory address bus (MA) during these slots, in order to refresh the dynamic RAM. Memory is refreshed on every raster line. During the DMA no data transfer actually takes place. The register address bus (RGA) is used to supply video syn- chronizing codes. At this time RASI* and RAS are low. CASU* and CASLY* are inactive during this cycle. RAM AND REGISTER ADDRESSING ‘The device generates RAM addresses from two sources, the processor or the device performing DMA cycles. The pro- cessor accesses RAM whenever AS* and RAMEN® are both low. At this time, the device also multiplexes the pro- cessor address (A1-A20) onto the MA bus. During row address time A9-A17 and A19 are placed onto MA0-MA8, ‘MAS, respectively; during column address time A1-A8, A18 and A20 are placed onto MA0-MA7, MA8 and MA9, respectively. In the 1 meg configuration, A19 is still used to determine the RAS line to be asserted. If A19 is low RASO* is active and if high RASI* is active. In the 2 meg option RAS will always be active on a RAM access. The IC will assert CASL* if LDS* is low or CASU* if UDS* is low. When the device needs to do a DMA cycle, the device disables the processor from accessing RAM by asserting the Data Bus Request Line (DBR*). At this time, the device multiplexes its generated RAM address onto the MA lines and will activate RAS and the proper RASO* or RASI* line unless it is a refresh cycle where all RAS lines are active. During a DMA cycle, the IC device will also assert both CASU* and CASL*, unless it is a refresh eycle where they both remain inactive. ‘The device also generates RGA addresses from either the processor or device DMAs, each of which is selected by an internal multiplexer. This multiplexer allows the processor to perform a register read/write access when AS* and RGEN* are both low. The device then takes the low order byte of the processor address Al to AB and reflects its value on the RGA output bus RGAI to RGA8. The device will reflect the status of PRW input on the RRW output line, to indicate a memory read or write operation. During a device DMA cycle, the device prevents the processor from doing a register access by asserting the DBR* line. The device will then place the contents of its register address encoder onto the RGA bus. 29 BER RERE ERR ERE EE EEE SE SG SEA500 PLUS SERVICE MANUAL 8375 AGNUS (Continued) amie. ieee ae, a eK Fe riz \ a yi ! Lf Clock Relations CLOCK RELATIONS (Refer to Figure above) SYMBOL MIN MAX UNIT 2.4.1 28MHz clock cycle 128MC 34.57 35.27 ns 2.4.2 28MHz clock high (28MHi 12.0 2.9 ns 2.4.3 28MHz clock low 128MLo 12.0 2.9 ns 2.4.4 CCK clock cycle teye 260 290 ns 2.4.5 CCK clock high tech 130 150 ns 2.8.6 CCK clock low tel 130 150 ns 2.4.7 CCK-CCKQ clock separation teq 65 15 ns 2.4.8 TMHz clock cycle 17MC 130 150 ns 2.4.9 TMHz clock high 17MHi 65 8 ns 2.4.10 MHz clock low 17MLo 65 8 as 2.4.11 TMHz-CDACQ clock separation t7MQ 30 40 ns 2.4.12 CCK to 7MHz delay tc7™M 0 15 ns 2.4.13 CCKQ to TMHz delay tq7M. 0 15 ns 2.4.14 Clock rise time a 0 10 ns 2.4.15 Clock fall time wf 0 10 as 210A500 PLUS SERVICE MANUAL 8373 DENISE HI RES MAIN FUNCTIONS ** Display data buffer, encode display object to RGB colors. * Bitplane & Sprite display. Parallel data from data bus is retained in six (6) Bitplane and eight pairs of Sprite data buffers. * Bitplane Data loaded and serialized during display activity. « Sprite Data loaded during display inactivity — individual serialization occurs when Sprite position Compare logic detects equality between the Syne Counter and any Sprite Position Register. * Six (6 lines of Bitplane & eight (8) pairs of serial data go to Priority control logic which selects only one (1) of the Sprites or one (1) of the separate Bitmap images to produce the five (5) bit color select code at its output. This five (6) bit code then selects one of the thirty-two (32) color registers to produce the twelve (12) bit RGB video output. ‘The Bitplane and Sprite serial lines also go to the Collision Detect Logic, which detects real time coincidence between them, and sets appropriate bits in the Collision Storage register. This register is read and cleared by the 68000. * The four (4) “mouse counters” are controlled by the two (2) mouse joystick connectors. These count the pulses representing the horizontal and vertical motion of two (2) “mouse” controllers, and are read by the 68000. CHIP ELEMENTS 32 Color Registers; Bitplane Priority and Control Registers; Color Select Decoder; Priority Control Logic; 16 Sprite Serial Lines; Sprite Data Registers; Bit Plane Controt Registers; Two (2) Mouse Connectors; Sprite Position Compare Logic; Sprite Horizontal Control Registers; Bit Plane Serializer Collision Detect Logic; Collision Control Register; Collision Storage Register; Buffer — Data Bus; Buffer — Register Address Decode; Bit Plane Data Registers Video: RGB; Sprite Serialization. av COLLISION PRIORITY. COLOR |_ 32 ‘ ar ggomny Tel Sart fay cada [> e0 LOGIC Losi DECODE_ REGISTERS 8 ‘ ) (2) CELOOH Sean] a Poe CouTROL eesrion || ‘Pron eae owpane || a covrmo. toate || heaisrens eae (_RERISTERS SERIALIZE ‘SPRITE DATA — | REGISTERS Ld Bir PLANE 6) 8 SERIAL TauLoW OT PARE] (BIT PLANE car |)” SPRITE STORAGE ata reaisren || ‘Cormac won || one AcaSTER ‘6 REGSTER catt, || postion # ecisrens_|| | | DB lg | | {| | | fe 5 on sm i rca [gl ape le REGISTER ADDRESS DECODE ] Denise Block Diagram auA500 PLUS SERVICE MANUAL 8364 PAULA Paula is the Port, Audio and Uart chip. Its main function is the four audio channels. It also contains the I/O ports, (Disk and Pots), Serial Port (Uart), and the Interrupt Control and Status Register. D TO A CONVERTERS ‘The four audio channels each have a DMA pointer register, data register, period, (frequency), register and volume register. Each channel has an on chip D to A (digital to analog) converter on the output. The four channels are grouped into a right and left audio output. DISK CONTROL The disk controller has registers for data read, data write and control. It also contains a Precompensation Output circuit, a Data separator input circuit with a digital phase lock loop. UART CONTROL ‘The serial port uart included in Paula contains Data registers, Control registers, Transmit, (TRN), and receive registers. POT CONTROL ‘The four pot ports are general purpose I/O ports. They have counters for simple A to D (digital to analog) conversion of an external capacitor charging, which could also be used for analog joystick controllers. INTERRUPT CONTROL ‘The audio, disk and uart controllers all set their own Interrupt Status register bits. DMA REQUEST LOGIC ‘The audio and disk controllers also go to the DMA request logic, (remember: they are DMA users), causing the DMAL_ signal to request DMA cycles from Agnus. tt ft ‘Audio. ‘Audio Disk UART POT ee . ‘ ttt = be ae ; re oe fcr in a oa Ta = cen |) ee sy oa ca sewn = oo, | | oe, im ma fs ise e— a = on = = = -4 apes [eee (eon a ge —— ene epee i oe 2 7 aie : : RB Register Adress Decode 8 Paula Block DiagramGARY CUSTOM CONTROL CHIP FEATURES + Provides all bus control signals. + Provides all address decoding. © Generates the 68000 VPA signal. © Handles some of the floppy circuitry. Provides keyboard reset interface. For signal descriptions, ‘see Schematic #312813, sheet 1 of 10 GARY BLOCK DIAGRAM 68000 Addresses 6 ‘Address Strobe (AS) ups, LDS Clocks Gey Override (OVR) ‘Overlay (OVL) Processor read write (PRW) Expansion Board Present (EXPEN) DER XRDY Override (OVR) A500 PLUS SERVICE MANUAL ‘KBRESET 4 vect | MIR - DKWE 4 pKwo Tos ups } ves E sare E \irron + DkwoB b DKwEB, DTACK LAUT bast f cnps baz F a2 21 woh A20 fais ubais BEAN a2} EXRAM aif xepy 30F ove, 2b OVE 2ef cc af ccxg ast cDac. 2s LATCH us GARY KReset Keyboard Reset. ———*} RAM Enable (RAME) RGA Enable (RGAE) ROM Enable (ROME) Real time clock read and write (RTCR, RTCW) VPA CDR | Bidirectional CDW tistate latch tatcu } cont TACK as 243ZBegeqgegegeog#»@n@gmttrtimttakt wean aS a THE [FART wo esoRITON + | s2a6or | sorrow case 2 | iezasen | toe saeco 5 | drsoea | tor seo 2 | ease | too sueco,ewoo 0 § | asmear | msucanon sveer 3 | sooo | sorrow sme 3 | Sraspear | ois omve assevany. cnn fo | Samzor | Pea asses aso 1US, REV. 8, Pa 13 | Samace | Pea assem son PLUS, REV 8, WSC 43 | sanasor | Rr swe.o exaision 47 | Siasmeor | Reveoaso ASseNeLy, usu te | same | RevBDARo ASSEMBLY, WAY 19 | Simas | kevooano aSseneLy. Fae 20 | Siastzos | Kevaoano ASSEMBLY’ SOP 21 | aston | KEveoano ASSEMBLY” SP | Sietaor | NEvaoano ASSEMBLY” OW 2 | sto | Nevaoano ASSEMBLY. SEV 24 | Santen | Revaoano Assen. 3 | Sastooe | Kevanano assenaty. 1 a | doste | Kevaoaso asoevay UAL 2 | Stosoege | revaoano assevely, BLANK | secs | stowrasr sravooer 36 | Seoraear | Screw, roroue, ws sve sree S| Semen | Screw: Mevac us 8.0 SELF TAPPING 3 | povrzon | Shape Temunal, mace | swans | Loox washer. Scena room 34 _| Ssoasce | Some Toma, 5 = 30.6 Stee CONNECT TO CN13. CONNECT TO CN1t (CONNECT TO CN12 [i>TISTIE ATAWASSV 9d SNTd 0OSV = A500 PLUS SERVICE MANUALA500 PLUS SERVICE MANUAL Commodore International Spare Parts List A500 PLUS SHIPPING ASSEMBLIES ‘Commodore part numbers are provided fr reference only and donot inccate the availabilty of spare parts from Commodore. Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to country, some parts may ‘ot be avaiable in al countries. Part Numbers are subject to change, see Parts (Section 2) of current Techtopcs for current numbers. [Sarna ASST Ata PLUS SHIPPING ASS A PLUS ert sont Jus. 3150001 [SOFWARE SUE ASSY Us sss. |on iss | SOFWARE 0 ASSY CX sass as | oc stsec | SOFWARE S08 ASSY UK aso | ise ot | SOrWARE SB ASSY GR sso: |e issu |SOrWaRE Sus assy FR sso |i ise | Sortwane Sua Assy 7 ase |e Sissasor | SOrWARE Sue ASSY Se sass as | 86 sissboe [SOFWARE Sus ASSY 56 sso | sts600 | SorWaRE Sus assy SF 850810 [AU (or useo) Stsae 10 | SOFWARE Sus ASSY WR ssue |e sis | SOFWARE SUB ASSY SO sous 12 | 50 Bisa 12 | SOFWARE SUB ASSY sone 13 | Sis 13 | SOFWARE SUB ASSY NE sue |e Sia | SOFTWARE SUB ASSY ON Essone's | Sisaae 15 | SornWane 506 assy 3 ssone 6 [BF saab 16 | SOFWARE SUB ASSY AL ase” |B wor useD) isa | SOFTWARE SUB ASSY PS ssone ie [aL res |auex connect FoR. 0 sou8 18 [CEL wor useoy arson. | mTROOUGING THE Asoo enus sasoue20 | aes. | NTACOUGING THE AsO GERMAN S100 02 [ax MASTER StePIG £50 PLUS (UB FR S198) aeeso 2 | MTRODUCIS THE ASD FR 5rses 0 | ax PACS AUD PLUS amas | nTROOUGINS THE Asoo Sez 01 | Man assy usion sess |emoouci THE As00 SP 6202 | MAN ASS GRAD augseot | vTROOUGINS THE AStO NR 6208 | MAN ASSY FLBE seco. | vTmooUciS THE AE00 SW e204 | MAN ASSY SOPH 3230. | NTROOUGING THE ASOD Fos 3602.08 | MAN ASSY SP suaot ot | rmoouciNs THE Asoo DUTCH sets | MAN ASSY OW S320 | OoUGINS THE A500 DASH seca | MAN ASS Sev Sees |IeTROOUGIG THE AS00 PORTUCUESE eset | MA ASSY NR 20980 | aux conc GUIDE ASO GERUAN 362.08 | MAN ASS NEAL ssso0 01 [utc connect GUE Asoo FR 38360210 | MAN ASSY UK See [oc CONNECT GUIDE ASO ITALIAN asec [a ASST 5360101 |outc connect GUE aso sexu ais6e12 [AN ASSY 76 Seea01 [utc CONNECT GLIDE Asoo NORWEGIAN ce 95 | MAN ASS AN KEYBOARD bees [ic CONNECT GUIDE Asoo sweDisn asroasaa | Povaae ax stanc Besa [ie GoNnecr SDE Asoo usa zcsr at [axe ORYIG ace Besar [oie connect SuDe Asoo outa ies | Enea Lert Sete 01 fick CONT GUIDE Asoo Dawe rasan |nbear AGT Seco [dick CONT GUIDE Asoo PORTUGUESE Sioe8 3 [MLL Bose Wr Fou 312s |powes suPeLy ULCSA 10V si2sasaz | powen suPeLy st 2407 srasasaa|poweR sueety voe 200 Srasut|poweR SUPPLY Sev 220) stasusas | POWER SUPPLY Sx 2200 Harem | wouse assr Ssoeast | ee 25 PM SCART TO 23 PW 0 SUB WR FOR TV Con sreasce |e vate Season | a eo8RD Segoe | Sea. TAMPER EvbeNT PLACE ON BOK FLAPS) sreq7 [Last HaNOLe seaoeo | ADHESIVE TAPE TRANSPARENT Sow (ON MASTER SHIP BOK FLAPS) sour. [ox ACCESSORY S70 | sacen caRDeae seer | Set Tomorrow s2ase% | seer Soe oss |rowen PLUG Fuseo Ux. 42A500 PLUS SERVICE MANUAL Commodore International Spare Parts List S00 PLUS MAJOR ASSEMBLIES Commodore part numbers are provided for reference only and do nt indicate the avaiability of spre parts from Commodore. Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally, Part number information may vary according to country, some parts may ‘ot be avaiable in all countries ASS 0 PLS 801 eseet2 ees eet eas Eary eeiear eeo8 208 e210 cat ese 1 6229 12061 soesbat Sst ozaseo1 see sao srsae soe so Sra Hew aoxeot srsteot rosea roses srasoe ross Siosne08 si2saear siesta sizsazon rasa. izs0298 sraeeat sacs at cost) sesaae Sores Sarr ese 03 Boso0 02 stro seo 1 Pare surge eases Sigs ot sist rose seit sso esto) econ ese ese ese iso 8 seo? Sse 08 sieeeot estuo02 sear 0+ eet 08 eet 10 23a o+ ous ot Een Wan ASSY FSG PLUS US EROR Wan ASSy AS09 PLUS GERMANVALSTAR lua ASS ASCO PLUS FRANCEIBELGRAK aus sv aS09 PLUS SWEDEN ass Assy AS00 PLUS SPAS. AMERICA fans assy as09 PLUS Dems aes ASS AS PLLS STZERL AND ano sy as00 PLUS NORWAY un ASS aso PLUS NETHER ANOS aa ASS aso PLUS Uk aad ASS a5t0 PLUS ALY Man ASS aSO0 PLUS PORTUGAL Ma ASSYASIO PLUS BLANK FEYBOARO PAL BOTTOM CASE {or Sep op SHEL (ue ror sissy sesso.) oe seo ao0o Lp (USE Was288-) MSULATION SHEET porrow SMeLD gk DAVE ASSY CANON Dg OVE ASSY PARASONC SUB FOR 31258401) PCB ASSY AS00 PLUS REV 8 PAL Poa ASS ASO PLUS EV 8 NTSC RF siELD Expasion REYBDSRO ASSY U.S cAN Revbasno ASS GUA Revenamo ASS Re Revooaro ASS I evens Assy SomN REYBDSAO ASSY SP REVBDRRD ASSY ON REvaDARO ASSY SEV REveDARO ASSY NR evaoano ASSY Uc REvaOAnO ASSY BL revaoano Supromt cRPcsT STANOrE uckPOsr STAIDOF Sue fom soes-o icRPosT STANOOF SUB oR Ses.) SoREW TORODE #51576 LG STEEL (CTY 4)USE ON TOP SMELO& RF SRW TOROUE 6 X76 UG (58 FOR 200145.) SEREW PAN HEAD 29 x 8 SELF TAPPNG (8 FO S016) SCREW META MS X80 SELF TAPPING (OT 4 ~ USE WISI259401) SPADE TERMINAL MALE Lock WASHER EXTERNAL TOOTH SCREW TORQUE 45 3 LG STEEL (TY 6 — USE Wrar2s6an) SOREW TOROUE 5 X38 LG (Sus FOR soo.) SoREW PAN vA 291 9:5 SELP TAPPING (08 FR 3801642) Rat exPansion 008 over CxPnsion op case RawEPLATE wen Fer LABEL RATING PAL ADE WEAN LABEL RATING NTSC MADE ni GEARY LABEL RATING PAL ADE USA) SUB FOR 3668101 EL RATING NTSC (WADE USA) SUB FOR 9584-0) LABEL RATING PAL MADE IN HONG KONG) ABEL RATING NTS MADE HONG ONG) EL RATING PAL (MADE IN PHILP) ABEL RATING NTS MADE IN PHELPS) LABEL WARNING POWER OF STINER SEAL WARRANTY SPRING FINGER TABEL RATING PAL QUADE Wo LABEL RAT NTSC (MADE TNH abe LAR Las 208 Cove Lan LABEL 65 CODE BLANK sissa01 ise 02 Sisco isos sis03805, 51508 08 sis 31500808 ise i510 Sis8-1 saa? sis isa sis 5 saae 8 aa? ezacot ereiso1 serait sees sie seve. ot Sar601 aca CONSUMER A CONSUMER SOFWARE SU ASSEML Y CANADA aul CONSUMER SOFTWARE SUB ASSEMBLY Ux acs CONSUMER SOFTWARE SB ASEM GEFMAINY al CONSUMER SOFTWARE SUB ASSEMBLY FANE auc CONSUMER SOFTWARE Su ASSEMBLY MALY au CONSUMER SOFTWARE SUB ASSEMBLY SPAN Mi CONSUMER SOFTWARE SU8 ASSEMBLY SWITZERLANO-GERMAN AM GONGUMER SOFWARE S08 ASSEMBLY SWITZERLAND ENA ste CONSUMER SOFTWARE SU ASSEMBLY NORWAY AMIGA CONSUMER SOFTWARE SUB ASSEMBLY SWEDEN Ml CONSUMER SOFTWARE SUB ASSEMBLY FINLAND ANNA CONSUMER SOFTWARE SUB ASSEMELY NETHERLANOS MGA CONSUMER SOFTWARE SUB ASSEWBLY DEAMARH AMA CONSUMER SOFTWARE SUB ASSEMBLY BELGMRENCH sua CONSUMER SOFTWARE SUB ASEMELY AUSTRALIA a CONSUMER SOFTWARE SUB ASSEMBLY PORTUGAL aaa USING THE AMIGA WORKBENCH ENGLISH Disk ASSY WORKBENCH 24 U's. (TERNATIONAL) 35° Sk ASSY WORKBINCH 204 CANADA FRENCH 35° DSK ASSY WORKBENCH 204 UK. 35" DSK ASSY WORKBENCH 2.04 GERMAN 35° DSK ASSY WORKDC NCH 2.04 FRENCHBELGIUM 3.5° DSK ASSY WORKBENCH 2:4 ALAN 3.5” Sk ASSY WORKBENCH 2.4 SPANISH 35° DSK ASSY WORBENCH 2.4 SWS 35° Sk ASSY WORKBENCH 2 4 NORNEIAN 3 = Sk ASSY WORKBENCH 2 4 SWEDSUFIINSH 35° DSK ASSY WORKAENON 2.4 DANS 35" DSK ASSY EXTRAS 2.04 NTERWATONAL 35° DSK ASSY FONTS 204 TERNATIONAL 35° DswerteFo.nER 35 SOFTWARE UCENSE AGREEMENT ENGUSH SOFTWARE LOENSE AGREEMENT GERMAN OLY BAG CATCH 20 70M ence SU8 ASSY A500 SERIES. AAD WARRANTY CANADA AR WaReasTy Ux EA WaeeasTy GesMaNy CARD WaeaNTY FACE CARD WARRANTY SWITZERLANO CARD WARRANTY AUSTRALIA CaR0 OS REPLACEMENT Us Ean 1S PLACEMENT CANADA wana USING THE AMIGA WORKGENCH FRENC WenLAC USING THE AMIGA WORKBENCH ALAN wenLAL USING THE AMIGA WORKBENCH GER FasL USING THE AMIGA WORKBENCH SASH axWAL USING THE AMIGA WORKBENCH ORNSH MANUAL US THE AMIGA WoRRBENCH DUTCH MANUAL US TE AMA WORKBENCH HORWEGAN MRMUAC USING THE AMIGA WORKBENCH SWEDISH 43A500 PLUS SERVICE MANUAL Commodore International Spare Parts List 500 PLUS PCB Components PCB Assembly #312812 (-01 — PAL; -02 — NTSC) ‘commodore pat numbers are provided for relerene oly and do not indicate te avaiailty of spare prs tom Commodore. Indus standard pars (Restor, ‘pacts, Connectors) should be secured lcaly Pat humberinfxmatan ay vary according Yo oun, some parts may not bearable nal counts. SPN EAPAETORE en over cia a SIO LE AL TR OE eae TCS ois cts to Sins ce cst mom feces smo | er vi Sts |e uate eae svc es be rcs |i seat xm ener Sone etn & a i toast lice ust me een Staoreo oe ara sy ts ans [esc aia tow so ee ce Seer (at a asta 200 8 Bano [ees ain a3 «700 ez cae zeny (os st a & rode [eee ayo tne ov irae enter |yos as Aas 2 HE Pa fa Boros [eee alia ad ze emcees Sete [4s ars Ads 2 wes nc te ros [eee alin ao 6 2 ocr tac | S20 NA Sk tue sts [ees cv aa 9 FS eso tes [rau tie ee sui2ot |e ss oro [oF rT Stowe ua aac as urs ze oo. since Joa eek x «ob um ron oy | ues orsos8 onan en oe ca sapoat loarie is sso for 1c rove nae, Sueno |r ts fone a aaa Steet | eo weno int eas er, Soa: [os Bs NSE HES te orsozz [or ms oer [Paster ts orga Jr a oe over pasate trou ousons Joram, be soe [ruse ote az 2 [ras ne sorsnss [car On cs rors siz st|rase sz oss |e Ot asa Sst [Os Sra Ne ES ie eee ee aes ie soos sosose [or ra asia oa [OPN ae ovens [crs ome fm Sousa [oc n or tr sovsoes cis ora ange Semasot [s¢ on ce te sovsnea [cr zr om rove erreot| us on sus sss [eax om npr sient, stro. |B ue Fon oy sie roger suns |< pk ie sso 35 ct rea EOOIETOS RESETS = stieat [REA BER WE ADD ea xia oF on ow a ezieas [rc eek veo Cero eo sev [or eto eo zine |r eck Bac A es sow (of ome rn Start | Re HE METAL 8 on zzrz01 a 20 | cacao sor [of 47 ae a ce ears [fm te ore ee sa (cf $1 om ue on sy a a a zseou [pm opr rowenta ory eu) ee ee asset [ near owner wien hor. | ot 7 5 Sonor | eaten 3 om Wn fe Fx 6m {Om uz [oot SF TOPE EE ea ras Sacre seaen 2 nue ae otc [Ps iro |e oat SP ora SE ez Sarct o'ie paren oa oF Ht” [es sez |p oaiSe OPM SEE |e sacoe-ot | Sus 25 pn FEMALE coz CEWTRONICS) | CW” sz 0 22 al SF AOE ELE SUB FORO) | Reate Secor |b sie arm wale trp ooston [ou.cxe sgznoa |i SP em EEN Pet so pee Stews [oss soPuact oece wos” (ow smace |o ue Mae Oe eo, |e ssi [sro Se ewer reise sist [8p ak wn evant) ens MSSELANEOUS SSO TOESETERS hi Do ara | ATER MED TOT aT 8 SGLLATONS. THNSITORS AAD ORS mr sien |e FLIER 00 PF srusrossvese cent ae sz [roan ow esr | fers ren cm sec enean oocso.t | abe nets pears ose oe Scie [One ars um ro axasoon ——fosovosiione | [ers ea TR so eg ease Pieueas [osouston rv we on) fe se = Sort [em FLTER 409 ene et cas eu mes loscuston wee wee wns {t icra wera i mre csene ES earns ca em eR 0 ov evnsan ca sii | MM SETF_G7F re on ee ema [wana 20 or Eesciocrcrsexe Et esresen ci | [astsace [ane rusen i ferscaooesn” | [3eieor [nt eo ows Fate soz |e en. 25 6 ens Sse [rene eto Co ue rom acraan [tne Sins | ME eal 25 SF Evzacscrocw | [sess |rnmte Seb one romain | an ewecencance cy, | [zen | eae SED OAL Perec Etccaosees cam | [ooo | rene Beto ask sus rn arson eoeas eas fenrcacaor | | mesos [at sun coe sta anata san. so 2 evi eres |e an cone aa Sere a ana ho Ease oe meter 44Commodore International Spare Parts List A501 PLUS SHIPPING ASSEMBLIES A500 PLUS SERVICE MANUAL ‘Commodore part numbers are provided for reference only and do not indicate the availabilty of spare parts from Commodore. Industry standard parts (Resistors, Capacitors, Connectors) should be secured locally. Part umber information may vary according to country, some parts may ‘ot be avaiable in all countries, Part Numbers are subject to change, see Parts (Section 2) of current Techtopcs for current numbers. Sr ABBY As PL Sie ASST Ast PLUS (anne sso 01 sett 200604 Sverre sean SASSY AS PLS TERRAIN MA assy ASO PLUS 4G STAT Bx STATIC (sus FOR 24106-0) LEAT STRUCTION 326020] TRAY 80K e009 |x MONOUAL Sean 0 | Sea. TAMPER EvbeNT Steno |x MASTER SHPPING 14 see ¢ = = 45SEQ GREET EEE agagad & & A500 PLUS SERVICE MANUAL Commodore International Spare Parts List A501 PLUS MAJOR ASSEMBLIES ‘Commodore pat numbers ae provided for reference only and donot indicate the availabilty of spare parts from Commodore. Industry standard pars (Resistors, Capacitors, Connectors) should be secured locally. Part number information may vary according to county, some parts may not be avalible in all countries. See Section 3 for Disassembly diagrams. A ASS a PLS MRT ASST PLUS oe) 20007 MAN ASSY FUT PLUS ras [oe seo tase | aor seo stort | mguATON SHEET 5260601 ent set 65480 TAPE PRESSURE SENSTIVE PCS ASSEMBLY 801 PLUS, Tage ann coDe LAN 05° x 175° LABEL BAR CODE BLANK OX 1.00"ot be avaiable in all counties. A500 PLUS SERVICE MANUAL PCB Assembly #363834 Commodore International Spare Parts List A501 PLUS PCB Components ‘Commodore part numbers are provided for reference only and do not indicate the avalilty of spare parts from Commodore. Industry standard parts (Resistors, Capacitors, Connectors) should be secured local. Part number information may vary according to county, some parts may COMPONENTS RESISTOR WETWORRS 51900 04 [Ona 256 X4 TRS Tra sor 05 [os Of SP 10 PS LEMENT rd stance [aa 25k x4 dons (sus For sta. [UT MSCELLANEDUS onMEcTORS aso ]LABEL BAR CODE BLAME D5" 1TS™ 201105 [EMAL READER PANEL iz 335009 |LAaeL ax CODE BLAME 05" 100° eapacrons 00K | MCE ANAL ou OF eae sono. 02 | Lec ALUM RAD TOQUE 16 cinco BEERERER ERE REE ER ERE ERE ELE 47Schematic #312813, Rev. 1 4 Sheet 1 of 10 JUMPERS AND STUFF er _|TYPE _|DESCRIPTION pace fe EL “RE YEQHRORESET T Ic LE, cove, 02 SQOREES oe mi fPsrne eee Seven [aa Breas: PrcayTE DECODER IBLOR—IEXPONS [DNZTIER OPTION Bee vow foet eecee | ipLog—IGK-A08RD ATC BYPASS — BLoeIeepae agin 1/8 urout lacoa TT "70_CORP_SYNt SIGNAL GLOSSARY : tor [eT Pea iPHeRal ENABLE CLOCK ExTick EANSION PRESENT /-Rit FCLe:T ETREGAL AE aUTToN-O71 rice ———} SLT PRATES oR BaOCt StH HOeTeoRT AC ear CV Hinges Tinga Pu setae é Finite-a-61 Eau ies1— Forest] Tia Bes 5 Heitor Tn eaT0R [ Tesua — rates —p KSDATE RETAMUa BRIA TRE TaaRE) — KARESET BORED Rt ESET (Re YaORROy rupee / LOWER URIS: STRCEEs TERDanT Led POWER ON LED 7 AUOTS FILTER Disaple CEPY/RIGHT [Lee T RIGHT AUDIO (RUBIO)A500 PLUS SERVICE MANUAL CONNECTORS REVISION HISTORY SCRIP ve IN ror ocoeR REVISION 375 603R0S| SEE SCHERATIC 912611-08 [For Guoen Revision en77 a3aRod SEE scnEneTiC 912007-01 rr tk Drs ms oncrnne novorne our MPOS TEV IZ ]TNTERNHL FLOPPY INTERNAL FLOPPY IKE YRDAR mT KEY COMPONENTS SASchematic #312813, Rev. 1 Sheet 2 of 10 NOTE: VARIOUS COMPONENTS ARE FOR EM! CONTROL PND HAY BE LOADED WITH FUNNY THINGS... Ul MC68000A500 PLUS SERVICE MANUAL A281) (1510 ROC 16:0 Tavinai Funeria US » EXTICK vt ovR ROY 5719 mm GARY _ROHEN CLARO CLKKR uO Gacerah LUIS oa DoD cia EVENCIR cok cKO ica] mig cone U2 8375 AGNUS HR ROACB HA) oracaso1 ASL. CAS -ARS(O) RASC) HE mH? A mk LPeN TAS YC VSTNC SYNC MAL ANTS Fe102 Th . nam XI xeLK ; __XCLKENE 52Schematic #312813, Rev. 1 Sheet 3 of 10 ROt 15:0): prars:0y comcpediitun _15lag avd hes Hes RAS OIE 2am Tras 1 thee ar EASLE ——thes —CRSU>*$—— peg tn feel Lt | 7 Ee ere UFA500 PLUS SERVICE MANUAL RAL 9:0) e202 4 Rezo | BRAS(O) BRAS() UPAR =BCASLO) -BCASLEA) JP 4B =BcASUCO} »-BCASUCI) FIT wuts tee or mo Leh a ms SPARE ; ores 20-29, use NOT CORDED FOR S12K sySTEH P21 igyae 68 i Be EG Se + a 53Schematic #312813, Rev. 1 Sheet 4 of 10 ORL 1S 101 oeeEe DENISE HR] 8373 § a cen he —esYNco> conc ett —thove The A > 403A500 PLUS SERVICE MANUAL VIDEG POWER = 1 Toy eet Tob fdond o a ies Fi Dw ta Be pd VIDEG HYBRID | _XCLKEN UPLT xu » AYIA coor x ANNEX EVEL FOR 390229-01 TORI. cok IXLSH SSN NMEA ARSE 54Schematic #312813, Rev. 1 Sheet 5 of 10 _F REA JP8 brent Fire #——_— a a | 8364 spencer ints Tiebett 2 NTS PRULA Sb ase inte opt 8 XD ep 8S 1x00 ROE 15:0). avons aca “LOKRD ; > 30K WD $3 one uy RoAL BLD orp lth comcast cenoceans the RST i , NOTE: GROUND INTERCONNECTION NEAR AUDIO vAcKS. “L ) on fp gl” u38™A500 PLUS SERVICE MANUAL LEFT oY r. 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