DesignandFPGAimplementationofafivestageMIPSpipelinedprocessor

Presentationdeadline:May8,2015

YoushoulddesignandimplementapipelinedMIPSprocessorinVerilogHDL.Theprocessorshouldcontain
the hazard avoidance unit (HAU) to solve data hazards by data forwarding and stalling the pipeline if
necessary.DemonstratetheoperationofyourprocessorusingthefollowingthreeMIPSprograms.
1. Thefollowingfigureshowstheblockdiagramofafilterimplementingy[n]=h0x[n]+h1x[n1]+h2x[n2]
equation.WriteaMIPSprogramfortheoperationofthisfilter.

Youcanusethefollowingvaluesinyourtestbench:
x={1,2,3,4,5,1,0,3,4,1,2,3,4,2,1,3,2,6,1,1,7};
h0=3,h1=3,h2=5;
Loadtheprogramanddataintotheinstructionanddatamemory,respectively,atinitialization.
2. The following figure shows the block diagram of a secondorder section (SOS) implementing y[n] =
b0x[n]+b1x[n1]+b2x[n2]a1y[n1]a2y[n2]equation.WriteaMIPSprocedurefortheoperationof
thisSOS.
b0

x[n]
D

b1

y[n]
-a1

x
D

b2

-a2

Youcanusethefollowingvaluesinyourtestbench:
x={1,2,3,4,5,1,0,3,4,1,2,3,4,2,1,3,2,6,1,1,7};
a1=3,a2=3,b0=5;b1=3;b2=7;
3. WriteaMIPSprogramfortheoperationofthefollowingfilter.

Youcanusethefollowingvaluesinyourtestbench:

x={1,2,3,4,5,1,0,3,4,1,2,3,4,2,1,3,2,6,1,1,7};
s0=3,s1=3;

SOS0:a1=3,a2=3,b0=5;b1=3;b2=7;
SOS1:a1=3,a2=5,b0=3;b1=5;b2=7;

Importantpoints:
(a)Latepresentationswillreceiveagradeofzero.Noexceptions.
(b)YourVerilogdescriptionoftheprocessorshouldbewellcommented.
(c) You should present your work individually on Friday May 8 in the VLSI Design and Test laboratory.
Pleasemakeanappointmentinadvance.
(d)Ifyouarereadytopresentyourprojectearlier,youcansendmeanemailtomakeanappointment.
(e) After you present your project, no additional time will be given to represent your project. So if you
decidetopresentyourprojectearly,makesurethatyouareready.
(f)Duringpresentation,Imayusedifferentvaluesforthevariablestotestyourdesign.