Major difficulties in Pipeline

Resource conflicts
Data dependency
Branch Difficulties

Resource Conflicts
Use Two separate memories for data
and Instruction

Data dependency
Hardware interlocks
Operand forwarding
Delayed Load

Handling Branch
Instructions

Prefetch target instruction

Branch target buffer(BTB)

It is a associative memory in Fetch segment of pipeline

stores previously executed branch instruction and target
instruction for that branch.
It also stores next few instructions in after branch target.

Loop buffer
Branch prediction-

guess the outcome of

conditional branch instruction

Delayed branch-

Compiler rearanges
instructions or inserts nooperation instructions

RISC Processors Features

Instructions are Uniform length
Single clock cycle for execution
Load store architecture

Three Segments of RISC

pipeline

Delayed Load

Delayed Branch