A Detailed Router for Field-Programmable Gate Arrays ‘Stephen Brown, Jonathan Rose, and Zvonko Vranesic of Toronto, Ontario, Canada MSS 1A4 Dept. of Electrical Engineering, University Abstract ‘The deuiled routing of Feld Programmable Gat Ars (FPGAS) sw new and dificalt problem because the wiring Se ‘ments evailable for routing can ony be conneciod togeta ins limited number of ways. This paper presents the Coase Grsph ‘Expansion (CGE) dealed routing algritun for FPGAs. The algorithm has he ability w resolve outing confi by consider {ng the side-effects of one connection on anoter, and can be sed over wide range of FPGA inercomecton arhtectires, (CGE ha teen used to obtain exelent routing ress for several industrial iets with various FPGA routing archise- fare. Theres how tha COE i able o route elaively large FPGAs in the absolute minimum munber of tacke ar dete ‘mined by global routing. and that CGE has linear run-time ‘ver ict ie, 1. Introduction Fie Programmable Gate Amays are an excting now approach io Application Specific Inapated Ceci tha educes 1Crmanufacuring time from months to minutes, snd mantic. ‘uring costs from dhousands of doles to unr $100. An FPGA hasan aay of logic ells connected bya general routing stuc- ture, ike a Mask Programmable Gute Array, but itis pro- agarmed by the user like a PLD. The FPGA was fist ino. ‘hcnd in (Car86, with newer versione presented in [EIGiS9] sa (Wong89]. Tie complexity of FPGAS has increased tothe int whee automatic design tools are essential. ‘A key problem in the detailed routing of FPGAs is that the suocesfl routing of some conecton may rely on the sssigament of a specie wiring segment inthe FPGA for that connection If this essential segment i assigned to some ober Connection, then routing fale ie guranced. Consider igure 1, which shows tee views ofthe same section of an FPGA. Each view gives he routing options for one of conaeedons A,B, tnd C. Inthe figure, rouing switch shown aan Xa wiring Segment asa doved ine, and a posible routs as slid line ‘Now, assume tata router fst completes connection A. If the wiring segment numbered 3 is chosen for A then one of connce- Tons B and C cannot be routed bees ty bh rely on the same single remaining option namely th wing segment num ‘bred I. The comect solution is forthe roster to chose the wi ing sepment numbered 2 for connection A, in which case both B and Ce als rouble, Altjough thsi a simplied example, i Ausrates the eosnce of conti because of limited rooting options in FPGAS. Common approsches used for detailed routing in other ‘ypes of devies ae not suitable for FPGAS. Maze rooers (Loeb) ae ineffective because they are inhereuy sequential tnd 0, when routing one connection, they cannot cone the side-effects on other connections. Channel outers (Has? ae ‘ot appropiate because the general routing problem cant be “This_work wat suposed by NSERC Opening Grns uRF0033298, HOGPOONSDED and reser prt rm Bell Noto Revach and TTRC. 22 (cH2924-9/90/0000/0362501.00 © 1990 IEEE Figure 1 - Routing Contes: ‘ubivided int independent chanel Nowe tht x channe! oat ‘ng algorithm is used for FPGAS in (GrecS0, bat tis only split for the particular eae of mn Actlsike FPGA (E1Ga89) ‘which is ranged at rows of lope calle separated ty channels, ‘This paper i nganined a8 follows: Section 2 presents the ‘model of the FPGA, Section 3 defines the detailed roting prob Jem, Section 4 describes the CGE algorithm, and Section $ resens resus fom tess of he outer 2. The FPGA Mode! ‘The FPGA is modeled as 4 two-imensional aay of logic cells interconnected by verical and horizontal rooting channels, simul 1 (Cen86), The FPGA comprises tree major pts: the Logie (1), Connection (C), and Switch (8) Blocks, as Shown in Figure 2 inthe figure, each L block as tv pins, wd there ae tee uacks in each routing chanel. The Agu aso defines several tems that ae used throughout the paper = ole ‘hata two dimensional gis overlayed onthe FPGA. The locks are programmable cells which howe the combination] sand seuential Hogi that form the functionality of a ezcu An Cbiock hts a number of pins that may each comectothe four sdjcentC blocks. Note hat UO blocks appear as L blocks on the priphery ofthe chip, ‘The C Blocks ae rectangular switch boxes with cone tion points on al fou sides, and sre wed 6 connec the L block ‘pin tothe chanels via programmable wich. Depending on ‘be topology, each L lock pin may be switchable al ory frscon of the wiring segments tht pase tough te C block. ‘The fewer wing segments connectable in the C Blocks, he hater the FPGA so route. Connections may also pass suaight through aC block, but na typieal outing architec no sich ‘would be involved fer such comectons ‘The S blocs are als rectangular switch boxes, They ae sed w connect wing segments in one channel segment {0 those in another. Depending on the topology of the 8 block ‘each wiring segment on onesie of an 8 block may be switch. thie wall oc any action ofthe wiring regmente on each other Sie of the 8 block. The fewer mizing segment tat can be ‘Switched 1, the harder the FPGA isp fous. A connection Dat ‘uses trough an S block may do s through switch or it may hardwired,3. General Approach and Problem Definition ‘Asin other design yes, FPOA routing isa combinator- ally complex problem, requiring the usual two-stage approach of tobe routing flowed by detaled routing, The global rue {eed here itn adaption of the Locusfoute global eating Algortim for sanded celle (Rose0b]- The global router ‘vides mull-oint nets ino two-point connections and routes them in minimum distance pai. I dstibues the comectons tsnong the channels so thatthe channel desis are balanced. Seay Letogetiek | V War CLecmecon Bock Rosia Chama! Sloua em Figure 2 The FPGA Modet “The globel router defines «cours route fr each connec- tin, by assigning ita teguence of channel segments, Figre 3a shows a representation of typical global rou for one connec tion. It gives a sequence of channel sogmens that the global outer right chose to comet some pa af logis lock a gid location 22 to another at 44. The lobl rou is called a coarse ‘79ph, G(V.A), where the L Mock at 22 isthe root ofthe graph fd the L block at 4 isthe leaf, The vertices, V, and edges, A, (Of GVA) are dented by the ged of Figwe 2. Since the glo- ‘bal router split all nets ino two-point connections the course ‘raph alvayshave afin outof oe. Fue a, Cours graph Figure 3-4 Typical Coarse Graph and its Expanded Graph After global rowing the problem is wansformed 0 the folowing: foreach two point conection, the detailed router ‘ust choose specific wrig segments to implement the channel ‘epmensassgned during global routing. AX this requires com: ‘te information about the FPGA routing architecture, CGE ‘se he deta of the LC, and S blocs, a described inthe fl- Towing sections, Fe3b. Beaniegga0h,D 4. The CGE Dotalled Router Algorithm. COB routes in two phases. In the first phase, it vumeries a rumber of dlematives for the detald rote of tach coarse graph, end then nthe scond phase, viewing all the Sltematver stone, it makes specie choles for each comec- fon The dessons made in phase 2 are driven ty « costing facto tat eben the lteratives enomerated in pase 441 Phase 1: The Expansion of the Coarse Graphs During phase 1, COE expands each couse graph and rwoorde a rbeet ofthe possible ways that it can be implemented. For each GVA), the expansion phase defines a dtalld graph, cealed DWE). N are the vertices of D and are its edge, with ‘ach edge refering wo a specie wiring segment in the detailed FPGA. The edges se abled with a number tht refers to the ‘comerponting Wing bgment. ‘The expansion algorithm is designed to allow CGE to ‘route wtitary interconnection architectures by testing the po: ‘Seles that define the connection topology of the C and 5 locks black-box functions. This approach alowed te use of (CGE a areearch bol in recent paper on FPGA rating chi- tectures [Rosed0d), The black-box function for # C Block is Genoted as fldasdatlds) amd for am S Block a8 Gilda ds. The parmeses in square brackets define an ‘ge tha connects vertex to veriex dy using Wiring se9- ‘ent labelled Such an edge is Int rfered wo as, where sda). The parameter dy isthe successor vere of d “Te tat ofthe fet cell canbe stated as "I the iting se. ment numbered is wed w connect vertex dy 10d, what ae dhe ‘wring segments that can te used to reach ds fom d3?" The fetion cal returns these of edges that answer this question. ‘igwe 3b shows en expanded graph for he couse graph of Fig ese ‘The raph expansion process for each couse graph roceods as follows: (Create D and give it the sume oot as G. Make the immediate cessor tothe rot af D the same as forthe wot of G, While traversing D breadh fit, expand cach aed vex ecisthe ‘ge inD tha has already bein chosen to connect 0 from predecessor. isthe required neces vere of C (mG) and 2s the et of edges retuned by fC). The call of) as |2| ees oD. Expand an$verx in D by cling (er) = Z eps he ‘lige inD that has already ben choaen to conect 0 Strom its predecessor. mi the required sucess verte of $ (ia G) and Zs the set of edges returned. by ()- Thal to (ads 121 oes D. Although te above description implies that ll possible ‘paths in an FPGA are seconded during the expansion proces, this is not practical becaue the number of path ean be very large in some architectures, Consequently, CGE reduces the number of path by pruning asi expans. At regu incrvals, 1 the course graph is expanded, heuristics are sed w discard ‘elected pati. Te heritice choogs which pth to koxp based fm the Wing sogmens they use. To help prevent routing tonics, when choosing between two wiring segments te Dedrsice wil Keep the one that has been used in fover expanded graphs thus fe. Note that when pats se discarded because of pruning, they are ot necessarily abandoned per sanenl by the route. ln phase 2, 6 CGE chooses comectons,it routing conflicts consume all of the slematives for some ‘paph, COE re-vokes the graph expansion proces o obtain & ‘ew satof phe i some eit 42 Phase 2: Connection Formation After expansion, each D(V.E) may contin numberof stumatve paths. CGE. places all the paths from all the expanded graphs into a single path lit Based on a costing fare tion, CGE then selects paths fom the lit each selected path efines the deulled route of ‘is coresponding connection Because the costing function allows it consider al the path ‘once, CGE is sido roue the connections “in pale. Phase 2 roceeds a follows: Put al he pas in the expanded graphs nto the pathist While the pasts not empty "e there ae pais in the past that are known w be sent, ‘Select the essential path that has the lowest cost Fhe Setect tho path with the lowest cost ‘Mark the graph comesponding to the selected path ar outed = remove all puke in this graph fom the path, ind al paths dat would conflict with the ssleced path ‘nd emove them from the path ist (6 Now). I a connection loses all of its aliemaive paths, re el Erate), Because ofthe summing proces in c(e), the mote graphs 0 oS Cec 10 ra anne | @ | 2 |e Drsm [6 | 10 1 [aos mse] 5 pas ‘Table 2- CGE Minimum W for 100 % rousing (F, = 0.5W) For comparison prpotes, the same problems have also teen rowed using CGE with is cost facty disbled. In this node CGE is basicaly » sequenial router, much like a maze footer. The conmectons are ordered forthe "maze’ rout by {kscendng length becuse the Ingest connection rquie he ‘most routing resources and intively should be the hardest 10 ‘ont, The second fom the right column in Table 2 gies the ‘uber of tacks thatthe "are’ ror needed to achieve 100 fetcon rooting. These rele show tha the aze’ roster Feauires an average of 68 percent more tacks than CGE. This ‘how tat solving routing conflict is impotae and that CGE (sdreue thi iesoe wall igure S shows the dealled routing for eteit BUSC, withthe FPGA parameters in Table 2 the L blocks ae shown a slid boxes, whereas the Sand C blocks are dashed bos. 53 Memory Requirements and Speed of CGE For the exaapls od here CGE noods between 15 and “15 Mites of memory. Ar shown ia the righmost column of ‘Table 2 experimental mearorement bow that CGE isa linear time algontim, requiring from 25 w 215 SUN 360 CPU Seconds for the sales othe largest ofthe example cucu. 6. Conclusions and Future Work ‘This paper has dexcribed the implementation of # new ind of deuted routing algorithm that can be tied to route ‘wide range of FPGA routing architectures. ‘The algorithm is {his consider the side-effect that routing deisions made for ‘ne connection may have on another, and ths resolve routing ‘conf In fur reser, routing delay opimizaton will be ddd to CGE. ‘Acknowledgments “The authors woud ike to thank David Lewis end Pal (Chow for mggertons onthe design ofthe route. Figure 5 ~The Detaled Rowing of Circuit BUS 6, References (Canto) W. Cane et al "A User Programmatic "Reconigersble Gate Amy,” Proe. 1986 CICC, May 1986, pp. 235-235 {1G389] ABI Gamal, et. "An Arcitctre for Elcsically ‘Configurable Gaie Araya” IEEE JSSC Vol. 24, No.2, ‘Api 1989, pp. 394-398, {red0} J, Greene, V. Royehowdhury, S. Keptnogl, and A. El Gamal, “Segmented Chanel Rowing. Proc. 27th DAC, pp. 567-572, Jone 1990. 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