SA CHAPTER 5 MOS INVERTERS: STATIC CHARACTERISTICS Design a resistive-load inverter with R = 1k such that V,, = 0.6 V when an cenhancement-type nMOS driver transistor has the following parameters: (@). Determine the required aspect ratio, W/L. (b). Determine V,, and Vj, (©), Determine noise margins NM, and NM, SOLUTION: (a) 4sv When V,,.= Voy. Vj = Vop = 5.0V, the driver transistor operates in linear region. Using Eq6.13) 5-06 _22x10* W =e. ~1)0.6-0.67 con [2(5-1)0.6-0.67] Solve for W/L, Feo01 ()When V,, = V,,, driver transistor operates in saturation region. Using Eq.(5.19) Vo ~ Vou =p W (Vn Veo R, hy a, Taking derivative with respect to V,, and set Dy, | 281 aVuy R, dv, Thus, 1 Vis = Vig # yp = LO 1000-22 x10 -90.1 =10 1s[v] ‘When V,, = Vip driver transistor operates in linear region. Using Eq.(5.24) repeated here: EW, 2L [2% ~Vro Mae ~ Vou] aw, 1 Ree L Plug in back to Eq(5.24) repeated above to solve for V,, Vin = Veo + 2Vow — Yop — Vou & W] 3.09[V]© 5.2 Layout of the resistive-load inverter design. (@) Draw the layout of the R-load inverter designed in excise problem (5.6) using a polysilicon resistor with sheet resistivity of 25Q/square and the minimum feature size of 2um. It should be noted that stands forthe effective channel length which is related to the mask channel length as L=L,,+8- 2L.,, where 5 (process error) = and L,=0.25 ym. To save the chip area, one should use the minimum sizes for L and W. Also, the resistor area can be reduced by using the folded layout (snake pattem) of the resistor. (©) Perform the circuit extraction to get the SPICE input list from the layout. (©) Run the SPICE program to obtain the DC voltage transfer characteristic (VIC) ‘curve. Plot the VTC and check whether the calculated values in Problem 5.6 match with the SPICE results. SOLUTION: (@) The layout is shown in the following. io 2(©). SPICE simulation for the parameters given in problem 5.6. SPICE input list: Reload inverter DC analysis mi 21.0 0mn wel80u 120, r32%r vad 300 5.0 vin 10 00 smodel m mos (vton1.0 kp=22u gamman0.2) séo vin 0 5 0.05 sprint de v(2) sod ‘The VTC curve is shown in the following. V,, and V,, match the calculated values. in 2853 Refertothe CMOS process described in Chapter 2. Draw cross-sections of the following device along the lines A-A' and B- Poysicon ‘Active Area Bd] com Figure P55 SOLUTION: ‘The cross section is not drawn to scale. For A-A', SCY gate oride Si-substrate 29‘The cross section for B-B': Poly-Si Si-substrate SA Calculation of Vi» Vo and the noise margins for the saturated enhancement-load MOS inverter circuit. SOLUTION: In order to obtain NH, Va, and V,, needs to be calculated. The value of Vy, must be found first to caleulate V_y- ‘Veg? load transistor in saturation, since y=0, V,=Viy k 2 24 (Von ~ Vou ~ Vr)? =0 nt j Vou foo ~ Vp =5-0.8=4.2V ‘Vo! load transistor in saturation, driver transistor in linear region, input is V.,, Koa 2 _ Keviver “st (Vino ~ Vou — Veo) = “#2 (2(Vou ~ Vro)Vou ~ Vou") (5-Vo, -0.8)° =10(2(4.2-0.8)Vo, 11Vo,? —76.4Vo, +17.64 = 0 Vo, = 0.239V Vo.2) ‘V,,: load in saturation, driver in saturation. k, ky Ais (Voo ~ Vas ~ Veo) = “48% (Va Veo) (5 Va ~0.8)* = 10(¥j, ~0.8)° o take derivative wit respect to V, on both sides and use55 57 59 5.10 W, a, Ie We 2 Vg) <4} (4 -{% )=2902-09) Vipg =12.2-10Vy, when V,, = V;,- Thus plug these relationship back into (1) (4.2-12.2+10V;,)" =10(V;, -0.8)" 90V,.? -144V, +57.6=0 Vj, =0.8V NM, = Vy Vor = 0.8-0.239 = 0.561V Please follow Example 5.3 and discussion of the design criteria for the depletion-load inverter circuit (pages 165 - 172) Please follow Example 5.4 and discussion of the noise margins for the CMOS inverter circuit (pages 179 - 181). Please follow the discussion of the inversion threshold for the CMOS inverter circuit (pages 181 - 182). For Part (a), note that the nMOS transistor M3 operates in linear region, and that its drain current must be zero. Consequently, the drain-to-source voltage drop across M3 isalsozero. Thus, the CMOS inverter operates at inversion threshold (by definition), and its output voltage is equal to V,. The remaining parts (b and c) can be solved by straigthforward use of the current-voltage equations. For Part (a) and (b), the solution is very similar to Problem 5.7. For (c) and (4), note that the slope of the transition region of the voltage transfer curve (VTC) becomes smaller (i.e. less steep) for larger values of the channel length modulation factor 2. Consequently, CMOS inverters built with long-channel transistors can be expected to have steeper transfer characteristics, and hence, a higher gain in the transition region. The solution can be obtained simply by solving the corresponding current-voltage equations for each stage. 31