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    Figura 09: Practica en Protoboard

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    © All Rights Reserved
    Download as PDF or read online from Scribd
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    13 views26 pages

    Datasheet PalFigura 09: Practica en Protoboard

    Uploaded by

    Diego Aguilar
    Figura 09: Practica en Protoboard

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    com PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic SITINQNN5I25, OAO/SI25 IND: H.10/15°28, 0.2025 iL: #1572025 Advanced Micro Devices DISTINCTIVE CHARACTERISTICS 1 Pin, function and fuse-map compatible with all 20-pln GAL devices 1m Electrically erasable CMOS technology provides reconfigurable logic and full festapiny 1 High-speed CMOS technology — 5ns propagation delay for 5" version = 7.5 ne propagation delay for 7" vorsion 1m Direct plugein replacement for the PALIERS ‘seriea ond moot ofthe PALTOHS coreg 1 Outputs programmabie as registered or combinatorial in any combination ‘& Programmable output polarity 1m Programmanle enabio/aisabie control 1 Proloadable output registers for testability, Automatic ragister reat an power up 1m Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages ‘= Extensive third-party software and progran ‘support through FusionPLD partners © Fully tested for 100% programming and functional ylelas and high rotapiity 1m 51s version utilizes a spilt leadtrame for Improved performance GENERAL DESCRIPTION The PALGEI6V8 Is an advanced PAL device bul wilt low-power, high-speed, electricaly-erasable CMOS technology. Iti functionally compatible with al 20-pin GAL devices, The macrocol provide auniversal doviec arcitecture, The PALCET6V8 will drecty replace the PAL16R8 and PAL 10H6 series devices, wih the excep- tion of the PALIEC ‘The PALCE16V8 ullizes the familar sumo products (ANDIOR) architecture that alows users to implement ‘complex logic functions easly and eftciensy. murple levels of combinatorial logic can always be reduced to ‘sumof products forn, taking advantage of the very ‘wide Input gales avalably ht PAL Uevives, The equa tions ate programmed into the device through floating gato cols in the AND logic array that can be erased slecticaly, “The ixad OR areay allows upto sight data product torms per outputforlogicunctons. The sumofthese products fas Une ouipul macrocell Each macrocellcan be pro- (rammed as registered or combinatorial with an active high or actve-tow output. The output configuration is, dotormined by ‘wo global bite and one local bit ‘contaling four multiplexers In each macrocoll AMD's FusionPLD program allows PALCE16V8 de- ‘signs tobe implemontod using a wide variely of popular industry standard design tools. By working closaly with the FuSionPLD partners, AMD cortles that the tools rove accurate, ually Suppon. By ensuring trated party tools are avaliable, costs are lowered because a designer doas not have to buy a compete set of new Tools for each device. The Fusion? LD program also ‘greatly reduces design tine since a designer can use a tool that already installed and familar, Piease refer to tho PLD Software Reference Guide for cariled dave ‘opmenteystems andthe Programmer Reference Guide {or approved programmers 28 sacicaadiediod Mead auo o1 BLOCK DIAGRAM noe este Programmable AND Arey ‘ex an I Il I ll bas facto] __firacro]__ fact farcro]_ fora fascr sacra] [waco] : lcs I 1 i Se We Ws es Os Wor CONNECTION DIAGRAMS Top View DIPISOIC PLCCILCC. Sag 3a $e joes ones fe: i$ mar onrton Sos sees PIN DESIGNATIONS CuK = Glock GND = Ground P= input vo npuvourpur OE = Curpurenabie Veo__= Supply Votage PALCE16V8 Family 249 Th nwo ORDERING INFORMATION ‘Commer cial and Industrial Products AND programmable ogc produce for commercial and Indus appcatons are avalabla with several orderag options. Tha ‘tder number (Vaid Comtinaton) is formed by a combination of FAMILY TYPE PAL = Programmable Aray Logic TECHNOLOGY GE = CMOS Electicaly Erasable PAL CE YEH SPOS L ‘OPTIONAL PROCESSING Blank = Standard Processing PROGRAMMING DESIGNATOR Blank = lava Algorthm NuMBER OF Tt Fa enon a 1 Second prion ves (Same Algorithm as /4) gureur re ST Nersate NUMBER OF FUPFLOPS POWER ‘OPERATING CONDITIONS H = Hat Powor (90 ~ 125 mA lo) = Quater Power (55 mA lc) C= Commercial (0°06 +75°C) VT industrial eA0%C 0 20550) soso srotgoe ye ao PORIE REE, on ro say sa fom 2 = Seesaw bal alent = 20-Pin Plastic Gull-Wing 20 = 20nstro maak PALCE LESH. JC 5 ‘Valid Combinations lists configurations planned Bien [— pos ed Sout on coarse PALCE16VaH-10 | PO, JG, $6. PL 7 {helocal AMD salsa conti aalabty of micoeere| —Peaese | Seca facsriore | Poa PALCE16VBH-25 | PC, JC, SC, PILI “ a PALCE16VBH-67/10/15/25, Q-10/15/25 (Com') H-10/1825, 020725 (Ind) wo o4 ORDERING INFORMATION APL Products (Mi AN progr ” able age product fx (Agproved Products List) progucs are full compar wit ML ST Aerospace and Delense appeaions re avaiable wth sevoral ordering options. APL 889 roqrmants. Tha order number (Vand Combinaton) PAL CE GVOHASESORA FAMILY TYPE LEAD ANISH Pat» Programmable ray Loge Bre Ho! Solder Dp ‘TECHNOLOGY - PACKAGE TYPE CE = CMOS Exctcaly Ersable B = 20in Ceramic iP (cn con) NUMBER OF ‘ARRAY INPUTS ourput type We Nereis, NUMBER OF FLIP-FLOPS Power H = Half Power (199 mA ee) SPEED 15 = 156i 20 5 zoe 25 © 25net0 Yatld Combinations 2 2 208in Coramie Leadiese Chip Carter (CL. 020), DEVICE cLass B= CassB PROGRAMMING DESIGNATOR Blank ~ ital Relaace Ee = Fist atid Combinations PaLceiavenis | 64 PALCEseveH.20 | Blan PaLceieveHios | E+ Vaid Combinations lists configurations planned tobe supported involume arth devem, Coneut thelocal AMD sales oficeo cons avaabty of $pectiovaldcombnatone anda chesk anneniy ‘leased combinations RA itary Burn Macy bu i ssaordance win conditlona are selected at AMD's oon, Group A Tosts [Group A tests consi of Subgroups 1,2,8.7,8.8, 10.11 18 Uren! resin of MiL-STO-889, Test Method 1015, Conlon A through E, Test PALCET6VGH-15/20125 (Mi) 2a Thaw FUNCTIONAL DESCRIPTION ‘The PALCE1EV8 is auniversel PAL dovice.Ithas eight independerily configurable macrocels (MCs-MC?). Each macrocellean be configured as regstered output ‘combinatorial output, combinatorial /O or dedicated in put. The programming mati implements a program Table AND log array, which dives a fixed OR logic array. Burers for device InpuIs have complementary ‘outputs to provide user-programmable input signal po- lay. Pins 1 and 11 serve ether as aay inputs or as ‘uch (CLK) and oulput enable (OE), respectively, forall tip-top. Unused input pins shouldbe tied directly o Voc or GND. Product terms wih all bis unprogrammed (discon nected) assume the logical HIGH state and product ‘terms ith oth true and complement of any input signal connected assume a logical LOW state The programmable functions on the PALCE16V8 are automatically conigured fom the usore docign specification, which canbe in anumber of formats. The esign specication is proceaoed by devolopmant cot. ‘are to very the design and rea a programming io, ‘Thisfle, once downloaded aprogrammer, conigures the devion acenring o the user's dasted function ‘The user is given two design options with the PALCE16V8, Firs, canbe programmedasa standard PAL device fom the PALIORS iti PALIOH® series. ‘The PAL programmer manufacturer wil supply device ‘codes forthe standard PAL device architectures to be Usediwith the PALOL#OVO. Tho programmer wil pro- gram the PALCE16V8 in the corresponding archite- ture, Ths allows the user to use existing standard PAL ovice JEDEC fies without making ary changes 10 them, Atematively,the device can be programmedas ‘aPALCE16V8, Here theuser mustuse the PALCE16V8 fevica code. This option allows ful utlization of the macrecel, a = ees, on oe 39) = Jo: vec P04 Fel + T 4 + + Asox soi - jo a Noe 10 ox = 7 From ean ssar JL stox Pin ‘in macrocalls MCo and MCr, SG1 Is replaced by SGO on the feedback multiplexer. oe PALCE16V8 Macrocat ‘BS PALCE16V6 Family uo 21 Configuration Options Each macrecellean be corfigured ae one o tho follow ing:registered output, combinatorial output, combina ial VO, or dedicated input. In the registered output ‘configuration. the cutout butleris enabledny the OF pin Inthe combinatoval configuration, the butler is ether Controted by a product tem or alvays enabled. Inthe \esicated input configuration, tis always disabled. With the exception of Mo and MG», a macrocal configured as adedicatedinput derives the input signal trom an ad- Jacent VO. MCe derives its input from pin 11 (OE) and MO from pin + (CLK. ‘The macrocell contiguraions are contolied by the con: Aiguration control werd. It contains 2 global Bis (SCO ‘and SG1) and 16 ca bits (SLO through SLOrand SL 10 through SL17). SGO determines whather registers will bo allowed. St dotormines whether the PALCE10V8 willemulate a PAL 16R6 family ora PAL 10H family de- vie. Within each macrocel, SLO, in conjunction with Gt, selocte the contiguration of the mooreoal, and Lis sets the output as ether active low or active high {or the individual macrocel ‘he configuration bits work by acting as contol inputs {or he mutplexersin the macrocell, There are four mut tiplexers: product term input, an enable select, an out ul select, and a foecack seiect mutpiexer. Sst and ‘SLO are the control signals oral four muliplexers. In MCo and MC;, 55 replaces SGt on the feedback mul Uptener. This accommogates GLK being the aojacent Pin for MCr and OE the adjacent pin tor MCe. Registered Output Configuration The control bit settings are SGO=0, SG1 = 1 andSLO,= 0. There is only one rogisteed configuration. Al eight product terms are available a inpuls lo lite OF gal Data polaty is determined by SLtx The tlipsop is loaded on the LOW-1o-HIGH transition of CLK, The feodback path io from @ on the register. The ouipul bufferis enabled by OE. Combinatorial Configurations ‘The PALCE16V8 has throe combinatorial ouput con: figurations: decicatedoutputin anon-registered device, UO in a nan-ragiiorad rlavion and UO in 2 rgistered evice, Dedicated Output in a Non-Registered Device ‘The controibitsettings are SGO = 1, 81 = OandSLo. ©. All eight product terms ara avataia to the OR gate ‘Although the macrocellis a dedicated output, the toed. back is used, wih the exception of pins 15 and 16, Pins 15 and 16 do not use feedback inthis maa Reeause CLK and OF are not used in a non-registered device, pins 1 and 11 are avalable as input signals. Pin wil Use the feedback path of MCr and pin 11 will use the fenctack path of Ms Combinatorial V/O In a Non-Registered Device ‘The contrlbitsotings are SG0~ 1,SQ1-=1,andSLO«= 4, Only seven product terms are availabe to the OR ate. The eighth procic erm fs tsd in anata tha out put buffer. The signal at the VO pin is fed back to the AND array via the feedback muitiplaxor. This allows the pinto be used as an input Because CLK and OE are not used in a non-registered device, pins t and 11 are avalable as inputs. Pin 1 will tee the foedbace path of MC;and pin #1 will use the feedback path of MC. Combinatorial VO in a Registered Device ‘The controtbt settings are S60 =0, SGI = 1 and SLOe= 1. Only seven procuct terms are available to the OR ‘gato, Tho aighih produet torm ig used ag tho output ‘enable, The feedback signal isthe corresponding VO signal. Dedicated Input Configuration ‘The controlbitsettings are SG0 = 1, SG1 = 0and SLOx= 1 Thacupuathuiterisdieablod. Excopltor Me and Cr the feedback signalis an adjacent VO. For MCa and Cr the feedback signals are pins and 13. These contig: rations are summarized in Table t and iitrated in Figure 2 ‘Table 1. Macrocell Configuration Sa7[ 5G] stor] Cer coniguravon| Devers Emulsed Dovico Uses Registers ©] 1] © | eaiteres up [PALiona TORS o L114 |conbistratuo [PAttens, ene Device Uses No Registers TO] © | eomneintat [Pat rane Pa ipa va tate, ola ie tae ies 1 fo} + frp Paine ae fang tate at tL] s Jeon vo [PAtiers Programmable Output Polarity The pola of each macrocell canbe actve-high or ac tive-low, ether to match output signal needs or to feduce product terms. Programmable olay allows Boolean exprossions to be writenin heir mostcompact form (rue or inverted), and tho output can silbe ofthe esizd pola. I can also save “DeMorganizing" ettons. Selection is through a programmable bit SLs which controls an excieive- OR gate atthe output ofthe ANDY COR logis. The outputs active high #SLtsis 1 andactive low if SL13160 PALCEI6V8 Family Excl Daw of of = Rogistered Active Low = — Combinatorial vo active Low = ‘Combinatorial Output Active Low Notes: 1, Feadback's not avaiable on pins 15 Mid 18 Ure cosa wat nde 12, This configuration is net avalabe on pine 1 and 16 —«t—_ Rogistered active Hight a ee Comtnatoria VO Active High ==} — Combinatorial Output Active High Fl. TEE Meeertvo Niote2 Dedicated input a vsteo0s Figure 2. Macrocell Configurations 254 PALCET6VE Family Power-Up Reset Alllip-lops power upto aloo LOW tux previciable sys- {em intiazation. Outputs of the PALCE6V8 wil de Pend on whether they ate selected as registered or ‘comhinatarialWragistoredis selectod, the output wil bo HIGH. If combinatorial i seloctod, the output wil be a function of the loge Register Preload ‘The register on the PALCE16V8 canbe preloaded trom the outout pins to facilitate functional esting af camplax sale machine designs. This feature allows direct load- ing of arbitrary states, making it unnecessary to cycle ‘through long fast vector sequences to reach a dosed slate. In addition, transitions from ilegal stales can be verlod by loading legal states and observing proper recovery, Security Bit security bts provided on the PALCE16V8 as adeter rent lo uneullrized copyiig of tne array eonnguraton patterns. Once programmed, ths bit defeats readback and vefication ofthe programmed pattern by a device ‘programmer, coeuing proprioary designs form com ptitors. The bit can only be erased in conjunction with the array during an erase cycle Electronic Signature Word ‘An electronic signature word is provided in the PALCE16V8 davice. it consists af its of programm. able memory that can contain user-defined data, The signature datais alvays availabe tothe user independ: ent ofthe security bi aun oA Programming and Erasing ‘The PALCE eve canbe programmed on standard ogte programmers. it also may be erased to reset a prev ‘ously configured device back to is virgin stat. Erasure Ie automatealy pertormes by the programming har ware. No special erase operation is required Quality and Testability ‘The PALCE16V8 offers a very high level of bull-in qual ily. The erasebilty ofthe device provides a direct means fat varying peviormance ofall AC and DC parameters. In addition, his verios complete programmabilty and functionally of the device to provide the highast pro gramming yields and post-prearammina functional yelds inthe industry. Technology ‘The high-speed PALCE16V8 is fabricated with AMD's advanced electrically erasable (EE) CMOS process. ‘The array connections are formed with proven EE cels Inputs and outputs are dasigned to be compatioe with TTL devices. This technology provides strong input clamp diodes, output stow-rate control, and a grounded Substiate for ea smh, PALCE‘6V6 Family 255 Davo LOGIC DIAGRAM recone we PALCE16V8 Family au TV LOGIC DIAGRAM (continued) TT a nna eves (coro) PALCE16V6 Family 287 Tl nwo ABSOLUTE MAXIMUM RATINGS. Storage Temperature e°C to +1508 ‘Ambient Temperature with Power Applied . -B55C 10 43250 ‘Supply Voltage with Respect toGround esse 05Vi0+70V DC Input Votiage OV to Veo + 1.0 0c Output or YO Pin Voltage OSV toVes+ 10 State Diecharge Vottage 2001 v Latchup Current (T= 0°C to 475°C) 100A Stresses above those listed under Absoluto Maximum Rat ings may cause pormanent device favre. Funcionaty ator above thse iis sno nolo Exposure to Absolute Max ‘num Hangs tor extended periods may afer oovi ekaa- ly. Programming cordtons may afer OPERATING RANGES Commorcial(C) Davieos “Tomporature (Ta) (Operating in Free Air Supply Vottage (Voc) with Respect to Ground 0°C 10 475°C 4A 75V10 45.25 Operating angeo dein thoes nite batwoon which nef. ‘ional othe doviee fs quarantod, DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified ‘Symbol | Parameter Description Test Conaitions tain | nox _| unit Var | Ouput HIGH Votage Towe-82mA Vane Vir Vi 2a v vee = Min Vor | Ouipul LOW Vatiage ToL =24mA Vn= Vivor VL os |v Veo = Min Vin | pat ice Vonage ‘Guaranteed pul Logical GH 20 v Voltage tor al Inputs Noo 1) Ve | RRA TOW Vato “Guaranteed Input Looeal LOW oa | Valege fora Inputs (Note 1) 7 Trp HIGH Leakage Currant | Un = 85 V, Voo » Max Nate 2) [a ™ TapU LOW Leakage Curent | Viv= OV, Vas» Man Ww 2) 300 [we Tox | Oft-Sate Output Leakage | Vour #55 V, Voc = Max 70 | oA Curent HIGH Vs = ior Ves Note 2) Toa | Of State Ouput Leakage | VauT= OV, Voo = Max =100 | aw Curent LOW Vot= Ve oc Vn ote 2) Toe | ouiut Sion Oreuk Gurent | Vou = 05 V, Voo = Mov (Noto 3) mae] ase [a eo | Supply Cure ‘Outputs Open, (our = mA) 115 | ma (Dynamic) | Wee «tat = 25 Me Rote Those ae absolute values with aspect tothe deve ground and al overshoot de to systom andtester noise are include, 1 2 wOple leakage isthe worst case of lx and lo (or ano 3. Not more than one output shouldbe tested aati. Duration of tho short-circuit test should not excoed one second our 05 V has boon chosen to avoid tes problems causod by taster ground degradation Te~C~CSC AL CENVBH-7(Com”ty aw 21 CAPACITANCE (Note 1) Parameter ‘Symbol | Parameter Description Test Conditions Typ_| voit Gn Input Capactance Va=20v VoenS0V,Tan250 |__§ | oF cour | Output Capactance Vour=20¥) (a2 el Note: 1. Those parameters are nt 100% teste, but ore wrote a iil aati an ay ttn eg undid whore eapactance may be afectes, SWITCHING CHARACIEHISTICS over COMMERCIAL operating ranges (Note 2) Tag oe SET [pana seintin ole] vn | une ohne Fons Soave [Tas SS Cee ‘Guero eH ae 7 z oi in 3 = [oes ialaeale Beam Sir ies GSSTOS TOS ts a a vitae | Ear eat —— [a ra it ww [MS [asain e ine (wees) No Feedback Tito + 89) 125 MHz | aoe tS [oF ores et ae SCE Te 2, See Switching Test Ccut for test conaitons. ‘3. Those parametars are not 100% tasted, but a nara frequency may be alleen. 4. Skew testing tahos into account patern ad switching decin dllerences between ouput that have equa loading. 5. Output dey minimums ort toa tna ne ton 2d tate dened under boot ase conions. Future procass improvements ‘may attr these values therefor, minimum values aro recommended fer sinuaton purposes oni, cakulte at intial charactoriation and at any tine the desi s madied PALCE(6V8H-7 (Com')) et TV aw ABSOLUTE MAXIMUM RATINGS, OPERATING RANGES Ctorage Temperature 166:C to 1160°¢ Commercial (C) Devices ‘Amant Temperature “Temperature (Ta) Operating wth Power Applied sos -B5°Ct0 415° in Free Air . 0°C 475°C ‘Suppty Vonage win ‘Supply Voltage (Vee) with Respect to Ground... 05Vi0 +7.0V Respect to Ground = +475 V 10 45.25 V Oc eee +1 5 VI0Ves +05 operating ranges define those lng between which the fone DC Output or 10 analy of the device i guarartood. Pin Voltage... 05 V0 Yeo +05 Static ischarge Voltage 2001 v Latchup Current (T= 0°C 10 75°C) ceeee 100 mA ‘Sresses above thos listed under Absolute Maximum Rat ings may cause permanent devi alr. Functionally ator ‘above these mks not implied. Exposure to Absolute Ma et evn vob DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified ‘Symbol | Parameter Deseiston Tost Conditions tin_| tox | uot Vor | Oulput HIGH Votage Tow=-22mA Vw Vor Va, 24 v Vor | Ouipul LOW Vatage Tee24mA Vn=Vivor Vi os |v Veo = Mia Va) Ra GH Voiags “Goaranteed apt Logeal HIGH zo v oiiage or al inputs (ee 1) Ve | npulLOW Vatage “Guaranteed Input Logeal LOW os |v Vatage for nus te 1) rm Topui HIGH Leakage Curent | Viv= 525, Vos = Max Note 2) [a ni Input LOW Leakege Gun Vin = OV. Vee = Max (Note 2), 100 | va Tox) Off Siate Ouput Leakage Vour = 825 V, oo = Max 10 | wa Curent HIGH Voi = Vetor Ve (Note 2) Tea | orate Cupar Leakage Your = 0V, Mas = Max 700 | oa Curent LOW Vis Vitor Vi ote 2) is] Output Shon-Groul Curent | Vour = 05 V, Voc = Max (ole) =e | =150 | ma Tec | Soppiy Curent (Oyearic) ‘Outs Open (our = 0 mA) = | ma Voo= Mak f= 15 te 1. These are absolute values nth respect o device ground and all overshoots due fo system or testo ois are included, 2, UO pln eskage isthe worst case of fc and aa (or and oz) ‘8 Not mare than one ouput shouldbe shorted at a time ad drain of the short-ccut shou nt exceed ane $6200. Vout = 05 Vhas boon chosen to avoid lest problems caused by tester ground degradation. 264 PALCET6V6G-10 (Com') amo 01 CAPACITANCE (Note 1) Parameter ‘Symbol | Parameter Descriptions Test Conditions typ _| unit Gu__|toput Capactance Vne20v | Voo~50V, Ta 25 5 | oF our | Ouper Capaciance Vout= 200] f= 1Mi or Note: 1. These parameters are nt 100% tested, but ar mere capactance may be afected. alvsted at tial charatorzation and at any tne the deslan is meted SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Poramete Symbol _| Parameter Description ax_| unit ‘eo | pul os Fecubck Combinatorial OupUT 70 [a8 15__ | Setup Time om Input or Feadbackto Cock 7s = tw __ [Hold Time ® ne 1eo__| Cockto Output 3) 7s | te rm tow @ ne Ht tok tn wei m= Maman Extonal Feadbeck “tsse0) ea, ui tnx | Rae Intomal Feedback le) Tia i No Feodback “wavin 235 ate wax | OE w Outaut Enable foe toot twa | BE t Ouput Disable 2 | 0 [a tex | input Output Enable Using Product Term Control 3 | 0 [ne ‘ten | Input to Output Disabia Using Procuct Term Contol 3 | 0 | me Note 2. See Suiting Test Cou orrastconations. ‘3. Thoso paramoters are not 100% taste, but ar calculated at nal characterization and at any tie the design is modified whore frequency may be afected. 4 Cutputeotay minimums for ra ca texte tex ard ten are defined under best case condions. Fuure process improve: ‘ments may ater these values therefor, minimum values are recommended or simulation purposes ony. PALCET6V8G-10 (Com) 265 Tino ABSOLUTE MAXIMUM RATINGS Storage Temperature 85°C fo +150°C Ambient Temperature vith Power Applied BBC 10 +125°C ‘Supply Voltago with Fospect to Ground ~O5Vi0 +70V DC Input Voliage ........-.. -O5 Vio Vec +05V UG Ourputor WO Pin Voltage... O5Vio Veo +05 Static Discharge Voltage 2001 V Latchup Current (Th= 40°C 10 +85°0) 100 mA Stresos above those Feted under Absoule Maxinum Hat- ‘ngs may cause pormanent dace faiure. Funetonaliy ator ‘above these linis not ped. Exposure to Absolute Max mum Fatings for viondod painde may alot davine ata. 4 Programming condions may afer OPERATING RANGES. ‘Commercial (C) Devicos ‘Temperature (Ta) Operating in Free Air Guppy Volago (Veo) with Respect o Ground = OC t0475°C A750 +525V Industral () Devices Temperature (Ta) Operating in Free Air... 40°C 10 485°C ‘Supply Voltage (Vee) with respect to Ground +45 V10155V Operating ranges define thas iit btweon which the uno Analy 0 the devia la guarantood. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating rangee Parameter ‘Symbol | Parameter Description ‘Test Conditions: min | max | unit Vor | Output HIGH Votage To=-32mA_Vn= Vino Va 2a v oo = Min Vor | Outpur LOW Vatiage ‘a =24mA Vara Vor Vi os |v Vor «Mie Vin | rut HIGH Votage ‘Guaranteed input Logical HIGH 20 Vv atiaga oral inputs Na 1) Vi | ipa LOW Vorage “Guaranteed Input Local LOW oe fv Voliage for al inputs Nott) Ti [tat GH Leakage Ooront | Vin= 525 V, Ve = Mex (ote) 7 [aw © Trp LOW Leakoge Curent | Viv= OV, Yoo = Max (Note 2) m0 | wa. Toa | Off-Site Out Leakage Vour =525 V, Vo = Max 70 | HA Curent HIGH Vin Visor Vi (ote 2) Toa. | Off State Ouput Leakage Vour=0V, Voc = Max 00 | eA Cumrant | OW Var= Visor Us (ota 2) Tee | Output Shon Otel Curent | Vour = 05 V, Vos = Max (Nate 5) =0_[=150 [ma ‘co | Commercial Sippy Gurent | Oulpuis Open (laur= 0 mA) iH 20) a (Pynamiey Woo= tag ta 19 tz @ 35 Teo | advent Supply Curent ‘Quits Open (cur = 0A) a 1301 (ynamic) oo Max, t= 15 Mle @ |" Notes: 1. Theso aro absolute values wth respec to device ground and all overshoot due fo system ortestor noise are included. 2. WO pn leakage fs ne worst case of. anf (0r ant az. ‘Not more than one ouput shouldbe shorted ata tine and duration ofthe shorckeut should nt exceed one second. Vour = 05 V has boon chosen te avoid est problams caused by tester ground degradation 208 PALCE16VBH-15125, O-15/25 (Com, Ind), 0-20 (nd) amo OU CAPACITANCE (Note 1) ‘Symbol | Parameter Descriptions ‘est Conditions yp | von Cn | pst Capacitance Vnz20V | Vo5~50V, Tn = 256, | pF Gurr] Ovi capac Wournzov | teimne © LF Now: 1. These parametor ae not 100% tested, but are evaluated at intial charactrizaion and at any tine the desion is modied whore capactance may be sfocted, ‘SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) a =o Parameter Description Min] Max | Min [ox | ain] Max | Uni ‘to __| Input or Feedback to Combinatorial Ouipak 15 20 25 | ns 7s] Setup Tine fom Rpt or Feedback Cock 7% 3 ne tH __| Hol Tine 2 2 © ns ae e 7 [as ™ | coawan LO" @ 0 2 te ‘wn HIGH, 2 o 2 ne a Exiemal Feedback [iiteves) | 455| a1] 7 ez fax | eaueney Intomal Feedback (cx 50 a5. 40 Mee No Feedback [twisty | 62.5] 509] os (wax ___| OE Oupul Enable 7 7 2 | ns a 12 ts | os ‘x | puto Output Enable Using Product Term Gonvol 15 18 20 | #8 ten | Hout Outout Disable Using Product Tam Conte 15 8 20 | oe Notes: 2. See Switching Test Creu forest condone. 3. These parameters are no 100% teste, Dut are casio at tial charactentation and at ay time tho design is modiied anor frequency may be affected. PALCET6VGH-15i25, Q-15/25 (Com', ind), O-20 (Ind) 27 ano 21 ABSOLUTE MAXIMUM RATINGS ‘Storage Tamnacatire 65°C 0 +150°C Ambient Temperature with Power Appled BSC fo +1250 ‘Supoly Voltage with, Respect to Ground: -05Vt0 +7.0V DC Input Votiage - 5 VinVec +05V DC Output or vO Pin Voliage DEVI Ves 105 Static Discharge Voliage +2001 V Latcnup Current (Ta = 0°C 10 75°C) = 100-ma Stresses above thove fisted under Absolute Maximum Rat- ings may cause pormanert device favre. Functonalty ator ‘hove these mts e rot implies. Exposure 0 Absolut aN ‘mum Ratings for extended periods may aflect dove relab- fy. Programming condtons may dtr. OPERATING RANGES ‘Commercial (C) Devices “Ambient Temporature (Ta) ‘Operating in Free Air ‘Supply Vottage (ve) win Respect io Ground Industrial () Devices Operating Case 0°C w 475°C 4475 V 10 +525 “Temperature (Te) 40°C 485°C ‘Supply Voltage (Veo) win Respect o Ground . HSVIOWSSV Operating rane eve sls between which tho fe tionally othe devi Is quarantoe. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Parameter Description __| Test Conditions in| mex | une Voi | Ouput HIGH Votage Ynn= VivorVi. iou=6ma | 386 Vv Veo = Min Tou = 204 |Voo~0.1V Vv Var | Cupar TOW Votage Vans vier Ve ig = 2m os_[-v Veo = Min es 6m, oa fv) n= 20k orp Va | Rea HIGH Vatage Guarariood hp Logkal HIGH 20 Vv Votage fora Inputs tas 1 and 2) Vi [rea Ow voroge ‘Gusrenieed Fp Logical LOW oe pv Voge or al inputs (Notes 1 and 2) Tix [ope HIGH Loskage Curont_| Viv= Vos, Veo = Max (Noto 9) To | va in| put COW Leakage Curont_[ Vin= OV, Voo = Max (cto) =o [ua Tox | Of-State Output Leakage | Vout = Vos, Veo = Max Curent HIGH Viv= Vier Vi (Note 3) noe ee Tox. | OF State Outnat Leatage | Vour = OV, Voo = Max FA Current LOW Vave Vitor Ve (Nota) a Teo ouput stoncrom Goren | VuvimesV Veo = Max (Noted) ee eo | Supply Curent ‘uiputs Open (aur=OmA) [1 =OMHa 15 La. Voc = Max r= 25 MAE 30[ ma ‘Noles: 1. These are absolute valves with respecte dave ground and all overshoots due to system r taster noo aro Included 3. 4 Reprncants th wore ate of HC and HCT standards. alowing comoatilty wit ether. 0 pin eakage ithe worst case of and oa. fr I ane la [Not more than one ouput shouldbe shared ata tine and duration of he short-cteuit shoud not exceed one second. Vour = 02 V has been chosen to avoks es problems caused by esr yruund degra 210 PALCE16VE2.25 (Com, ina) auo ZU CAPACITANCE (Note 1) Symbol” | _ Parameter Description Tost Conaition tye_|_ unt ‘Gn | put Gapactance Vin=20V | Voo=S0V, Tan de SL oF Guvr | Ouput capactanee Vour= 200] = 1 Miz o_o Note: 1 Thaso parameters are not 100% tested, bu are evaluatd at ial characterizaion and a any tine tha design ie meted nore capactance may be affected, SWITCHING CHARACTERISTICS over COMMERCIAL ond INDUSTRIAL operating ranges ote Parameter] Symbol | Parameter Dseroton tain] rox | une 120 | put or Feedback to Contnatoral Gap Note] [ae 1s | Setup Time tom iit or Foedoacko Clock 2 ‘s wae Tine ° 1 120 | Cockto stp io | oe Sock with = : # ww HIGH 8 a ‘un xara Feedback] Waa) wea aie tux | Frequency Intemal Feedback (lew) 0 Miz ome No Feedback [nisin 2 Mite a [Fe Oopa rate [ve ‘rz [OE w Ovput Disabe 25 |e {eh [put to Output Crabs Unig Plus Tor Conver | ten |lnputto Osput Disable Using Predict Term Conte =| ve Notes: 2. See Switching Test Creu for test condone, ‘3. This parameters tested in Standby Mode. When the device i notin Standby Mode, the 20 wi typically bo 2 ns faster, 44 Thaw parameters are not TuU% teste, but are evaluated. whore hequoncy maybe acted. at nal characterization and at any tine the dasign ks modified ‘PALCET6VE2-25 (Com', Ind) 2a Daw SWITCHING WAVEFORMS aa ve : 5 " restr ra w m to. ha cond oie ‘Supt we ‘Out, a a = combintral Output reaistred ouput vst we otek es = a a cioce with input to Output isebetenabe ‘anon {eo ouput Disabierenabie so 4, Vw 4 Vior hput signals and Voo2 fr output signal 2, Input gue amplitude 0 Vio 3.0 V. 2 Input om and a tne 28 ~5 tical aa PALGET6V8Z Family KEY TO SWITCHING WAVEFORMS aun 21 Saar eco we fomfitoL from Atel, Pommited” Unknown ee « ns ts ia =a mn |e « le lel. Le see ce | oe 3 PALCE16V8Z Family 2113 Dw TYPICAL lec CHARACTERISTICS FOR THE PALCE16V8Z-12/15 Veo = 5.0 V, Ta = 25°C 100 kee (ma) 75. ° 10 2 30 4 50 Frequency (at) 9061040 Ics. Frequency Graph for the PALCE16VEz-12115 The solocted"ypcal pattern uted 50% ofthe device resources. Hat ofthe macrocels were programmed as registered, and tha ether half worn pmgranmed as combinatorial. Half tha mvalabla prs tare wave ise for ach masteall On ay vector, ha ofthe ouputs were switching. _By utitzing 60% othe devo, 2 midpoint defined fore. From this midoit, adecigner may scale the lc graphsupor down to ‘estima holo requirements for a parculardesian. aaa PALCET6VOZ-12/16 auo ZU TYPICAL kc CHARACTERISTICS FOR THE PALCE16V8Z-25 Veo = 5.0 V, Ta = 28°C 150 125: recimay 30 2 el 2 0 5 1 1% mm 2% 0 9% 4 4 80 Frequency (MHz) soso lec vs. Frequency Graph tor the PALCE16v@2-25 Tho solectd *ypcapattrnulitzed 50% of the device resources. Hal ofthe macrocele wore programmed as registered, and the othr hall were programmed as combnatral Halo the avalable product orme wore used foreach masrecelt Of ary vector, hal ofthe oupute were switching {By teing 0% ofthe device, a midpoint dotined ore. From this midpoint designer may scale thee graphs upor down to ‘ostinato the le requirements for a particular desion PALCE16VEZ-25 Bats Dw ENDURANCE CHARACTERISTICS Tho PALCE*6VAzZ ie manufactured using AMD's ad ‘vanced Electrically Erasable process. This technology Endurance Characteristics uses an EE cello replace the fuse tink used in bipolar paris, AS a result, the device can be erased and Feprogrammed ~a feature which alows 100% testing at the factory. [symbot | Parameter Test Conditions Min Unit tea | Min Panern ata Rtoninn Time 10 Years Max Operating = Years Temperate TW | Win Roprograning Gye ermal Programing To yeas Condlione ROBUSTNESS FEATURES limits negative overshoot, eliminating the possibility of “The PALCE18V8Z has some unique features that make Itaxtramnly robust, axpacinly when operating in highe speed design enviconments. Input clamping circuitry INPUT/OUTPUT EQUIVALENT SCHEMATICS false clocking caused by subsequent ringing. A special ‘noise fiter makes the programming ccultry completely Insensitive 19 ary posilve overshoot al has & pulse width of ess than about 100 ns. veo eo tpa “a” Doan {Praag J Seite, |_[pegacnra cate oe PCS Type put — Prov Protecion and Camping es ESD Proload Feedback Input + Gicuity “Input Teanstton Detection ‘Typical Output ne aE PALCEI6V8z Family POWER-UP RESET “The PALCE16V87 has boon designed withthe eapabi ly to reset during system power-up. Following power- up, al fip-fops wil be reset fo LOW. The output state willbe HIGH independent ofthe logic polarity. This fea- {ure provides extra flexibly tothe signer ands espe-

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