LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUIT

SEQUENTONAL LOGIC CIRCUIT

DESIGN PROCEDURE
THE PROBLEM IS STATED
INPUT |& OUTPUT VARIABLES ARE DETERMINED
INPUT & OUTPUT VARIABLES ARE ASSIGNED
LETTER SYMBOLS
TRUTH TABLE IS DERIVED TO DEFINE THE
RELATIONSHIPS B/W INPUTS & OUTPUTS
THE SIMPLIFIED BOOLEAN FUNCTION FOR EACH
OUTPUT IS OBTAINED
THE LOGIC DIAGRAM IS DRAWN

CONSTRAINTS FOR
A PRACITAL DESIGN
MINIMUM NUMBER OF GATES
MINIMUM NUMBER OF INPUTS TO A GATE
MINIMUM PROPAGATION TIME OF THE
SIGNAL THROUGH THE CIRCUIT
MINIMUM NUMBER OF INTERCONNECTIONS
LIMITATIONS OF THE DRIVING
CAPABILITIES OF EACH GATE

COMBINATIONAL LOGIC

n INPUT
VARIABLES

CIRCUIT

m OUTPUT
VARIABLES

BLOCK DIAGRAM OF A COMBINATIONAL CIRCUIT

ADDERS
HALF ADDERS

S = x y + x y

C = xy

x
0
0
1
1

y
0
1
0
1

C
0
0
0
1

S
0
1
1
0

x
y

x
y
x
y

(a) S = x y + x y

C=xy

x
y
x
y
x
y

(b) S = (x + y) (x + y)

c=xy

x
y
S

x
y

(c)

S = (c + x y)

x
y
x
y

C=xy

C
(d) S = (x + y) . (x + y)

C = (x + y)

X OR
x

S=x y

C=xy
VARIOUS IMPLEMENTATIONS OF A HALF ADDER

FULL ADDER

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

c
0
0
0
1
0
1
1
1

s
0
1
1
0
1
0
0
1

yz
x
0
x
1

00

01
1

11

10
1

1
z

S = x y z + x y z + x y z + xyz

yz
x
0
x
1

00

01

11

10

1
1

1
z

C = x y +xz + yz

MAP FOR FULL ADDER

x
y
z

x
y

x
y
z
x
y
z
x
y
z

z
S=xyz+xyz+xyz+xyz

C=xy+xz+yz

IMPLEMENTATION OF FULL ADDER IN SUM OF PRODUCTS

x
y

c
z
IMPELEMENTATION OF A FULL ADDER WITH TWO
HALF ADDER AND AN OR GATE
S = z (x y)
= z(x y) + z (x y)
= z (x y + x y) + z (xy + xy)
= z (x y +x y) + z(x y + x y)
= x y z + x y z + x y z + x y z

c = z(x y + x y) + x y
= x y z + x y z + x y
= x y z + y (x z+ x)
= x y z + y [ (x + x) (x + z)]
= x y z + y (x + z)
= x y z + x y + y z
= z ( x y + y) + x y
= z[( x + y) ( y + y)] + x y
= z (x + y) + x y
=xz+yz+xy

Half subtractor
X

D = x y + x y
B =x y

D=x -y

x
D
y

Full subtractor
X

yz
00

D=xy-z

y
01

11

0
x

10

1
z

D = xyz+xyz +
xyz+xyz

y
x
o

yz 00

01

11

10

1
z

MAPS FOR FULL- SUBTRACTOR

D= xyz+xyz+xyz+xyz
B = xy+xz+yz

B =xy+xz+yz

Full subtractor
x
y

D=z(xy)
D=z(xy+xy)+z(xy+xy)
D=xyz+xyz+z(xy+xy)
D=xyz+xyz+xyz+xyz

B=z(xy+xy)+xy
B=z(xy+xy)+xy
=xyz+xyz+xy

B=xy+xyz+xyz
= x(y+yz)+xyz = x(y+y)(y+z)+xyz = x(y+z)+xyz
= xy+xz+xyz = xy+z(x+xy) = xy+z(x+x)(x+y)
=xy+z(x+y) = xy+xz+yz

Code conversion
Input

Output

BCD

Excess-3 code

Z=D
Y=CD+CD=CD+(C+D)

x=BC+BD+BCD = B(C+D)+BCD
W=A+BC+BD = A+B(C+D)

Truth table for code-conversion example

Z=D
y=CD+CD=CD+(C+D)
X=BC+BD+BCD=B(C+D)+BCD
=B(C+D)+B(C+D)
W=A+BC+BD=A+B(C+D)

AB
00

01

CD
00

C
01

11

C
10

AB
00

CD
00

01

11
1

1
01

10

1
1

B
11

B
11

10

A
10

D
Z=D

D
Y =CD+CD

AB

CD
00

C
01

11

10

AB
00

00
1

01

CD
00

01

01

11

10

B
11

B
11

10

A
10

D
X=BC+BD+BCD

D
W=A+BC+BD

MAPS FOR BCD-TO-EXCESS-8 CODE CONVERTOR

C
D
B

B
C

F=A(B+CD)+BC
(a) AND / OR Implementation

AND
1

OR
3

B
A
B

AND

AND

4
2
C

OR
5
(b) Substituting Equivalent NOR Functions

C
D

4
A
B
C

(c) NOR implementation

Implementation of F = A (B+CD ) + BC with NOR gates

(Block Diagram Method)

Analysis Procedure
C
D

T1
1
T3
3

T4
4
A
B
C

T2

T5
5

Method 1 : Algebraic manipulation

T1 = (C +D) = CD
T2 = (B + C) = BC
T3 = (B + T1) = (B + CD) = B (C + D)
T4 = (A + T3) = [A + B (C + D] = A (B + CD)
T5 = (T4 + T2 ) = [A (B + CD) + BC ]
F = (T5) = [{A(B+CD)+BC}]

Method 2 Derivation of the truth table

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

T1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1

T2
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0

T3
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0

T4
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1

T5
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0

F
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1

Method 3 : Block Diagram Transformation

F = (A+B+C)

A
B
C

C
D

A
B
C

F = A+B+C=(A+B+C)

A
B

C
F = (A+B+C) + BC

(a) NOR Logic diagram

C
D

A
B
C

(b) Substitution of invert AND symbols in alternate levels

C
D

F = A(B + CD) + BC

A
B
F
C
(c) AND OR Logic diagram

Conversion of NOR logic diagram to AND - OR

F=x

F = x y = x y + x y

x
y

y = x y + x y

x
y

y
(a) With AND OR NOT gates (X-OR Implementation)

[x ( x + y )] = x + x y
x

[ ( x + x y)( y + x y)]
= x (x + y) + y (x + y) = xy+xy
x+y

[ y (x+ y)] = y + x y

(b) With NAND gates (X-OR Implementation)

Exclusive OR implementations
CD

AB

00 01 11 10

00

01 1
A

11

(a) F=A B C D
F= (1,2,4,7,8,11,13,14)
(0s and 1s are odd)

01

1
1

00 1

1
1

10 1

AB

00 01 11 10

1
1

11 1
10

1
1

1
D

(b) F=A B
C
D
F= (0,3,5,6,9,10,12,15)
(0s and 1s are even

Map for a four-variable (a) exclusive-OR function and (b) equivalence function

BC
00

01

A 1

11

A0

00

10

A0

A 1

(1s are odd)

For Table (b)

(A B C) = F= A B
B

C)= A

11

10

1
1

1
C

F= A B C = A

(A

01

(a)

BC

BC

Map for three-variable functions

Uses of X OR AND
(iv) Arithmetic operations
(v) Error- detection & error-correction codes

F= A B C = A
(1s are even)

BC

Odd-parity generation
Three-bit
messages

Parity-bit
Generated

Logic diagrams for parity generation and checking

x
y

Note : Parity checker can also be used as parity

generator by Keeping input at 0 and making
output as p

z
(a) 3-bit add parity generator

P= x y

x
y
C
z
P

C= x
(a) (b) 4-bit odd parity checker

ODD-PARITY CHECK
Four- bits received

Parity-error
check