Code of register file

module regfile (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);

input clk, write;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
output [3:0] dataA;
output [3:0] dataB;
reg [3:0] regf[6:0];
reg [3:0] dataA;
reg [3:0] dataB;

always @(posedge clk)

begin
if(write)begin
regf[wadd] = wdata;
end
else begin
dataB=regf[raddB];
dataA=regf[raddA];
end

end
endmodule

Code of the circuit to solve A*B+C*D+E*F using 1 adder and 1

multiplier

module ocircuit (ooutp,s0,s1,clk,write,raddA,raddB,wadd,wdata);

output [9:0] ooutp;
input clk, write,s0,s1;
input [2:0] raddA;
input [2:0] wadd;
input [2:0] raddB;
input [3:0] wdata;
reg [9:0] ooutp;
wire [3:0] dataA;
wire [3:0] dataB;
reg [9:0] inner=10'd0;
regfile y (dataA,dataB,clk,write,raddA,raddB,wadd,wdata);
always @(negedge clk) begin
if (s0==0&&write==0&&s1==0) begin
inner <=(dataA*dataB);
end
else if (s0==1&&write==0&&s1==0) begin
inner <= (dataA*dataB)+inner ;
end
else begin
inner=inner;

end

if (s1==1)begin
ooutp<=inner;
end
else begin
ooutp<=10'd0;
end

end
endmodule

State diagram

S0= input 1
S1= input 2
S2= input 3
S3= input 4
S4= input 5
S5= input 6
S6= A*B
S7= reg+(C*D) save the result again to reg
S8= reg+(E*F) save the result again to reg
S9= Give the value in reg at output

Code of state Machine

module state (out, reset,in, val,clock);
input reset,in,clock;
input [3:0] val;
output [9:0] out;
reg [3:0] state;
wire w;
assign w = (~(state[0]&state[1]&state[2]))&(~state[3])&(~((~state[0])&state[1]&state[2])) ;
wire [2:0] rA;
assign rA=((state-3'd6)*3'd2);
wire [2:0] rB;
assign rB=((state-3'd6)*3'd2)+3'd1;
wire s00;

assign s00=(state[3]&(~state[0])&(~state[1])&(~state[2]))|((~state[3])&(state[0])&(state[1])&(state[2]));
wire s11;
assign s11=state[3]&state[0]&(~state[1])&(~state[2]);
reg clk;

ocircuit y (out,s00,s11,clk,w,rA,rB,state,val);

parameter zero=4'b0000, one=4'b0001, two=4'b0010, three=4'b0011,four=4'b0100 ,five=4'b0101 ,

six=4'b0110 , seven=4'b0111, eight=4'b1000, nine=4'b1001, ten=4'b1010;
always @(posedge clock or posedge reset) begin
if (reset)
state=zero;
else
case (state)

zero:
if(in)
state=one;

else
state=state;

one:
if (in)
state = two;

else
state = state;

two:
if (in)
state = three;

else
state = state;

three:
if (in)
state = four;
else
state = state;

four:
if (in)
state = five;

else
state = state;

five:

if (in)
state = six;

else
state = state;

six:

state = seven;

seven:

state = eight;

eight:

state = nine;

nine:

if (in)
state = zero;

else
state = state;

endcase

clk=0;
#40
clk=1;
#40
clk=0;

end

endmodule

Code of test bench

module test_statemachine();
reg in,reset,clock;
reg [3:0] val;
wire [9:0] out;
state z (out, reset,in, val,clock);
initial
begin

clock =1'b0;
#10
clock =1'b1;
in=1'b0;
reset=1'b1;
val=4'd5;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd2;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd1;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd2;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd3;
#100

clock =1'b0;
#10
clock =1'b1;

in=1'b1;
reset=1'b0;
val=4'd2;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd5;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd5;
#100

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd5;
#100
clock=1'b0;

clock =1'b0;
#10
clock =1'b1;
in=1'b1;
reset=1'b0;
val=4'd5;
#100
clock=1'b0;

end
endmodule

Simulation result
For A=5,B=2,C=2,D=1,E=3,F=2