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Introduction
A chip for inductive battery charging is presented, which needs no
external components except an antenna to capture the energy from an
electromagnetic field. The integrated system blocks are a front-end to
limit and rectify the induced alternating voltage and a charge regulator
with three control loops for the current, the voltage and the
temperature.
The external antenna forms a resonance circuit with the on-chip
capacitor. The resonance frequency of the front end is 13.56 MHz, so
it is compatible to the well known smart-card standard. In the
electromagnetic field of commercial reader systems the chip produces
an output current to charge a lithium battery with the mandatory
constant-current-constant voltage (cccv) charge profile This
architecture is implemented to charge lithium cells at a current of 4
mA up to a cell voltage of 4.2 volts. The target application are highend smart-cards with secondary batteries.
The chip, fabricated in a 0.8 m BICMOS-technology, includes two
contacts for the antenna and two for the battery. The operating current
of the IC is approximately 1 mA.
Transmitter Block
Voice
Signal
Base
Station
User 1
Electric
Signal Of
DC Power
Supply
V/F
Converter
Frequency
mixer
Transmit
signal
Receiver Block
Receiver
signal
Frequency
Voice
Signal
For mobile
speaker
Separator
Frequency
Of
Electric
Signal
F/V
Converter
Mobile
Battery
Carger
CHARGING SYSTEM
Charging profile
Voltage limiter
Integrated circuits work only in a limited voltage range, so special protection circuits are
used. For commercial ICs this range is e. g. 4.5V
the voltage is regulated by an NMOS transistor, controlled by an amplifier. This
transistor regulates the maximum voltage indirectly by shortening the current.
Advantages
Its provide more battery backup
Power theft protection.
It provide emergency power
Less infrastructure cost
Application
Wireless mobile charging
Electrical and Electronic device can charge wireless
We can use in ruler area
Conclusions
An fully integrated inductive charging system was presented in this paper. There are no
external components required except the antenna for charging. The charge current for the
battery was 4 mA. For the reader and the antenna standard components has been used
Implementing this charging system in smart-cards high performance devices with various
applications become possible. By the use of rechargeable accumulators, the lifetime of
the card is not limited to the capacity of the battery as it was with active cards and
primary batteries.
1. HARDWARE DESCRIPTION
RESISTORS:
These are current resisting devices.These are made of
carbon, metallic wire wound etc. These are read through this
acronym
BBROYGBVGW. This
stands
for, Black,
Brown,
Red,
lines
indicate
the
number
corresponding
to
color. The
numbers indicated by the colors are shown in table below. The third
line indicate the number of zeros, the fourth line indicate the
percentage of tolerance of the resistor.
BLACK
BROWN
RED
ORANGE
0
1
2
3
E.g.
Brown
YELLOW
GREEN
BLUE
VIOLET
4
5
6
7
GRAY
WHITE
Gold
Silver
8
9
5%
10%
22K; Red, Red, Yellow = 220K ; Red, Red, Green = 2.2M ; Red,
Red, Yellow = 22 M
These are available in various wattages like 1/4W, 1/2 W,
1W, 2W, 5W, 10W, 20W, 50W, 100W, 200W. In electronics most
common use are up to 5Watt.Higher the wattages bigger the sizes.
The value and wattage of resisters are to be selected as per the
applications. The tolerance in variation of the rated value is also
selected as per the applications. The resisters are
fabricated
DIODES:
These
devices
allow
to
flow
current
in
only one
germanium diodes have 0.3 voltage drop. The different diodes are
used for different purposes.
Current
Voltage
Diode Symbol
ideal curve
Current
Forward Region
Break Down Voltage
Voltage
Diode Characteristics:
Diodes are of different types like Photodiode, Varactor
diode, Schotkey Diode, PIN diode, Zener Diode etc.
Zener Diode:
Small signal and rectifier diodes are never operated
in
the break down region because this may damage them. The zener
diode is made to operate in breakdown region, sometimes called
breakdown diode. The zener diode is the back bone of voltage
regulators, circuits that hold the load voltage almost constant
despite large changes in the line voltage and load resistance.
TRANSFORMERS:
This are the devices which converts the primary ac
voltage to different secondary ac voltages .If the secondary voltage
is higher then primary voltage then the transformer is called step up
transformer, if the secondary is less then primary voltage then it is
called step down transformer , if secondary is same as primary
voltage then it is called unity transformer. This unity transformer is
also used as isolation transformer . These devices are highly
efficient unto 99.9%, i.e. very low power loss.
The transformers are required for making dc supply,
tuning circuit etc. The current rating of primary and secondary
winding determines the SWG gauge
POWER SUPPLIER:
The Power is given to the transformer, which steps down
the input voltage to 10 times less i.e. 20 V.
78M05
Transformer
Rectifier
Filter
Regulator
CAPACITORS:
This are the storage devices but has in built Resistance
thats why the storage voltage does not last for longer period. The
use of capacitor is for tuning the circuit, filtering the noise to
ground, creating the timing pulse as in our case. The capacitors
cannot be fabricated on ICs because of the technical difficulty.
The different values of capacitor that are available are
1pf, 2pf, 2.2pf, 100pf, 200pf, 1000pf, 0.001uf, and 0.01uf, 0.1uf, 2uf,
10uf, 22uf, 33uf, 47uf, 56uf, 68uf, 82uf, 100uf, 220uf, 330uf etc. The
capacitors are selected based on capacitance and voltage rating.
Higher the voltage higher the size of the capacitor. These are
available in following types.
Electrolytic Capacitor :
These
capacitors have
electrolyte
as the dielectric
between the two plates. These are available with polarity + and
-.These are available with vertical mount or horizontal
mount
configuration.
Paper Capacitor :
These
capacitors
are
available
in
low
range
of
Mica Capacitor :
These capacitors are also available in low range of
capacitance. The mica is used as dielectrics media between the two
plates.
Disc Capacitor :
These are available from 1pF to 1ooooUF.
RELAYS:
Relays
the
era
of
microprocessor,
circuit
were
constructed using desecrate logic like various gates, counters, flipflops, decoders, monostables and registers. Circuit diagram was
designed
as
per
the
requirement
prototype
PCB
is
made
it
was
possible
to
design
such
device
called
Intel
introduced
MCS-51
series
there
were
is 256 byte internal RAM which is always in side the chip & is called internal
RAM. Industrial application with moderate complexity can be fitted inside the 4K
of ROM. The 256 byte internal RAM is divided into two equal parts of 128 byte
each. The upper half, from location 128 to 256 is reserved for special purpose
registers & is called SFR area. If program demands extra ROM, one can use
higher version, the 89C52 which has on chip 8K ROM. Next higher version is
also available. Next higher version is also available. The 89C55 has 20K of on
chip ROM. If the program is written in assembly language, 4K ROM of 89C 51 is
more then sufficient for most of the application.
Overview of 89C51
PIN CONFIGURATION
89C51 is a 40 pin device. Two pins are used for power supply,
and require +5V. It has on chip oscillator circuitry to which requires
Fig2
pin configuration
BIT
BIT
ADDRESS
ADDRESS
90H
P1.0
91H
P1.1
2P
P 39
P0.0 80H
92H
P1.2
3O
O 38
P0.1 81H
93H
P1.3
4 R(90n)
(80n) R 37
P0.2 82H
94H
95H
96H
97H
P1.4
P1.5
P1.6
P1.7
RESET
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
XTL1
XTL2
GND
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
T
1
RXD
TXD
INT0
INT1
T0
T1
WR/
RD/
VCC
T 36
P0.3 83H
35
P0.4 84H
0 34
P0.5 85H
33
P0.6 86H
32
P0.7 87H
31 EA/VP
VCC
P 30
ALE
O 29
PSEN
RDOF ROY
R(Bon) 28
P2.7 A7H
T
P 27
P2.6 A6H
O 26
P2.3 A5H
3(A0n) R 25
P2.4 A4H
T 24
P2.3 A3H
23
P2.2 A2H
2 22
P2.1 A1H
21
P2.0 A0H
All the port pins are said to be Bit addressable. The bit addressable
RAM is a new concept. If the RAM location is
in
individual bit has unique bit address. Refer to fig. 2 for pin configuration and bit
addressable concepts. Bits in the bit addressable RAM can be addressed by
their bit address or in the dot notation. The bit address for pin, port 0.0 is 80 hex,
port 0.1 is 81 hex, port 0.2 is 82 hex and so on. The bit address for pin port1.0 is
90 hex, port 1.1 is 91hex,port 1.2 is 92hex and so on. Please note bit address
and port address are different 80 hex bit address means port P0.0 and 80 hex
internal RAM address means port 0 as a complete. There are separate
instruction for addressing bit and byte it is the instruction which decides weather
bit is addressed or byte is addressed 89C51 has instruction to clear the bit ,set
the bit, compliment the bit
OR
a port pin P3.4 and P3.5 these pins are labeled T0 and T1
respectively
If external ROM or RAM has to be interfaced then port 0 is used as 8
bit multiplexed AD bus. AD0
Addressed
generate strobe for latching lower order address byte. Port pin P3.6 and P6.7 are
connected to WR and RD/ for external RAM.
From the practical point of view, we can say that 89C51 has 4K on
chip Flash ROM and 256 byte of on chip RAM called internal RAM plus it has two
timer/ counter module, serial interface, four 8-bit ports, interrupt handling logic as
standard feature. It can also address 64K external RAM , and /or remaining 60K
of external ROM. But as many as 80 pins are used to interfacing external
memory. As so many pin are lost in interfacing, design using these external
memory are not preferred if one needs more RAM one can use serial EEROM ,
which are more economical, and used 3 lines for interfacing.
89C51 has wonderful features it has multiprocessing mode in this
mode, there is one master 89C51 and nos of other slave 89C51 master can
communicate with the slave 89C51,sharing the common serial bus, without
disturbing other 89C51 even though they are connected to common serial bus.
This feature is quite advanced. We just mention that chips in the MCS-51 have
multiprocessing capability and is not advised to go into details of it unless person
gathers basic skill in programming.
INTERRUPTS
We have seen earlier that many times, processor has to
respond to event happening real time world. The event may take place at any
time. Interrupts handling logic is incorporated inside the chip, for this purpose. In
such a case, Processor will suspend current execution of the program, & branch
to interrupt service routine. After finishing, it will resume the suspended work.
The situation can be seen very frequently, in our every day life.
Suppose a person is busy in doing some work, say writing a letter and all of a
sudden telephone ring. Then the person will stop writing the book, ans. the
telephone, & resume the writing the book. Some time there are 4,5 telephone
lines are available. In that case he may have to decide about to priority, in
answering the phone. Some times he himself is very busy in imp. meeting,& does
not want to get disturbed by the phone calls. All this types of situations exist in
microprocessor world also.
Those of you who are familiar with 8085 will recall that 8085 can
handle 5 different interrupts. 89C51 can also respond to 5 different interrupting
lines, equivalent of having 5 telephone lines. Two are external interrupts they are
called INT0, INT1 at port pin P3.2 & P3.3 respectively. If these interrupts are
activated & enable in software the program will branch to location 0003 & 0013
hex of program memory (ROM). 89C51 have two timers/counter modules. These
counters are UPCOUNTERS only. When counting starts, during the course of
counting whenever they overflow from FFFF to 0000, timer overflow flag, TF0,
TF1 is set, & interrupts are generated. If the interrupts are enable in software
then the will branch to location 0000bB hex. and 0001B hex respectively. 89C51
has built in serial interface. Whenever serial data is received, Receipt Interrupt
Bit RI is set and whenever data is fully shifted out Transmit
Interrupt bit TI is set. The RI & TI together generate one interrupt, called serial
interrupt. If this interrupt is enabled in software then the program will branch to
location 0023 hex. In ROM memory. The interrupt handling logic of 89C51 can be
explained with the help of following figure -
The external INT0 and INT1 can be defined as either negative edge
triggered or level triggered this means if interrupt is defined as negative edge
triggered interrupt will be generated whenever negative edge is detected on INT0
or INT1 line or if interrupt is defined as level triggered then interrupt is active as
long as INT0 or INT1 is held low. The bits IT0 interrupt type zero and IT1 interrupt
type one will decide whether the interrupt is defined as edge triggered or level
triggered. If the byte 0 then corresponding interrupt is level triggered and if the bit
is 1 then it is edge triggered. These bits are found in TCON register in the SFR
area of the internal RAM and its address is 88hex.
EA
-----
ET2
ES
ET1
EX1
ET0
EX0
There is interrupt enable register IE. The bits in the register IE will
decide which interrupts are active or in built. The MSB it of the IE register is the
global enable bit labeled as EA. If this bit is 1 mean interrupt are enabled and if is
0 then all interrupts are disabled. Other bits in the IE register will enable if they
are 1 or disable if they are 0, the individual interrupts. The interrupt enable
register IE has a place in SFR area and its address is A8 hex. It is a bit
addressable register.
There is a provision to decide the priority of the interrupt either
high or low. The priority can be defined in the register IP, interrupt priority register
the address of the register is B8 hex in the SFR area. It is a bit addressable
register if lower priority interrupt work is in progress and higher priority interrupt
arrives. Then lower priority interrupt work will be suspended processor will branch
to higher priority service routine after finishing higher priority work he will resume
the execution
priority
PT2
PS
PT1
PX1
PT0
PX0
will start the execution of the service routine. It is then hardwires and /or
programs responsibility to see that pin INT0or INT1 who has cased the interrupt
goes high so that bit IE0 or IE1 will be cleared if INT0or INT1 is not cleared then
program will again enter into the same service routine. Mostly this interrupt are
defined as edge triggered mode only. If they are defined as edge triggered then
the bit IE0 or IE1 will set whenever negative edge is detected and the bits will
automatically get cleared when program branches to respective interrupt service
vector.
Timer over flow bit TF0 or TF1 will set, whenever counter over flow
from FFFF
Diagram
The two register TL0 &TH0 will form 16 bit counter.TL0 & TH0 are
the registers & have place in the SFR area. Their location is 8A hex. & 8C hex.
respectively. They are not bit addressable. The counters are used in UP counter
mode only. While counting UP, whenever it will overflow from FFFF hex. to 0000,
the bit TF0 will set. The switch in the small box will pass the pulses to the
counter. Pulses will be passed to counter if out of the AND gate is high. The AND
gate has to input, one is bit TR0 & another is connected to the output of the OR
gate. The OR gate has again 2 input. One is Inverted GATE0 bit &other is
connected to PORT3 Pin P3.2, the INTO. The counter can count the pulses
coming from internal oscillator after division by 12 pulses appearing at Port 3 Pin
P3.4, the T0.The bit C/T0 will decide this.
The bits GATE0, C/T0 of TIMER0 & corresponding bits of TIMER1
the GATE1 & C/T1 are found in register TMOD located at address 89 in the SFR
area. This TMOD register is not bit addressable. The bits TR0, TF0 of TIMER0 &
corresponding bit TR1 & TF1 of TIMER1 are found in the register TCON locate at
address 88 hex. in SFR area. It is a bit addressable register .
GATE
TF1
C/T
TR1
M1
TF0
M0
TR0
GATE
IE1
C/T
IT1
M1
IE0
M0
IT0
89H
88H
service routine to reload TH0, TL0. The above mode is called 16 bit counter
mode. This mode is called MODE1.
There is one more mode called MODE2, the 8-Bit Auto Reload
Mode, which is also used very commonly. In this mode counting is done in
register TL0, so it is 8 bit counter mode. After overflow from FF hex. to 00, the
TF0 bit is SET. At the same time data in the register TH1 will be automatically get
copied or reloaded in to register TL0.The register TH0 set to holds the auto
reload count. This will ensure that interrupt will arrive exactly after same time
interval. All other logic will remain same.
The bits M0 & M1 in the TMOD register will set the mode. If both
the bits are 0 then MODE0 is selected. If exactly same as MODE1, except
counting is done 13 bit instead of 16 bit. If the bits are 0 1 then MODE 1, the 16
bit counter mode is selected. This mode we have seen above. If the bits are 1 0
then MODE2, the 8-Bit AUTORELOAD mode is selected. If this bits are 1 then
MODE3, special mode is selected. In this mode TIMER1 is temporally halted.
TL0 & TH0 are used as separate 8 bit counters. Counting logic for TL0 is same
as in case of MODE2. But all control bits of TIMER1 are now diverted for
counting of 8- Bit into TH0. This mode is not used in practice very much because
of the involved complexity.
COMPONENT LIST
SN
1
2
3
4
5
6
7
8
9
10
COMPONENT
IC Base
IC Base
IC1
IC2 & IC3
Crystal
Relay
Regulator IC
Regulator IC
Transistor
Resistor
11
Capacitor
TYPE
40 PIN
20 PIN
89C51
74245
11.0592 MHz
12v D.C.
7805
7812
BC547
10k,1/4W
4.7k,1/4W
1k,1/4W
33pf
12
13
14
LED
Switch
Diode
7000 microF/25v
47 microF/50v
100 microF/25v
Red
Micro
1N4007
18
Transformer
19
Lead Wire
6-0-6/750mA
6-0-6/250mA
QUANTITY
1
2
1
2
1
5
1
1
5
20
5
1
2
1
1
1
10
5
1
15
1
1
1
The interface IC1 and IC3 are connected to ports P1 and P0 respectively. The I/P
of IC1 i.e. pin 2 and pin 9 to which sensors can be connected. The pins of IC3 i.e.
pin 18 to pin11 are output pins. The output from P0.1 is fed to relay driver which
sends the command to delay the stored number to communication system. The
output from P0.2 is fed to relay which remove the connection from cradle. The
command is also fed to the circuit which starts the play of recorded message.
3. PCB LAYOUT
FRONT SIDE
REAR SIDE
CHAPTER IV
SOFTWARE DEVELOPMENT
FLOW DIAGRAM
ASSEMBLY LANGUAGE PROGRAM
HARDWARE DEVELOPEMENT
1. SOFTWARE DEVELOPMENT
Gone are those tiresome, exhausting days when one has to code,
the program manually on the paper, calculate jump address. Enter the code
manually in the kit. Execute the program on kit. Change the platform. Again code
it for target board. With he revolution in software industry, powerful simulator
packages are available, so the use of kit is outdated. The Development process
in any language is consisting of various stages. The tools and the stages in
developing program in Assembly Language are as follows. All the stage and
steps are taught in the Microcontroller Training program in detail.
Editor-
Assembler-,
Simulator-
will run the program on the computer and give us the result as if
2. HARDWARE DEVELOPMENT
PREPARATION OF THE PCB
Schematic Preparation
Schematic
either
circuit
is made otherwise
The schematic
is
drawn
single
with
layer
colored
then
multi layer
schematic
pen
is made .
to indicate
the
transparent
acrylic
on a paper, same is
plastic sheet
. This
circuit
is
size
different
of the
color tapes
desired
PCB .The
to identify
artwork is
drawn
with
and
gets
dissolved
remains intact
etching
in the
operation
solution
in the
the exposed
whereas
unexposed
copper
in
of the drills
should
the components
not be
either more
then the required or less then the required . If the hole is large the
it will be difficult to solder and lot of lead will be consumed. If the
hole is small then component will not be inserted easily.
Tinning of pcb
The PCB is tinned after putting the mask on PCB
.This
is done to insulate
the
any
short. The
PCB TESTING
PCB is checked
soldering.
with a
, they
are soldered