----------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date: 10:44:52 04/09/2015
-- Design Name:
-- Module Name: deber_if - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity deber_if is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
x : inout STD_LOGIC;

y : inout STD_LOGIC;
z : out STD_LOGIC);
end deber_if;
architecture Behavioral of deber_if is
begin
process (a,b,c,d)
begin
if(a='0' and b='0' ) then
x<='0';
else
x<='1';
end if;
if(c='0' and d='0' ) then
y<='0';
else
y<='1';
end if;
z<=x and y;
end process;
end Behavioral;
Reading design: deber_if.prj
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HDL Compilation
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Compiling vhdl file "C:/Documents and
Settings/user/Escritorio/DeberCristianVeloz/CristianVeloz_if/eber_if.vhd" in
Library work.
Entity <deber_if> compiled.
Entity <deber_if> (Architecture <Behavioral>) compiled.
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*
Design Hierarchy Analysis
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Analyzing hierarchy for entity <deber_if> in library <work> (architecture
<Behavioral>).
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*
HDL Analysis
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Analyzing Entity <deber_if> in library <work> (Architecture <Behavioral>).
Entity <deber_if> analyzed. Unit <deber_if> generated.

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*
HDL Synthesis
*
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Performing bidirectional port resolution...
Synthesizing Unit <deber_if>.
Related source file is "C:/Documents and
Settings/user/Escritorio/DeberCristianVeloz/CristianVeloz_if/eber_if.vhd".
Unit <deber_if> synthesized.
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HDL Synthesis Report
Found no macro
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*
Advanced HDL Synthesis
*
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Advanced HDL Synthesis Report
Found no macro
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*
Low Level Synthesis
*
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Optimizing unit <deber_if> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block deber_if, actual ratio is 0.
Final Macro Processing ...
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Final Register Report

Found no macro
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*
Partition Report
*
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Partition Implementation Status
------------------------------No Partitions were found in this design.
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*
Final Report
*
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Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.236ns
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Process "Synthesis" completed successfully