2.

5
otorola 68000.

DB

AB

AS

R/W /

UDS, LDS

DTACK

FC0-FC2

()

IPL0-IPL2

BERR (bus error)

HALT

RESET

CLK

BR (bus request)

BG (bus grant)

BGACK

E ()

VMA

VPA

Vcc, GND

 68000 (exceptions interrupts)

. 68000 ,
(Supervisor mode) (User mode).
:
68000 .
,
( ,
68000 ),
68000 User mode ( User mode
),
.
,
. (..
( ), , call OS
utility routines (TRAP instructions, ) ),
.
Trace (
), ISR (debugging
routine) .

E , ,
(IPL0-IPL2) ,
bus (low) BERR,
RESET.

(
).

RESET
BERR

Trace mode
(IPL0-IPL2)
/

TRAP/TRAPV
CHK
o

(

)

RESET
BERR

Trace mode
(IPL0-IPL2)
/

TRAP/TRAPV
CHK

(

)

( Reset, bus error

address error)
,
.
.
,
,
.

 68000 :

A (autovectored interrupts)
(vectored interrupts)
(non-maskable interrupts, )

interrupts)
(traps)

(restartable

,
(interrupt acknowledge cycle) DB 68000,
byte
,
. 68000

.
, IPL0-IPL2
7 ( ,
7 )

 , 1024
256
Program Counter (32 bit) 68000
.
256 ( 4 bytes )
System Stack Pointer (SSP)
Reset.
M 64 ,
192
( vectored interrupts autovectored interrupts) .

IPL0-IPL2
(auto- vectored vectored interrupts).
O 68000 IPL0-ILP2
bit SR.
IPL2-IPL0
bit SR, .

 ,

:

SR (IntReg).
S-bit SR 1, 68000 Supervisor mode.
T-bit SR 1, tracing
3 bit SR
IPL0-IPL2,

68000 (
).
slide

Program Counter , SSP

4.
SR (IntReg) Supervisor Stack, SSP
2.
Program Counter 4 bytes
.


,
:

(AS),
byte
.

byte
,

A1-A3

AB
IPL0IPL2
hardware (slide 12)

,
AB 0.
, FC0 - FC2=111
( )
DTACK
AS.

 (byte )
,
bits A23 A10 0, bit A1 A0. ,
bit 9 2 (8 bit ) byte
DB.
PC
,
.

 68000 :
) Priority encoder (PE) to serve 7 peripherals
Source 1 : Vectored Source 6 : Autovectored
Source 7 : NMI
DMUX
1-3 (
,
. IPL0-IPL2)

(VNR)
DB.

A1-A3

DTACK

AVEC =0, Autovector

68000.

To IACK=0 FC0-FC2 =111 (slides 1,9,18).

AVEC VPA 68000 (slide 1).

) Parallel priority system for a number of peripherals

Group 2 : Refers to a Group of 8 Peripherals (sources 20 - 27). Their priority is
resolved by vectored interrupt through corresponding DMUX and PE.
INT of PE of group2 is connected to input 2 of global PE.
Output 2 of global DMUX to EN of DMUX of group2.
3 bit code from DMUX of group2 is decoded .
One of the peripherals is enabled (vector is delivered).

Global DMUX
A1-A3
Global PE

EN

Group2

Group2

) Daisy chain method.

Peripheral 41 has the highest priority in the chain.
IACK (output 4 of DMUX) as the daisy chain signal.
Additionally IACK blocks interrupts made during
the interrupt acknowledge cycle.
All INT of sources (41-43) to input 4 of PE.

A1-A3

Chain signal

) Polling
Peripherals 50-57 are wired OR to input 5 of the PE. The whole group is
identified as an autovectored interrupt.
Their relative priority is resolved through polling.
Group 6 is configured in autovectored mode.

A3-A1

 , ,

.

. ,
, ,
,
. ,
.
restartable interrupts.
68000, (bus error
-BERR- ),
(or memory, due to wait states)
bus (DTACK,
)

.

 BERR
, HALT,
RESET. BERR

MMU (Memory Management Unit)
(Virtual) .

.
, slide,

.

BERR ,

BERR HALT.
( ), ( )
(bus cycle rerun)
.
.

 68000 bus
, (
slide 8) . ,
:
SR (IntReg).
S-bit SR 1, 68000 Supervisor mode.
T-bit SR 1, tracing.
Program Counter , System
SP (SSP) 4, PC 32
bit.
SR (IntReg) Supervisor Stack, SSP
2, SR 16 bit.
Instruction Register, ( byte)

bus, Supervisor Stack SSP
2. slide.
Supervisor Stack
bus ( 32 bit SSP
4).
Supervisor Stack
bus , SSP 2.
PC

 BERR
Address error
Function code (FC0-FC2): User Program Memory
User Data Memory
System Program Memory
System Data Memory
Exception

 bus (DMA)
O 68000 system bus (SB)
, . ME

, bus .
68000
system bus :
Bus Request
(BR,
),
Bus Grant (BG 68000 )
Bus Grant Acknowledge (BGACK 68000, BG
SB).

(SB) .

2.6

Interface I/O. :
Local System bus (Local SB, CPU-Memory).
. H .
Backplane bus, ,
/ (.. VME bus)
I/O bus (expansion, external, host), SB
(PCI, USB, SCSI).

.
:
(expandable),
(on-the-fly). :PCI, USB, SCSI, PCMCIA
(non-expandable),
.. IIC, VME


, master/slave.
.. DMA ,
, .
interfaces .
,
.
,

.
,
.
(bus
arbitration).
,
, (Local System Bus)
(Global bus).

2.6.1
.
,
. ,
, .. DMA (DMAC).
(Local System Bus, Local SB)
(slide 19) :
BREQ (Bus REQuest),

BGT (Bus GranT),

BGACK (Bus Grant ACKnowledge).

.
,
.

O DMAC Local SB BREQ.

,
,
Local SB , DB CB .

O ME Local SB BGT.
DMAC Local SB. DMAC
Local SB BGACK.
BREQ. BGT. DMAC
,
. DMAC Local SB
BGACK. Local SB.

2.6.1.1 (central
serialized arbitration)
DMAC
daisy-chain,
BREQi
BREQ
wired-or . daisy-chain
BGT .

Local SB
DMAC
BGACK.

Local SB,
BGT
BGT . Local
SB BGACK. E
, BGT ( BGT
) ,
Local SB, BGACK .

( DMAC).

2.6.1.2 DMAC
) Burst mode (halt)
. (..)
/O. (
, CLK ) .
, .

) Cycle stealing (partly parallel)

1 2 .. TSC (Three State Control)
(1-4 ..) state 1 1 (
). 2 DMAC, 1
.
5s 2 bytes I/O ..
.

) Transparent (parallel by time multiplexed)

DMAC Local SB
(
DMAC).
. RAM .
CLKs (1 2 DMAC) duty cycle
.

 3-state buffers
DMAC
DMA Synchronization clock ( 1 2, duty
cycle =1).

Data

DMAC

2.6.1.3 DMAC
4 channel DMAC
Status register : busy/free
status for all channels
Command register : Mode
of operation, read/ write
Memory address register :

.
INC.
Byte counter :
bytes

2.6.1.4 Isolated buffer memory

( DMA)
( ) I/O (I/O buffer memory).
Interface I/O MUX.
, UX Interface I/O.
.
,
UX.

2.6.2 (Dynamic central parallel arbitration)

(Global Bus, GB)
( ,
I/O) ( ME (Local
SB), GB.
, GB
,
.
(bus arbiters- ).
GB.
2.6.2.1 Priority -based
slide

GB. PU0.
BREQ BGT ( global SB), :
AS (Address Strobe)
DBR (Device Bus Request)
BUSY

CE (Chip Enable)
DBG (Device Bus Grant)
LPRQ (Lower Priority ReQuest)

 MPU0
, AS.
,
, device bus request (DBR0)
(bus arbiter 0).
BREQ0 o
3--8.
,
BGT0. ,
BGTi

. i,
(ASi=1, CEi=1).
reset
BUSY. , (bus arbiter 0),
BUSY
. ,
device bus grant (DBG0). ,

BUSY. ,
.

 GB ,
, GB (
)
GB.
, GB

GB. ,
wired-or LPRQ (Lower Priority Request) BREQ.
, GB
LPRQ, BREQ,
BGT
, BGT
.
GB
(BCLK) .
Y
(LOCKi).

2.6.2.2 FIFO based

FIFO,
.
FIFO.

,
.

2.6.3 (Distributed arbitration scheme)

,
.

. ..
IIC

2.7 I/O Computer

DMAC
. /O ,
,
, ,
.
I/O
ME. .
I/O ME 8 16 bit
I/O
I/O ( /
)
DMA / SB .
(
) ,
.

/ /.

/.

 16 bit
I/O 8 bit, , ,
interfaces ( slide).
, o
I/O DMAC,

/



/. O DMAC


.
,

(dual
port
memory)

2.7.1
. I/O

 I/O,
(.. , , )
(.. ,
), .
/ , /
(..
).
O /
(System bus, SB).
,
dual port
/O. dual port,
I/O SB (interface to SB). H dual port RAM,
.
6 (semaphore
registers), dual port.

dual port /.

2.7.2 .
K 8-bit, bits
. bit 7 bit.
1, , (
/). bit 6
.
SB.

(mutual exclusion).

 test
Wait:

test X
bmi Wait
set X

;Test semaphore bit

;branch to Wait, if busy
;set semaphore bit

.
,
, set X
Indivisible read, test and indicate resource
allocation operation Non- interruptable Read modify write operation (
3 )

 , , Test
And Set (TAS) .
TAS (read) , (modify)

(write) bit , .

setting bit. :
Wait :

TAS X
BMI Wait

TAS
bit (bit 7) 0
bit . E .
bit bit. ,
bit 1,
, o .
T bits
. ,
. , bit 7
0.


, lock X unlock X.

( ).
unlock X bit 7

( dual port, /).
lock X bit. (
, ),
. ( ),

bit .
unlock X:
CLR X
lock X:
Wait
TAS X
BMI Wait

X<7>:=0
WAIT: if X<7>=1 then N:=1
Else N:=0; X<7>:=1;
If N=1 then goto Wait

2.7.3 (bus
masters) I/O
(slide 37) .
E
SB I/O.
(slide 46). () :
( , , ,
) dual port
/. () : / ,
, DMAC o
. () : , /,
dual port,
( "", ) M .

I/O.
dual port

(SYN1 SYN2)
. (EXCL)
M
/ /.

2.7.3.1 .

dual port /
EXCL. lock
( /)
, unlock .
SYN1 SYN2
dual port /.
unlock SYN1
/
. Lock SYN1
I/O .
unlock SYN2, /
.
Lock SYN2, .
EXCL, lock SYN 1 SYN2 . ,
,
( ).

(A) :

dual port
/.
(B) : /
,
DMAC
o
.
() :

,
/,
M