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Dspic30F3014, Dspic30F4013 Data Sheet: High-Performance Digital Signal Controllers
Dspic30F3014, Dspic30F4013 Data Sheet: High-Performance Digital Signal Controllers
Data Sheet
High-Performance
Digital Signal Controllers
Advance Information
DS70138C
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS70138C-page ii
Advance Information
dsPIC30F3014/4013
dsPIC30F3014/4013 High-Performance
Digital Signal Controllers
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the dsPIC30F
Programmers Reference Manual (DS70030).
DSP Features:
Dual data fetch
Modulo and Bit-reversed modes
Two 40-bit wide accumulators with optional
saturation logic
17-bit x 17-bit single cycle hardware fractional/
integer multiplier
All DSP instructins are single cycle
- Multiply-Accumulate (MAC) operation
Single cycle 16 shift
Peripheral Features:
High current sink/source I/O pins: 25 mA/25 mA
Up to five 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
Up to four 16-bit Capture input functions
Up to four 16-bit Compare/PWM output functions
Data Converter Interface (DCI) supports common
audio Codec protocols, including I2S and AC97
3-wire SPI module (supports 4 Frame modes)
I2C module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
Up to two addressable UART modules with FIFO
buffers
CAN bus module compliant with CAN 2.0B
standard
Analog Features:
12-bit Analog-to-Digital Converter (A/D) with:
- 100 Ksps conversion rate
- Up to 13 input channels
- Conversion available during Sleep and Idle
Programmable Low Voltage Detection (PLVD)
Programmable Brown-out Detection and Reset
generation
Advance Information
DS70138C-page 1
dsPIC30F3014/4013
Special Microcontroller Features (Cont.):
CMOS Technology:
48K
8K
16K
2048
2048
1024
1024
AC97, I S
CAN
dsPIC30F4013 40/44
24K
I2C
dsPIC30F3014 40/44
SPI
Output
SRAM EEPROM Timer Input
Codec A/D 12-bit
Comp/Std
Bytes
Bytes
16-bit
Cap
Interface 100 Ksps
Bytes Instructions
PWM
Pins
UART
Program Memory
Device
13 ch
13 ch
Pin Diagrams
40-Pin PDIP
DS70138C-page 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dsPIC30F3014
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
VDD
Vss
OSC1/CLKIN
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
INT0/RA11
IC2/INT2/RD9
RD3
Vss
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Advance Information
AVDD
AVss
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
Vss
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
RD2
VDD
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
RD2
VDD
VSS
RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
44-Pin TQFP
dsPIC30F3014
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKIN
VSS
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/CN7/RB5
AN4/CN6/RB4
NC
NC
AN10/RB10
AN9/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
RF0
VSS
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/RB12
AN11/RB11
Note:
Advance Information
DS70138C-page 3
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
RD2
VDD
VSS
RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F3014
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKIN
VSS
VSS
VDD
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/CN7/RB5
AN4/CN6/RB4
AN11/RB11
NC
AN10/RB10
AN9/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
RF0
VSS
VDD
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/RB12
Note:
DS70138C-page 4
Advance Information
dsPIC30F3014/4013
Pin Diagrams (Continued)
40-Pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dsPIC30F4013
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
INT0/RA11
IC2/INT2/RD9
OC4/RD3
VSS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AVDD
AVSS
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VSS
C1RX/RF0
C1TX/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
44-Pin TQFP
dsPIC30F4013
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKIN
VSS
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
NC
NC
AN10/CSDI/RB10
AN9/CSCK/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
CTX1/RF1
CRX1/RF0
VSS
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/COFS/RB12
AN11/CSDO/RB11
Note:
Advance Information
DS70138C-page 5
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
OC3/RD2
VDD
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F4013
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKIN
VSS
VSS
VDD
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN11/CSDO/RB11
NC
AN10/CSDI/RB10
AN9/CSCK/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
CTX1/RF1
CRX1/RF0
VSS
VDD
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/COFS/RB12
DS70138C-page 6
Advance Information
dsPIC30F3014/4013
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Address Generator Units............................................................................................................................................................ 35
5.0 Flash Program Memory.............................................................................................................................................................. 41
6.0 Data EEPROM Memory ............................................................................................................................................................. 47
7.0 I/O Ports ..................................................................................................................................................................................... 51
8.0 Interrupts .................................................................................................................................................................................... 55
9.0 Timer1 Module ........................................................................................................................................................................... 63
10.0 Timer2/3 Module ........................................................................................................................................................................ 67
11.0 Timer4/5 Module ....................................................................................................................................................................... 73
12.0 Input Capture Module................................................................................................................................................................. 77
13.0 Output Compare Module ............................................................................................................................................................ 81
14.0 SPI Module................................................................................................................................................................................. 85
15.0 I2C Module ................................................................................................................................................................................. 89
16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 97
17.0 CAN Module ............................................................................................................................................................................. 105
18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 115
19.0 12-bit Analog-to-Digital Converter (A/D) Module...................................................................................................................... 125
20.0 System Integration ................................................................................................................................................................... 131
21.0 Instruction Set Summary .......................................................................................................................................................... 149
22.0 Development Support............................................................................................................................................................... 157
23.0 Electrical Characteristics .......................................................................................................................................................... 163
24.0 Packaging Information.............................................................................................................................................................. 205
Index .................................................................................................................................................................................................. 209
On-Line Support................................................................................................................................................................................. 215
Systems Information and Upgrade Hot Line ...................................................................................................................................... 215
Reader Response .............................................................................................................................................................................. 216
Product Identification System ............................................................................................................................................................ 217
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Advance Information
DS70138C-page 7
dsPIC30F3014/4013
NOTES:
DS70138C-page 8
Advance Information
dsPIC30F3014/4013
1.0
DEVICE OVERVIEW
FIGURE 1-1:
Interrupt
Controller
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Program Memory
(24 Kbytes)
INT0/RA11
PORTA
16
X RAGU
X WAGU
Y AGU
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
16
16
24
Address Latch
16
16
16
AN0/CN2/RB0
AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
16
Data EEPROM
(1 Kbyte)
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16
16
Decode
Instruction
Decode and
Control
16 16
PORTC
Control Signals
to Various Blocks
OSC1/CLKI
EMUD1/SOSCI/T2CK/U1ATX/
CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array
DSP
Engine
Power-up
Timer
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
ALU<16>
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
16
16
Watchdog
Timer
Low Voltage
Detect
PORTD
12-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C
Timers
DCI
SPI1
UART1,
UART2
EMUC2/OC1/RD0
EMUD2/OC2/RD1
RD2
RD3
IC1/INT1/RD8
IC2/INT2/RD9
Advance Information
RF0
RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/RF6
PORTF
DS70138C-page 9
dsPIC30F3014/4013
FIGURE 1-2:
Interrupt
Controller
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Program Memory
(48 Kbytes)
INT0/RA11
PORTA
16
X RAGU
X WAGU
Y AGU
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
16
16
24
Address Latch
16
16
16
AN0/CN2/RB0
AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
16
Data EEPROM
(1 Kbyte)
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16
16
Decode
Instruction
Decode &
Control
16 16
PORTC
Control Signals
to Various Blocks
DSP
Engine
Power-up
Timer
MCLR
VDD, VSS
AVDD, AVSS
DS70138C-page 10
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
ALU<16>
POR/BOR
Reset
CAN1
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
OSC1/CLKI
EMUD1/SOSCI/T2CK/U1ATX/
CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
OSC2/CLKO/RC15
16 x 16
W Reg Array
16
Watchdog
Timer
Low Voltage
Detect
IC1/INT1/RD8
IC2/INT2/RD9
16
PORTD
12-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C
Timers
DCI
SPI1
UART1,
UART2
Advance Information
C1RX/RF0
C1TX/RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/RF6
PORTF
dsPIC30F3014/4013
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral modules
functional requirements may force an override of the
data direction of the port pin.
TABLE 1-1:
Buffer
Type
AN0-AN12
Analog
AVDD
AVSS
CLKI
ST/CMOS
CLKO
CN0-CN7, CN17-CN18
ST
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
C1RX
C1TX
I
O
ST
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Pin Name
Description
Analog input channels.
AN6 and AN7 are also used for device programming data and
clock inputs, respectively.
Positive supply for analog module.
Ground reference for analog module.
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC
and EC modes. Always associated with OSC2 pin function.
ST
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
LVDIN
Analog
MCLR
I/P
ST
OCFA
OC1-OC4
I
O
ST
OSC1
ST/CMOS
OSC2
I/O
PGD
PGC
I/O
I
ST
ST
Advance Information
DS70138C-page 11
dsPIC30F3014/4013
TABLE 1-1:
Buffer
Type
RA11
I/O
ST
RB0-RB12
I/O
ST
RC13-RC15
I/O
ST
I/O
ST
RF0-RF5
I/O
ST
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
ST
SCL
SDA
I/O
I/O
ST
ST
SOSCO
SOSCI
O
I
ST/CMOS
T1CK
T2CK
I
I
ST
ST
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
ST
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
VDD
VSS
VREF+
Analog
VREF-
Analog
Pin Name
Description
PORTA is a bidirectional I/O port.
DS70138C-page 12
Advance Information
dsPIC30F3014/4013
2.0
CPU ARCHITECTURE
OVERVIEW
2.1
Core Overview
Advance Information
DS70138C-page 13
dsPIC30F3014/4013
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined natural
order. Traps have fixed priorities ranging from 8 to 15.
2.2
Programmers Model
2.2.1
2.2.2
STATUS REGISTER
2.2.3
PROGRAM COUNTER
DS70138C-page 14
Advance Information
dsPIC30F3014/4013
FIGURE 2-1:
PROGRAMMERS MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
AD39
AD15
AD31
AD0
AccA
DSP
Accumulators
AccB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
PSVPAG
0
RCOUNT
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DOEND
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
OV
Status Register
SRL
Advance Information
DS70138C-page 15
dsPIC30F3014/4013
2.3
Divide Support
TABLE 2-1:
DIVIDE INSTRUCTIONS
Instruction
DIVF
Note:
Function
Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd
DIV.sw or
DIV.s
DIV.ud
DIV.uw or
DIV.u
DS70138C-page 16
Advance Information
dsPIC30F3014/4013
2.4
DSP Engine
TABLE 2-2:
7.
Note:
Instruction
CLR
ED
Algebraic Operation
A=0
ACC WB?
Yes
A = (x y)2
No
2
No
EDAC
A = A + (x y)
MAC
A = A + (x * y)
MAC
A = A + x2
No
No change in A
Yes
A=x*y
No
A=x*y
No
A=Ax*y
Yes
MOVSAC
MPY
MPY.N
MSC
Advance Information
Yes
DS70138C-page 17
dsPIC30F3014/4013
FIGURE 2-2:
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
Barrel
Shifter
X Data Bus
16
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70138C-page 18
Advance Information
dsPIC30F3014/4013
2.4.1
MULTIPLIER
2.4.2.1
2.4.2
4.
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
Advance Information
DS70138C-page 19
dsPIC30F3014/4013
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation, or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.
The overflow and saturation status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three saturation and overflow
modes:
1.
2.
3.
DS70138C-page 20
2.4.2.2
2.
2.4.2.3
Round Logic
The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the LS Word is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LS bit
(bit 16 of the accumulator) of ACCxH is examined. If it
is 1, ACCxH is incremented. If it is 0, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4). Note
that for the MAC class of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
Advance Information
dsPIC30F3014/4013
2.4.2.4
2.4.3
BARREL SHIFTER
Advance Information
DS70138C-page 21
dsPIC30F3014/4013
NOTES:
DS70138C-page 22
Advance Information
dsPIC30F3014/4013
MEMORY ORGANIZATION
3.1
FIGURE 3-2:
Reserved
000000
000002
000004
Reserved
00007E
000080
000084
000084
0000FE
000100
0000FE
000100
Data EEPROM
(1 Kbyte)
Data EEPROM
(1 Kbyte)
7FFFFE
800000
Reserved
8005BE
8005C0
007FFE
004000
7FFBFE
7FFC00
7FFFFE
800000
003FFE
004000
Reserved
Configuration Memory
Space
User Memory
Space
User Flash
Program Memory
(8K instructions)
7FFBFE
7FFC00
User Flash
Program Memory
(16K instructions)
Reserved
(Read 0s)
Reserved
(Read 0s)
00007E
000080
User Memory
Space
000000
000002
000004
dsPIC30F3014 PROGRAM
SPACE MEMORY MAP
Vector Tables
FIGURE 3-1:
dsPIC30F4013 PROGRAM
SPACE MEMORY MAP
Vector Tables
3.0
8005BE
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
Device Configuration
Registers
8005FE
800600
F7FFFE
F80000
F8000E
F80010
Configuration Memory
Space
Reserved
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
DEVID (2)
FEFFFE
FF0000
FF0002
Reserved
DEVID (2)
FEFFFE
FF0000
FF0002
Advance Information
DS70138C-page 23
dsPIC30F3014/4013
TABLE 3-1:
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
Instruction Access
User
TBLRD/TBLWT
User
(TBLPAG<7> = 0)
TBLPAG<7:0>
Data EA<15:0>
TBLRD/TBLWT
Configuration
(TBLPAG<7> = 1)
TBLPAG<7:0>
Data EA<15:0>
User
FIGURE 3-3:
<0>
PC<22:1>
PSVPAG<7:0>
Data EA<14:0>
Program Counter
Select
Using
Program
Space
Visibility
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0
User/
Configuration
Space
Select
Note:
DS70138C-page 24
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
Program space visibility cannot be used to access bits <23:16> of a word in program memory.
Advance Information
dsPIC30F3014/4013
3.1.1
2.
3.
4.
Figure 3-3 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-4:
PC Address
0x000000
0x000002
0x000004
0x000006
Program Memory
Phantom Byte
(read as 0)
23
16
00000000
00000000
00000000
00000000
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
TBLRDL.B (Wn<0> = 1)
Advance Information
DS70138C-page 25
dsPIC30F3014/4013
FIGURE 3-5:
23
16
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 0)
Program Memory
Phantom Byte
(read as 0)
3.1.2
TBLRDH.B (Wn<0> = 1)
DS70138C-page 26
Advance Information
dsPIC30F3014/4013
FIGURE 3-6:
Data Space
Program Space
0x0000
EA<15> = 0
0x000100
PSVPAG(1)
0x00
8
15
Data 16
Space
15
EA
EA<15> = 1
0x8000
15
Address
Concatenation 23
23
15
0
0x000200
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x8200, W0
Data Read
Note:
PSVPAG is an 8-bit register, containing bits <22:15> of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
The memory map shown here is for a dsPIC30F4013 device.
Advance Information
DS70138C-page 27
dsPIC30F3014/4013
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
DS70138C-page 28
Advance Information
dsPIC30F3014/4013
FIGURE 3-7:
2 Kbyte
SFR Space
LS Byte
Address
16 bits
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
2 Kbyte
SRAM Space
0x0BFF
0x0C01
Y Data RAM (Y)
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x1FFE
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0x0BFE
0x0C00
8 Kbyte
Near
Data
Space
0xFFFE
Advance Information
DS70138C-page 29
dsPIC30F3014/4013
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-8:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
DS70138C-page 30
Advance Information
dsPIC30F3014/4013
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restrictions. Bit-reversed addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-7 and is not user programmable. Should an EA point to data outside its own
assigned address space, or to a location outside physical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) will return
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
0x0000
0x0000
3.2.4
DATA ALIGNMENT
FIGURE 3-9:
15
DATA ALIGNMENT
MS Byte
87
LS Byte
0001
Byte1
Byte 0
0000
0003
Byte3
Byte 2
0002
0005
Byte5
Byte 4
0004
Advance Information
DS70138C-page 31
dsPIC30F3014/4013
All byte loads into any W register are loaded into the
LS Byte. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
There is a Stack Pointer Limit register (SPLIM) associated with the stack pointer. SPLIM is uninitialized at
Reset. As is the case for the stack pointer, SPLIM<0>
is forced to 0 because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a Stack Error Trap will not
occur. The Stack Error Trap will occur on a subsequent
push operation. Thus, for example, if it is desirable to
cause a Stack Error Trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a stack pointer underflow (stack error) trap is
generated when the stack pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-10:
3.2.6
SOFTWARE STACK
0x0000
15
PC<15:0>
000000000 PC<22:16>
DS70138C-page 32
Advance Information
<Free Word>
Advance Information
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
W10
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
PCH
0040
0042
DOENDH
SR
OA
OB
Bit 14
u = uninitialized bit
003E
DOENDL
Legend:
003C
DOSTARTH
003A
0012
W9
DOSTARTL
0010
W8
0038
000E
W7
DCOUNT
000C
W6
0036
000A
W5
RCOUNT
0008
W4
0032
0006
W3
0034
0004
W2
PSVPAG
0002
TBLPAG
0000
W0
Bit 15
Bit 12
Bit 11
SA
SB
OAB
Sign-Extension (ACCB<39>)
SAB
Bit 10
Sign-Extension (ACCA<39>)
Bit 13
Address
(Home)
W1
SFR Name
TABLE 3-3:
DA
DCOUNT
RCOUNT
PCL
ACCBH
ACCBL
ACCAH
ACCAL
SPLIM
W15
W14
W13
W12
W11
W10
W9
W8
W7
W6
W5
W4
W3
W2
W1
DC
DOENDL
IPL2
Bit 7
W0/WREG
Bit 8
DOSTARTL
Bit 9
IPL1
Bit 6
IPL0
Bit 5
Bit 3
RA
DOENDH
DOSTARTH
PSVPAG
TBLPAG
PCH
ACCBU
ACCAU
Bit 4
OV
Bit 2
Bit 1
Bit 0
Reset State
dsPIC30F3014/4013
DS70138C-page 33
DS70138C-page 34
004E
0050
0052
YMODSRT
YMODEND
XBREV
DISICNT
BREN
YMODEN
Bit 14
US
Bit 12
Bit 13
EDT
Bit 11
DL1
Bit 9
BWM<3:0>
DL2
Bit 10
YE<15:1>
YS<15:1>
XE<15:1>
XS<15:1>
DL0
Bit 8
Bit 4
SATDW ACCSAT
Bit 5
YWM<3:0>
SATB
Bit 6
DISICNT<13:0>
XB<14:0>
SATA
Bit 7
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
u = uninitialized bit
004C
XMODEND
Legend:
0048
004A
XMODSRT
XMODEN
0044
0046
CORCON
Bit 15
MODCON
SFR Name
Address
(Home)
TABLE 3-3:
IPL3
Bit 3
RND
Bit 1
XWM<3:0>
PSV
Bit 2
IF
Bit 0
Reset State
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
4.0
4.1.2
MCU INSTRUCTIONS
4.1
4.1.1
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
Note:
TABLE 4-1:
Not all instructions support all the addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Addressing Mode
Description
Register Direct
Register Indirect
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
Advance Information
DS70138C-page 35
dsPIC30F3014/4013
4.1.3
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.1.4
Not all instructions support all the addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
4.2
Modulo Addressing
Modulo addressing is a method of providing an automated means to support circular data buffers using
hardware. The objective is to remove the need for software to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo addressing can operate in either data or program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for modulo addressing since these two registers are used as
the stack frame pointer and stack pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks will be performed on both the lower and upper
address boundaries).
DS70138C-page 36
Advance Information
dsPIC30F3014/4013
4.2.1
4.2.2
Y space modulo addressing EA calculations assume word sized data (LS bit of
every EA is always clear).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X
RAGU and X WAGU modulo addressing is disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which modulo addressing is to be applied, is stored in
MODCON<3:0> (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM), to
which modulo addressing is to be applied, is stored in
MODCON<7:4>. Modulo addressing is enabled for Y
data space when YWM is set to any value other than
15 and the YMODEN bit is set at MODCON<14>.
FIGURE 4-1:
Byte
Address
0x0800
MOV
MOV
MOV
MOV
MOV
MOV
#0x800,W0
W0,XMODSRT
#0x863,W0
W0,MODEND
#0x8001,W0
W0,MODCON
MOV
MOV
#0x0000,W0
#0x800,W1
DO
AGAIN,#0x31
MOV
W0,[W1++]
AGAIN: INC W0,W0
0x0863
Advance Information
DS70138C-page 37
dsPIC30F3014/4013
4.2.3
MODULO ADDRESSING
APPLICABILITY
4.3
Bit-Reversed Addressing
Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
2.
3.
FIGURE 4-2:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b7 b6 b5 b1
b2 b3 b4
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
DS70138C-page 38
Advance Information
dsPIC30F3014/4013
TABLE 4-2:
A3
A2
A1
A0
Bit-Reversed Address
Decimal
A3
A2
A1
A0
Decimal
12
10
14
10
11
13
12
13
11
14
15
15
TABLE 4-3:
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
0x0004
0x0002
0x0001
Advance Information
DS70138C-page 39
dsPIC30F3014/4013
NOTES:
DS70138C-page 40
Advance Information
dsPIC30F3014/4013
5.0
5.2
The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are
two methods by which the user can program this
memory:
1.
2.
5.1
5.3
FIGURE 5-1:
Run-Time Self-Programming
(RTSP)
Program Counter
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Advance Information
Byte
Select
DS70138C-page 41
dsPIC30F3014/4013
5.4
RTSP Operation
5.5
Control Registers
NVMCON
NVMADR
NVMADRU
NVMKEY
5.5.1
5.5.2
NVMADR REGISTER
5.5.3
NVMADRU REGISTER
5.5.4
NVMKEY REGISTER
DS70138C-page 42
NVMCON REGISTER
Advance Information
dsPIC30F3014/4013
5.6
Programming Operations
4.
5.6.1
5.
2.
3.
EXAMPLE 5-1:
6.
5.6.2
write
Advance Information
DS70138C-page 43
dsPIC30F3014/4013
5.6.3
5.6.4
EXAMPLE 5-2:
; 31st_program_word
MOV
#LOW_WORD_31,W2
;
MOV
#HIGH_BYTE_31,W3
;
; Write PM low word into program latch
TBLWTL W2, [W0]
; Write PM high byte into program latch
TBLWTH W3, [W0++]
Note: In Example 5-2, the contents of the upper byte of W3 has no effect.
EXAMPLE 5-3:
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0,NVMKEY
#0xAA,W1
W1,NVMKEY
NVMCON,#WR
DS70138C-page 44
;
;
;
;
;
;
;
;
;
Advance Information
0764
0766
NVMADRU
NVMKEY
WREN
Bit 14
WR
Bit 15
Bit 9
Bit 7
NVMADR<15:0>
TWRI
Bit 8
Bit 6
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
WRERR
Bit 13
u = uninitialized bit
0762
Legend:
0760
NVMCON
Addr.
NVMADR
File Name
TABLE 5-1:
Bit 3
Bit 2
KEY<7:0>
NVMADR<23:16>
PROGOP<6:0>
Bit 4
Bit 1
Bit 0
All RESETS
dsPIC30F3014/4013
Advance Information
DS70138C-page 45
dsPIC30F3014/4013
NOTES:
DS70138C-page 46
Advance Information
dsPIC30F3014/4013
6.0
NVMCON
NVMADR
NVMADRU
NVMKEY
Control bit WR initiates write operations similar to program Flash writes. This bit cannot be cleared, only set,
in software. They are cleared in hardware at the completion of the write operation. The inability to clear the
WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
Note:
6.1
Interrupt flag bit NVMIF in the IFS0 register is set when write is complete. It must be
cleared in software.
A TBLRD instruction reads a word at the current program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4 as shown in Example 6-1.
EXAMPLE 6-1:
MOV
MOV
MOV
TBLRDL
Advance Information
DS70138C-page 47
dsPIC30F3014/4013
6.2
6.2.1
6.2.2
EXAMPLE 6-2:
EXAMPLE 6-3:
DS70138C-page 48
Advance Information
dsPIC30F3014/4013
6.3
2.
3.
EXAMPLE 6-4:
6.3.1
6.3.2
; Init pointer
; Get data
; Write data
MOV
#0x55,W0
; Write the 0x55 key
MOV
W0,NVMKEY
MOV
#0xAA,W1
; Write the 0xAA key
MOV
W1,NVMKEY
BSET
NVMCON,#WR
; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Advance Information
DS70138C-page 49
dsPIC30F3014/4013
EXAMPLE 6-5:
6.4
MOV
MOV
MOV
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
TBLWTL
MOV
MOV
DISI
#5
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1,TBLPAG
#data1,W2
W2,[ W0]++
#data2,W2
W2,[ W0]++
#data3,W2
W2,[ W0]++
#data4,W2
W2,[ W0]++
#data5,W2
W2,[ W0]++
#data6,W2
W2,[ W0]++
#data7,W2
W2,[ W0]++
#data8,W2
W2,[ W0]++
#data9,W2
W2,[ W0]++
#data10,W2
W2,[ W0]++
#data11,W2
W2,[ W0]++
#data12,W2
W2,[ W0]++
#data13,W2
W2,[ W0]++
#data14,W2
W2,[ W0]++
#data15,W2
W2,[ W0]++
#data16,W2
W2,[ W0]++
#0x400A,W0
W0,NVMCON
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0,NVMKEY
#0xAA,W1
W1,NVMKEY
NVMCON,#WR
; Init pointer
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Write Verify
6.5
DS70138C-page 50
Advance Information
dsPIC30F3014/4013
7.0
I/O PORTS
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
7.1
A parallel I/O (PIO) port that shares a pin with a peripheral is, in general, subservient to the peripheral. The
peripherals output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 7-2 shows how ports are shared
with other peripherals and the associated I/O cell (pad)
to which they are connected. Table 7-1 shows the
formats of the registers for the shared ports, PORTB
through PORTG.
FIGURE 7-1:
Note:
Read TRIS
I/O Cell
TRIS Latch
Data Bus
WR TRIS
CK
Data Latch
D
WR LAT +
WR Port
I/O Pad
CK
Read LAT
Read Port
Advance Information
DS70138C-page 51
dsPIC30F3014/4013
FIGURE 7-2:
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
1 Output Enable
0
PIO Module
Output Data
0
Read TRIS
I/O Pad
Data Bus
WR TRIS
CK
TRIS Latch
D
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
7.2
DS70138C-page 52
7.2.1
EXAMPLE 7-1:
MOV
0xFF00, W0
MOV
NOP
W0, TRISB
btss
PORTB, #11
Advance Information
PORT WRITE/READ
EXAMPLE
;
;
;
;
Configure PORTB<15:8>
as inputs
and PORTB<7:0> as outputs
additional instruction
cylcle
; bit test RB11 and skip if
set
LATD
u = uninitialized bit
LATC14
RC14
LATC15
RC15
LATC13
RC13
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
RB11
LATB11
RB12
LATB12
LATB10
RB10
RB8
LATB8
LATD9
RD9
LATD8
RD8
TRISD9 TRISD8
LATB9
RB9
LATB7
RB7
RB5
LATB5
RB4
LATB4
RB3
RB2
LATB2
RB1
LATB1
RB0
LATB0
LATD3
RD3
LATD2
RD2
LATD1
RD1
LATD0
RD0
LATB3
LATF6
RF6
LATF5
RF5
LATF4
RF4
LATF3
RF3
LATF2
RF2
LATF1
RF1
LATF0
RF0
TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 0000 0000 0111 1111
LATB6
RB6
TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0001 1111 1111 1111
Bit 9
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Legend:
02E0
02D4
02D6
PORTD
02E2
02D2
TRISD
LATF
02D0
LATC
PORTF
02CE
PORTC
02DE
TRISC
TRISF
02CB
LATB
02C8
PORTB
RA11
LATA11
02C6
TRISB
02C4
LATA
Bit 10
Bit 11
02C2
PORTA
TRISA11
02C0
TRISA
Bit 12
Bit 14
Bit 15
Bit 13
TABLE 7-1:
dsPIC30F3014/4013
Advance Information
DS70138C-page 53
dsPIC30F3014/4013
7.3
TABLE 7-2:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset State
CNEN1
00C0
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CNEN2
00C2
CNPU1
00C4
CN15PUE
CN14PUE
CN13PUE
CN12PUE
CN11PUE
CN10PUE
CN9PUE
CN8PUE
CNPU2
00C6
Legend:
u = uninitialized bit
TABLE 7-3:
SFR
Name
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CNEN1
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
CNEN2
00C2
CN18IE
CN17IE
CN16IE
CNPU1
00C4
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
CNPU2
00C6
CN18PUE CN17PUE
CN16PUE
Legend:
u = uninitialized bit
TABLE 7-4:
SFR
Name
Bit 2
Bit 1
Bit 0
Reset State
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
00C0
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CNEN2
00C2
CN9PUE
CN8PUE
CNPU1
00C4
CNPU2
00C6
Legend:
u = uninitialized bit
TABLE 7-5:
Reset State
SFR
Name
Addr.
CNEN1
00C0
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
CNEN2
00C2
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
CNPU1
00C4
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
CNPU2
00C6
CN16PUE
Legend:
u = uninitialized bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
DS70138C-page 54
Advance Information
dsPIC30F3014/4013
8.0
INTERRUPTS
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
Note:
Advance Information
DS70138C-page 55
dsPIC30F3014/4013
8.1
Interrupt Priority
TABLE 8-1:
DS70138C-page 56
INT
Number
dsPIC30F3014 INTERRUPT
VECTOR TABLE
Vector
Number
Interrupt Source
Advance Information
dsPIC30F3014/4013
TABLE 8-2:
INT
Number
dsPIC30F4013 INTERRUPT
VECTOR TABLE
Vector
Number
Interrupt Source
8.2
Reset Sequence
8.2.1
RESET SOURCES
Advance Information
DS70138C-page 57
dsPIC30F3014/4013
8.3
Traps
If the user does not intend to take corrective action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Note:
5.
6.
8.3.1
2.
3.
4.
DS70138C-page 58
2.
1.
TRAP SOURCES
The following traps are provided with increasing priority. However, since all traps can be nested, priority has
little effect.
8.3.2
Advance Information
dsPIC30F3014/4013
Decreasing
Priority
FIGURE 8-1:
IVT
AIVT
8.4
TRAP VECTORS
Reset - GOTO Instruction
Reset - GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
0x000000
0x000002
0x000004
FIGURE 8-2:
0x0000 15
PC<15:0>
SRL IPL3 PC<22:16>
<Free Word>
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE
Interrupt Sequence
8.5
Advance Information
DS70138C-page 59
dsPIC30F3014/4013
8.6
8.7
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.
DS70138C-page 60
8.8
Advance Information
00A4
00A6
00A8
u = uninitialized bit
IPC9
IPC10
Legend:
Advance Information
C1IP<2:0>
INT2IP<2:0>
CNIP<2:0>
NVMIE
NVMIF
Bit 12
C1IE
ADIE
C1IF
ADIF
Bit 11
U2TXIF
U1RXIF
OVBTE
Bit 9
LVDIE
SPI1IE
U2RXIF
SPI1IF
COVTE
Bit 8
LVDIP<2:0>
MI2CIP<2:0>
U1TXIP<2:0>
T2IP<2:0>
OC1IP<2:0>
U2TXIE U2RXIE
U1TXIE U1RXIE
LVDIF
U1TXIF
OVATE
Bit 10
INT2IE
T3IE
INT2IF
T3IF
Bit 7
T2IE
T2IF
Bit 6
Bit 4
DCIIP<2:0>
U2TXIP<2:0>
SI2CIP<2:0>
U1RXIP<2:0>
OC2IP<2:0>
IC2IE
IC2IF
MATHERR
IC1IP<2:0>
OC2IE
OC2IF
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
IPC8
009C
IPC4
00A2
009A
IPC3
ADIP<2:0>
IPC7
0098
IPC2
T1IP<2:0>
T31P<2:0>
SI2CIE
009E
0096
IPC1
00A0
0094
IPC0
IPC5
0090
IEC2
IPC6
008E
IEC1
MI2CIE
CNIE
0088
008C
IFS2
IEC0
0086
IFS1
SI2CIF
MI2CIF
0084
IFS0
Bit 13
Bit 14
CNIF
0080 NSTDIS
0082 ALTIVT
Bit 15
INTCON1
ADR
INTCON2
SFR
Name
TABLE 8-3:
T1IE
T1IF
ADDRERR
Bit 3
Bit 1
OC1IE
OC1IF
INT2EP
U2RXIP<2:0>
INT1IP<2:0>
NVMIP<2:0>
SPI1IP<2:0>
IC2IP<2:0>
INT0IP<2:0>
IC1IE
IC1IF
INT1EP
STKERR OSCFAIL
Bit 2
Reset State
INT1IE
INT0IE
INT1IF
INT0IF
Bit 0
dsPIC30F3014/4013
DS70138C-page 61
DS70138C-page 62
Advance Information
C1IE
ADIE
C1IF
ADIF
Bit 11
DCIIF
U2TXIF
U1RXIF
OVBTE
Bit 9
LVDIE
SPI1IE
U2RXIF
SPI1IF
COVTE
Bit 8
LVDIP<2:0>
SPI2IP<2:0>
T5IP<2:0>
IC8IP<2:0>
MI2CIP<2:0>
U1TXIP<2:0>
T2IP<2:0>
OC1IP<2:0>
DCIIE
U2TXIE U2RXIE
U1TXIE U1RXIE
LVDIF
U1TXIF
OVATE
Bit 10
INT2IE
T3IE
INT2IF
T3IF
Bit 7
T5IE
T2IE
T5IF
T2IF
Bit 6
Bit 4
DCIIP<2:0>
U2TXIP<2:0>
T4IP<2:0>
IC7IP<2:0>
SI2CIP<2:0>
U1RXIP<2:0>
OC2IP<2:0>
OC4IE
IC2IE
OC4IF
IC2IF
MATHERR
IC1IP<2:0>
T4IE
OC2IE
T4IF
OC2IF
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
u = uninitialized bit
Legend:
00A8
IPC10
00A6
IPC9
00A2
C1IP<2:0>
00A4
INT2IP<2:0>
IPC7
00A0
IPC6
NVMIE
OC3IP<2:0>
CNIP<2:0>
ADIP<2:0>
T31P<2:0>
T1IP<2:0>
SI2CIE
Bit 12
NVMIF
MI2CIE
CNIE
IPC8
009E
0098
IPC2
IPC5
0096
IPC1
009A
0094
IPC0
009C
0090
IEC2
IPC4
008E
IEC1
IPC3
008C
IEC0
0088
IFS2
0086
IFS1
SI2CIF
MI2CIF
0084
IFS0
Bit 13
Bit 14
CNIF
0082 ALTIVT
INTCON2
Bit 15
0080 NSTDIS
ADR
INTCON1
SFR
Name
TABLE 8-4:
OC3IE
T1IE
OC3IF
T1IF
ADDRERR
Bit 3
Bit 1
IC8IE
OC1IE
IC8IF
OC1IF
INT2EP
U2RXIP<2:0>
OC4IP<2:0>
INT1IP<2:0>
NVMIP<2:0>
SPI1IP<2:0>
IC2IP<2:0>
INT0IP<2:0>
IC7IE
IC1IE
IC7IF
IC1IF
INT1EP
STKERR OSCFAIL
Bit 2
Reset State
INT1IE
INT0IE
INT1IF
INT0IF
Bit 0
dsPIC30F3014/4013
dsPIC30F3014/4013
9.0
TIMER1 MODULE
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
FIGURE 9-1:
Comparator x 16
TSYNC
1
Sync
TMR1
Reset
0
T1IF
Event Flag
0
1
CK
TCS
TGATE
TGATE
TGATE
TON
SOSCO/
T1CK
1x
LPOSCEN
SOSCI
TCKPS<1:0>
2
Gate
Sync
01
TCY
00
Advance Information
Prescaler
1, 8, 64, 256
DS70138C-page 63
dsPIC30F3014/4013
9.1
9.4
The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
Timer Prescaler
9.3
Timer Interrupt
9.5
Real-Time Clock
FIGURE 9-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
DS70138C-page 64
C1
SOSCI
32.768 kHz
XTAL
dsPIC30FXXXX
SOSCO
C2
C1 = C2 = 18 pF; R = 100K
Advance Information
dsPIC30F3014/4013
9.5.1
9.5.2
RTC INTERRUPTS
When the CPU enters Sleep mode, the RTC will continue to operate provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to 0 in
order for RTC to continue operation in Idle mode.
Advance Information
DS70138C-page 65
DS70138C-page 66
u = uninitialized bit
Legend:
Bit 14
TSIDL
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 7
Bit 6
TGATE
Period Register 1
Timer1 Register
Bit 8
Bit 4
TCKPS1 TCKPS0
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
0102
0104
TON
Bit 15
T1CON
0100
PR1
Addr.
SFR Name
TMR1
TABLE 9-1:
Bit 3
TSYNC
Bit 2
TCS
Bit 1
Bit 0
Reset State
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
10.0
TIMER2/3 MODULE
Advance Information
DS70138C-page 67
dsPIC30F3014/4013
FIGURE 10-1:
TMR3HLD
16
16
Write TMR2
Read TMR2
16
Reset
TMR3
TMR2
MSB
LSB
Sync
Comparator x 32
PR3
PR2
T3IF
Event Flag
CK
TGATE (T2CON<6>)
TCS
TGATE
TGATE
(T2CON<6>)
TON
T2CK
Note:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Timer configuration bit T32 (T2CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T2CON register.
DS70138C-page 68
Advance Information
dsPIC30F3014/4013
FIGURE 10-2:
Comparator x 16
TMR2
Sync
Reset
T2IF
Event Flag
0
1
CK
TGATE
TCS
TGATE
TGATE
TON
T2CK
TCKPS<1:0>
2
1x
FIGURE 10-3:
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Equal
Comparator x 16
TMR3
Reset
0
1
CK
TGATE
T3CK
TGATE
TCS
TGATE
T3IF
Event Flag
Sync
TON
1x
01
TCY
Note:
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
00
T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates
the schematic of Timer3 as implemented on the 30F6014 device.
Advance Information
DS70138C-page 69
dsPIC30F3014/4013
10.1
10.4
The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.
10.2
10.3
10.5
Timer Interrupt
Timer Prescaler
DS70138C-page 70
Advance Information
010A
010C
010E
0110
0112
u = uninitialized bit
TMR3
PR2
PR3
T2CON
T3CON
Legend:
TSIDL
TSIDL
Bit 12
Bit 11
Bit 9
Bit 7
Timer2 Register
Bit 8
Bit 6
Bit 5
TGATE
TGATE
Period Register 3
Period Register 2
Timer3 Register
Bit 4
TCKPS1 TCKPS0
TCKPS1 TCKPS0
Bit 10
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
TON
0108
TMR3HLD
TON
0106
TMR2
Bit 13
Bit 15
Bit 14
TABLE 10-1:
T32
Bit 3
Bit 2
TCS
TCS
Bit 1
Bit 0
Reset State
dsPIC30F3014/4013
Advance Information
DS70138C-page 71
dsPIC30F3014/4013
NOTES:
DS70138C-page 72
Advance Information
dsPIC30F3014/4013
11.0
TIMER4/5 MODULE
This section describes the second 32-bit General Purpose (GP) Timer module (Timer4/5) and associated
Operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 module.
Figure 11-2 and Figure 11-3 show Timer4/5 configured
as two independent 16-bit timers, Timer4 and Timer5,
respectively.
The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some differences
which are listed:
The Timer4/5 module does not support the ADC
event trigger feature
Timer4/5 can not be utilized by other peripheral
modules, such as input capture and output compare
FIGURE 11-1:
TMR5HLD
16
16
Write TMR4
Read TMR4
16
Reset
Equal
TMR5
TMR4
MSB
LSB
Sync
Comparator x 32
PR5
PR4
0
T5IF
Event Flag
TGATE (T4CON<6>)
CK
TCS
TGATE
TGATE
(T4CON<6>)
TON
T4CK
Note:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Timer configuration bit T32 (T4CON<3>) must be set to 1 for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
Advance Information
DS70138C-page 73
dsPIC30F3014/4013
FIGURE 11-2:
Reset
TMR4
Sync
0
1
CK
TGATE
TCS
TGATE
T4IF
Event Flag
Comparator x 16
TGATE
TON
T4CK
FIGURE 11-3:
TCKPS<1:0>
2
1x
Gate
Sync
01
TCY
00
Prescaler
1, 8, 64, 256
Equal
Comparator x 16
TMR5
Reset
0
1
CK
TGATE
TCS
TGATE
T5IF
Event Flag
TGATE
T5CK
TON
Sync
1x
01
TCY
Note:
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
00
In the dsPIC30F3014 device, there is no T5CK pin. Therefore, in this device the following modes should
not be used for Timer5:
1: TCS = 1 (16-bit counter)
2: TCS = 0, TGATE = 1 (gated time accumulation)
DS70138C-page 74
Advance Information
0120
T5CON
TON
TON
Bit 15
TSIDL
Bit 13
Bit 12
Bit 11
Bit 9
Bit 7
Bit 6
Timer 4 Register
Bit 8
Bit 5
TGATE
TGATE
Period Register 5
Period Register 4
Timer 5 Register
TCKPS1
TCKPS1
Bit 10
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Bit 14
u = uninitialized
011E
T4CON
Legend:
011A
011C
0118
TMR5
PR4
0116
PR5
0114
TMR4
Addr.
TMR5HLD
SFR Name
TABLE 11-1:
TCKPS0
TCKPS0
Bit 4
T45
Bit 3
Bit 2
TCS
TCS
Bit 1
Bit 0
Reset State
dsPIC30F3014/4013
Advance Information
DS70138C-page 75
dsPIC30F3014/4013
NOTES:
DS70138C-page 76
Advance Information
dsPIC30F3014/4013
12.0
12.1
Frequency/Period/Pulse Measurements
Additional Sources of External Interrupts
The key operational features of the input capture
module are:
12.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings specified by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
FIGURE 12-1:
T3_CNT
T2_CNT
16
ICx pin
Prescaler
1, 4, 16
3
Clock
Synchronizer
Edge
Detection
Logic
16
ICTMR
FIFO
R/W
Logic
ICM<2:0>
Mode Select
ICxBUF
ICBNE, ICOV
ICI<1:0>
ICxCON
Data Bus
Note:
Interrupt
Logic
Set Flag
ICxIF
Where x is shown, reference is made to the registers or bits associated to the respective input capture
channels 1 through N.
Advance Information
DS70138C-page 77
dsPIC30F3014/4013
12.1.2
12.1.3
The input capture module consists of up to 8 input capture channels. Each channel can select between one of
two timers for the time base, Timer2 or Timer3.
Selection of the timer resource is accomplished
through SFR bit, ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
12.1.4
12.2
12.2.1
CPU Sleep mode allows input capture module operation with reduced functionality. In the CPU Sleep mode,
the ICI<1:0> bits are not applicable and the input capture module can only function as an external interrupt
source.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111) in order for the
input capture module to be used while the device is in
Sleep mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
12.2.2
12.3
DS70138C-page 78
Advance Information
IC2BUF
IC2CON
015C
015E
IC8BUF
IC8CON
Bit 14
ICSIDL
ICSIDL
Bit 13
Bit 12
Bit 11
Bit 10
Bit 8
Bit 15
ICSIDL
ICSIDL
ICSIDL
ICSIDL
Bit 13
Bit 12
Bit 11
Bit 10
Bit 8
Bit 7
ICTMR
ICTMR
ICTMR
ICTMR
ICTMR
Bit 9
ICTMR
Bit 5
Bit 5
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICI<1:0>
Bit 6
ICI<1:0>
ICI<1:0>
Bit 6
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Bit 14
Bit 7
Bit 9
u = uninitialized bit
015A
IC2CON
IC7CON
0146
IC2BUF
0158
0144
IC1CON
IC7BUF
0140
0142
IC1BUF
Addr.
SFR Name
TABLE 12-2:
Legend:
Bit 15
u = uninitialized bit
0144
0146
IC1CON
Legend:
0140
0142
IC1BUF
Addr.
SFR Name
TABLE 12-1:
ICOV
ICOV
ICOV
ICOV
Bit 4
ICOV
ICOV
Bit 4
ICBNE
ICBNE
ICBNE
ICBNE
Bit 3
ICBNE
ICBNE
Bit 3
Bit 2
Bit 2
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
Bit 1
ICM<2:0>
ICM<2:0>
Bit 1
Bit 0
Bit 0
Reset State
Reset State
dsPIC30F3014/4013
Advance Information
DS70138C-page 79
dsPIC30F3014/4013
NOTES:
DS70138C-page 80
Advance Information
dsPIC30F3014/4013
13.0
FIGURE 13-1:
13.1
OCxRS
Output
Logic
OCxR
OCTSEL
Note:
OCx
OCFA
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
From GP
Timer Module
TMR2<15:0
Output
Enable
OCM<2:0>
Mode Select
Comparator
S Q
R
TMR3<15:0> T2P2_MATCH
T3P3_MATCH
Where x is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
Advance Information
DS70138C-page 81
dsPIC30F3014/4013
13.2
13.3.2
13.3
13.4
13.3.1
13.4.1
DS70138C-page 82
Advance Information
dsPIC30F3014/4013
13.4.2
PWM PERIOD
TMRx is cleared.
The OCx pin is set.
- Exception 1: If PWM duty cycle is 0x0000,
the OCx pin will remain low.
- Exception 2: If duty cycle is greater than PRx,
the pin will remain high.
The PWM duty cycle is latched from OCxRS into
OCxR.
The corresponding timer interrupt flag is set.
EQUATION 13-1:
PWM period = [(PRx) + 1] 4 TOSC
(TMRx prescale value)
PWM frequency is defined as 1 / [PWM period].
FIGURE 13-2:
Duty Cycle
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
TMR3 = PR3
T3IF = 1
(Interrupt Flag)
OCxR = OCxRS
13.5
13.6
13.7
The output compare channels have the ability to generate an interrupt on a compare match, for whichever
Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt will be generated if enabled.
The OCxIF bit is located in the corresponding IFS
Status register and must be cleared in software. The
interrupt is enabled via the respective compare interrupt enable (OCxIE) bit located in the corresponding
IEC Control register.
For the PWM mode, when an event occurs, the respective timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated if enabled. The IF bit is
located in the IFS0 Status register and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE) located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
Advance Information
DS70138C-page 83
0186
0188
018A
u = uninitialized bit
OC2RS
OC2R
OC2CON
Legend:
DS70138C-page 84
0188
018A
018C
018E
0190
0192
0194
0196
u = uninitialized bit
OC2R
OC2CON
OC3RS
OC3R
OC3CON
OC4RS
OC4R
OC4CON
Legend:
Advance Information
OCSIDL
OCSIDL
OCSIDL
OCSIDL
Bit 11
Bit 10
Bit 8
Bit 7
Bit 6
Bit 5
Bit 9
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
0186
OC2RS
0184
OC1CON
Bit 12
0182
OC1R
Bit 13
Bit 15
Bit 14
Bit 6
0180
Addr.
SFR Name
OC1RS
OCSIDL
OCSIDL
TABLE 13-2:
Bit 7
0184
Bit 8
Bit 9
0182
Bit 10
OC1CON
Bit 11
OC1R
Bit 12
0180
Bit 13
Bit 15
Addr.
SFR Name
OC1RS
Bit 14
TABLE 13-1:
OCFLT
OCFLT
OCFLT
OCFLT
Bit 4
OCFLT
OCFLT
Bit 4
OCTSEL
OCTSEL
OCTSE
OCTSEL
Bit 3
OCTSE
OCTSEL
Bit 3
Bit 2
Bit 2
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Bit 1
OCM<2:0>
OCM<2:0>
Bit 1
Bit 0
Bit 0
Reset State
Reset State
dsPIC30F3014/4013
dsPIC30F3014/4013
14.0
SPI MODULE
The Serial Peripheral Interface (SPI) module is a synchronous serial interface. It is useful for communicating
with other peripheral devices, such as EEPROMs, shift
registers, display drivers and A/D converters, or other
microcontrollers. It is compatible with Motorola's SPI
and SIOP interfaces. The dsPIC30F3014 and
dsPIC30F4013 devices feature one SPI module, SPI1.
14.1
14.1.1
The receive operation is double-buffered. When a complete byte is received, it is transferred from SPIxSR to
SPIxBUF.
A control bit, DISSDO, is provided to the SPIxCON register to allow the SDOx output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.
If the receive buffer is full when new data is being transferred from SPIxSR to SPIxBUF, the module will set the
SPIROV bit indicating an overflow condition. The transfer of the data from SPIxSR to SPIxBUF will not be
completed and the new data will be lost. The module
will not respond to SCL transitions while SPIROV is 1,
effectively disabling the module until SPIxBUF is read
by user software.
Transmit writes are also double-buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the contents of the shift register (SPIxSR)
are moved to the receive buffer. If any transmit data has
been written to the buffer register, the contents of the
transmit buffer are moved to SPIxSR. The received
data is thus placed in SPIxBUF and the transmit data in
SPIxSR is ready for the next transfer.
Note:
14.1.2
14.2
SDOx DISABLE
Advance Information
DS70138C-page 85
dsPIC30F3014/4013
FIGURE 14-1:
Write
SPIxBUF
SPIxBUF
Receive
Transmit
SPIxSR
SDIx
bit 0
SDOx
Shift
Clock
Clock
Control
SS and
FSYNC
Control
SSx
Edge
Select
Secondary
Prescaler
1:1-1:8
SCKx
Primary
Prescaler
1:1, 1:4,
1:16, 1:64
FCY
FIGURE 14-2:
SPI Master
SPI Slave
SDOx
SDIy
SDIx
Shift Register
(SPIxSR)
MSb
SDOy
LSb
Shift Register
(SPIySR)
MSb
SCKx
Serial Clock
LSb
SCKy
PROCESSOR 1
PROCESSOR 2
Note: x = 1 or 2, y = 1 or 2.
DS70138C-page 86
Advance Information
dsPIC30F3014/4013
14.3
14.4
14.5
Advance Information
DS70138C-page 87
0224
u = uninitialized bit
SPI1BUF
Legend:
DS70138C-page 88
SPIFSD
SPISIDL
Bit 13
Bit 12
Bit 10
DISSDO MODE16
Bit 11
CKE
Bit 8
SSEN
Bit 7
CKP
SPIROV
Bit 6
SMP
Bit 9
MSTEN
Bit 5
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
FRMEN
0222
SPIEN
0220
SPI1STAT
Bit 14
SPI1CON
Bit 15
Addr.
SFR
Name
TABLE 14-1:
SPRE2
Bit 4
SPRE1
Bit 3
SPRE0
Bit 2
PPRE1
SPITBF
Bit 1
Reset State
PPRE0
Bit 0
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
15.0
I2C MODULE
15.1.1
TM
15.1
15.1.2
I2C has a 2-pin interface: the SCL pin is clock and the
SDA pin is data.
15.1.3
I2C REGISTERS
FIGURE 15-1:
PROGRAMMERS MODEL
I2CRCV (8 bits)
Bit 7
Bit 0
Bit 7
Bit 0
I2CTRN (8 bits)
I2CBRG (9 bits)
Bit 8
Bit 0
I2CCON (16 bits)
Bit 15
Bit 0
Bit 15
Bit 0
Advance Information
Bit 0
DS70138C-page 89
dsPIC30F3014/4013
FIGURE 15-2:
I2CRCV
Read
SCL
Shift
Clock
I2CRSR
LSB
SDA
Addr_Match
Match Detect
Write
I2CADD
Read
Start and
Stop bit Detect
I2CSTAT
Write
Control Logic
Start, RESTART,
Stop bit Generate
Write
I2CCON
Collision
Detect
Acknowledge
Generation
Clock
Stretching
Read
Read
Write
I2CTRN
LSB
Shift
Clock
Read
Reload
Control
BRG Down
Counter
DS70138C-page 90
Write
I2CBRG
FCY
Advance Information
Read
dsPIC30F3014/4013
15.2
15.3.2
TABLE 15-1:
0x01-0x03
Reserved
0x04-0x77
0x78-0x7b
0x7c-0x7f
Reserved
15.4
15.3.1
0x00
15.3
SLAVE RECEPTION
SLAVE TRANSMISSION
In 10-bit mode, the basic receive and transmit operations are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation with two address bytes
following a Start bit.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a 7-bit
address. The address detection protocol for the first byte
of a message address is identical for 7-bit and 10-bit
messages, but the bits being compared are different.
I2CADD holds the entire 10-bit address. Upon receiving an address following a Start bit, I2CRSR <7:3> is
compared against a literal 11110 (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and if R_W = 0, the
interrupt pulse is sent. The ADD10 bit will be cleared to
indicate a partial address match. If a match fails or
R_W = 1, the ADD10 bit is cleared and the module
returns to the Idle state.
The low byte of the address is then received and compared with I2CADD<7:0>. If an address match occurs,
the interrupt pulse is generated and the ADD10 bit is
set, indicating a complete 10-bit address match. If an
address match did not occur, the ADD10 bit is cleared
and the module returns to the Idle state.
15.4.1
Advance Information
DS70138C-page 91
dsPIC30F3014/4013
15.4.2
15.5
15.5.1
15.5.2
15.5.3
DS70138C-page 92
15.5.4
15.6
Advance Information
dsPIC30F3014/4013
15.7
Interrupts
15.8
Slope Control
2
15.9
IPMI Support
15.12.1
Transmission of a data byte, a 7-bit address, or the second half of a 10-bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the Buffer Full Flag (TBF) and
allow the baud rate generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. The Transmit Status Flag,
TRSTAT (I2CSTAT<14>), indicates that a master
transmit is in progress.
Advance Information
DS70138C-page 93
dsPIC30F3014/4013
15.12.2
EQUATION 15-1:
15.12.3
I2CBRG =
15.12.4
CY
( FFSCK
FCY
1,111,111
CLOCK ARBITRATION
15.12.5
MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-master operation support is achieved by bus arbitration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a 1 on SDA by letting SDA float high
while another master asserts a 0. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a 1 and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and reset the master
portion of the I2C port to its Idle state.
DS70138C-page 94
15.13.2
For the I2C, the I2CSIDL bit selects if the module will
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
Advance Information
0206
0208
020A
u = uninitialized bit
I2CCON
I2CSTAT
I2CADD
Legend:
TRSTAT
Bit 12
Bit 11
Bit 13
BCL
A10M
Bit 10
GCSTAT
DISSLW
Bit 9
ADD10
SMEN
Bit 8
IWCOL
GCEN
Bit 7
I2COV
STREN
Bit 6
Bit 3
Transmit Register
Receive Register
Bit 4
Address Register
D_A
ACKEN
S
RCEN
Bit 5
ACKDT
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
ACKSTAT
I2CEN
0204
I2CBRG
0202
Bit 14
0200
I2CRCV
Bit 15
I2CTRN
TABLE 15-2:
R_W
PEN
Bit 2
RBF
RSEN
Bit 1
TBF
SEN
Bit 0
Reset State
dsPIC30F3014/4013
Advance Information
DS70138C-page 95
dsPIC30F3014/4013
NOTES:
DS70138C-page 96
Advance Information
dsPIC30F3014/4013
16.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
16.1
FIGURE 16-1:
UTX8
Write
Transmit Control
Control TSR
Control Buffer
Generate Flags
Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
0 (Start)
UxTX
or UxATX
if ALTIO=1
1 (Stop)
Parity
Parity
Generator
16 Divider
Control
Signals
Note:
x = 1 or 2.
Advance Information
DS70138C-page 97
dsPIC30F3014/4013
FIGURE 16-2:
16
Write
Read
Read Read
UxMODE
Write
UxSTA
UxRX
or UxARX
if ALTIO=1
Load RSR
to Buffer
Receive Shift Register
(UxRSR)
Control
Signals
FERR
8-9
PERR
LPBACK
From UxTX
1
16 Divider
DS70138C-page 98
Advance Information
dsPIC30F3014/4013
16.2
16.2.1
1.
2.
3.
4.
16.2.4
5.
16.3.2
ALTERNATE I/O
16.2.3
Transmitting Data
16.3.1
16.2.2
16.3
16.3.3
Advance Information
DS70138C-page 99
dsPIC30F3014/4013
16.3.4
TRANSMIT INTERRUPT
16.4.2
b)
16.3.5
TRANSMIT BREAK
16.4.3
RECEIVE INTERRUPT
a)
b)
c)
16.4
Switching between the Interrupt modes during operation is possible, though generally not advisable during
normal operation.
16.4.1
Receiving Data
RECEIVING IN 8-BIT OR 9-BIT
DATA MODE
16.5
16.5.1
1.
2.
3.
4.
5.
DS70138C-page 100
a)
b)
c)
Advance Information
dsPIC30F3014/4013
16.5.2
16.6
16.5.3
16.5.4
IDLE STATUS
16.5.5
RECEIVE BREAK
Setting the ADDEN bit (UxSTA<5>) enables this special mode in which a 9th bit (URX8) value of 1 identifies the received word as an address, rather than data.
This mode is only applicable for 9-bit data communication. The URXISEL control bit does not have any
impact on interrupt generation in this mode since an
interrupt (if enabled) will be generated every time the
received word has the 9th bit set.
16.7
Loopback Mode
16.8
EQUATION 16-1:
BAUD RATE
Advance Information
DS70138C-page 101
dsPIC30F3014/4013
16.9
16.10.2
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
DS70138C-page 102
Advance Information
0212
0214
u = uninitialized bit
U1RXREG
U1BRG
Legend:
ALTIO
Bit 10
UTXBRK UTXEN
Bit 11
021E
u = uninitialized bit
U2BRG
Legend:
Bit 12
Bit 10
UTXBRK UTXEN
Bit 11
UTXBF
Bit 9
URX8
UTX8
TRMT
Bit 8
LPBACK
Bit 6
LPBACK
Bit 6
ABAUD
Bit 5
PERR
Bit 3
RIDLE
Bit 4
PERR
Bit 3
Receive Register
Transmit Register
RIDLE
Bit 4
Receive Register
Transmit Register
WAKE
Bit 7
URX8
UTX8
TRMT
Bit 8
ABAUD
Bit 5
WAKE
Bit 7
UTXBF
Bit 9
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
021A
021C
USIDL
Bit 13
Bit 14
UTXISEL
UARTEN
Bit 15
U2RXREG
0216
0218
U2MODE
U2STA
Bit 12
USIDL
U2TXREG
Addr.
SFR
Name
TABLE 16-2:
0210
U1TXREG
UARTEN
020E
UTXISEL
020C
U1MODE
U1STA
Bit 13
Bit 15
Bit 14
TABLE 16-1:
Bit 1
Bit 0
Reset State
Bit 1
OERR
FERR
OERR
PDSEL1 PDSEL0
Bit 2
FERR
Reset State
Bit 0
Bit 2
dsPIC30F3014/4013
Advance Information
DS70138C-page 103
dsPIC30F3014/4013
NOTES:
DS70138C-page 104
Advance Information
dsPIC30F3014/4013
17.0
CAN MODULE
17.1
Overview
17.2
Frame Types
Advance Information
DS70138C-page 105
dsPIC30F3014/4013
FIGURE 17-1:
BUFFERS
Acceptance Filter
RXF2
MESSAGE
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
TXB2
MESSAGE
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
MESSAGE
TXB1
MSGREQ
TXABT
TXLARB
TXERR
MTXBUFF
TXB0
A
c
c
e
p
t
R
X
B
0
Message
Queue
Control
Acceptance Mask
RXM0
Acceptance Filter
RXF3
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
Identifier
M
A
B
Data Field
Data Field
PROTOCOL
ENGINE
Note 1:
RERRCNT
TERRCNT
Transmit
Error
Counter
CRC Generator
R
X
B
1
Identifier
Receive
Error
Counter
Transmit Shift
A
c
c
e
p
t
Err Pas
Bus Off
Receive Shift
Protocol
Finite
State
Machine
CRC Check
Transmit
Logic
Bit
Timing
Logic
CiTX(1)
CiRX(1)
Bit Timing
Generator
DS70138C-page 106
Advance Information
dsPIC30F3014/4013
17.3
Modes of Operation
Initialization Mode
Disable Mode
Normal Operation Mode
Listen Only Mode
Loopback Mode
Error Recognition Mode
Note:
17.3.1
INITIALIZATION MODE
17.3.2
DISABLE MODE
17.3.3
17.3.4
17.3.5
17.3.6
LOOPBACK MODE
If the Loopback mode is activated, the module will connect the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
Advance Information
DS70138C-page 107
dsPIC30F3014/4013
17.4
17.4.1
Message Reception
17.4.4
RECEIVE BUFFERS
17.4.2
17.4.3
RECEIVE OVERRUN
17.4.5
RECEIVE ERRORS
17.4.6
RECEIVE INTERRUPTS
DS70138C-page 108
Advance Information
dsPIC30F3014/4013
Receive Error Interrupts:
A receive error interrupt will be indicated by the
ERRIF bit. This bit shows that an error condition
occurred. The source of the error can be determined by checking the bits in the CAN Interrupt
Status register, CiINTF.
- Invalid Message Received:
If any type of error occurred during reception of
the last message, an error will be indicated by
the IVRIF bit.
- Receiver Overrun:
The RXnOVR bit indicates that an overrun
condition occurred.
- Receiver Warning:
The RXWAR bit indicates that the receive error
counter (RERRCNT<7:0>) has reached the
warning limit of 96.
- Receiver Error Passive:
The RXEP bit indicates that the receive error
counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
17.5
17.5.1
Message Transmission
TRANSMIT BUFFERS
17.5.2
17.5.3
17.5.4
ABORTING MESSAGE
TRANSMISSION
17.5.5
TRANSMISSION ERRORS
TRANSMISSION SEQUENCE
Advance Information
DS70138C-page 109
dsPIC30F3014/4013
17.5.6
17.6
TRANSMIT INTERRUPTS
Transmit Interrupt:
At least one of the three transmit buffers is empty
(not scheduled) and can be loaded to schedule a
message for transmission. Reading the TXnIF
flags will indicate which transmit buffer is available
and caused the interrupt.
FIGURE 17-2:
17.6.1
BIT TIMING
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
TQ. By definition, the nominal bit time has a minimum
of 8 TQ and a maximum of 25 TQ. Also, by definition,
the minimum nominal bit time is 1 sec corresponding
to a maximum bit rate of 1 MHz.
Input Signal
Sync
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sync
Sample Point
TQ
DS70138C-page 110
Advance Information
dsPIC30F3014/4013
17.6.2
PRESCALER SETTING
17.6.5
EQUATION 17-1:
TQ = 2 (BRP<5:0> + 1) / FCAN
17.6.3
17.6.4
PHASE SEGMENTS
17.6.6
PROPAGATION SEGMENT
SAMPLE POINT
SYNCHRONIZATION
17.6.6.1
Hard Synchronization
17.6.6.2
Resynchronization
Advance Information
DS70138C-page 111
0308
030C
0310
0312
0314
0318
0320
C1RXF2SID
C1RXF2EIDH
C1RXF2EIDL
C1RXF3SID
C1RXF3EIDH 031A
031C
C1RXF1EIDL
C1RXF3EIDL
C1RXF4SID
DS70138C-page 112
Advance Information
u = uninitialized bit
0354
Legend:
C1TX1DLC
034E
C1TX2CON
0350
034C
C1TX2B4
0352
034A
C1TX2B3
C1TX1EID
0348
C1TX2B2
C1TX1SID
0346
C1RXM1EIDL 033C
0344
C1RXM1EIDH 033A
C1TX2DLC
0338
C1RXM1SID
C1TX2B1
0334
C1RXM0EIDL
0342
C1RXM0EIDH 0332
0340
0330
C1RXM0SID
C1TX2EID
032C
C1RXF5EIDL
C1TX2SID
TXRTR
TXRTR
Bit 3
TXRB1
TXRB1
Bit 2
TXREQ
DLC<3:0>
DLC<3:0>
TXRB0
TXRB0
Bit 4
0328
C1RXF5EIDH 032A
C1RXF5SID
Bit 5
0324
Bit 6
C1RXF4EIDL
Bit 7
0322
Bit 8
C1RXF4EIDH
Bit 9
Bit 10
C1RXF1EIDH 030A
Bit 11
C1RXF1SID
Bit 12
Bit 13
0302
Bit 14
0304
Bit 15
C1RXF0EIDL
0300
C1RXF0EIDH
Addr.
SFR Name
C1RXF0SID
TABLE 17-1:
Bit 0
SRR
Reset State
MIDE
MIDE
TXPRI<1:0>
SRR
Bit 1
dsPIC30F3014/4013
Advance Information
0362
0364
0366
0368
036A
036C
036E
0370
0372
0374
0376
0378
037A
037C
037E
0380
0382
0384
0386
0388
038A
038C
038E
0390
C1TX0SID
C1TX0EID
C1TX0DLC
C1TX0B1
C1TX0B2
C1TX0B3
C1TX0B4
C1TX0CON
C1RX1SID
C1RX1EID
C1RX1DLC
C1RX1B1
C1RX1B2
C1RX1B3
C1RX1B4
C1RX1CON
C1RX0SID
C1RX0EID
C1RX0DLC
C1RX0B1
C1RX0B2
C1RX0B3
C1RX0B4
C1RX0CON
C1CTRL
Legend:
Bit 12
Bit 11
WAKFIL
CSIDLE
ABAT
CANCKS
CANCAP
TXRB1
Bit 8
SEG2PH<2:0>
DLC<3:0>
RXFUL
RXRTRRO
RXRB0
SEG2PHTS
SAM
SJW<1:0>
OPMODE<2:0>
RXFUL
TXREQ
SRR
DLC<3:0>
FILHIT<2:0>
SRR
Reset State
uuuu uuuu uuuu uuuu
TXPRI<1:0>
SRR
DLC<3:0>
Bit 0
TXPRI<1:0>
Bit 1
BRP<5:0>
PRSEG<2:0>
ICODE<2:0>
SEG1PH<2:0>
RXRB0
TXREQ
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
TXRB0
Bit 7
TXRTR
Bit 9
REQOP<2:0>
Bit 10
Bit 13
Bit 14
Bit 15
u = uninitialized bit
0394
0360
C1TX1CON
C1CFG2
035E
C1TX1B4
0392
035C
C1TX1B3
C1CFG1
0358
035A
C1TX1B2
0356
Addr.
C1TX1B1
SFR Name
TABLE 17-1:
dsPIC30F3014/4013
DS70138C-page 113
0398
039A
C1EC
DS70138C-page 114
u = uninitialized bit
RX1OVR
Bit 14
TXEP
Bit 12
RXEP
Bit 11
Bit 9
Bit 8
Bit 10
TXBO
Bit 13
IVRIE
IVRIF
Bit 7
WAKIE
WAKIF
Bit 6
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Legend:
RX0OVR
0396
C1INTF
C1INTE
Bit 15
Addr.
SFR Name
TABLE 17-1:
TX2IE
TX2IF
Bit 4
TX1IE
TX1IF
Bit 3
TX0IF
Bit 2
TX0IE
ERRIE
ERRIF
Bit 5
RX1E
RX1IF
Bit 1
Reset State
Bit 0
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
18.0
DATA CONVERTER
INTERFACE (DCI) MODULE
18.1
Module Introduction
18.2
18.2.3
CSDI PIN
18.2.3.1
COFS PIN
18.2.4
Data values are always stored left justified in the buffers since most Codec data is represented as a signed
2s complement fractional number. If the received word
length is less than 16 bits, the unused LS bits in the
receive buffer registers are set to 0 by the module. If
the transmitted word length is less than 16 bits, the
unused LS bits in the transmit buffer register are
ignored by the module. The word length setup is
described in subsequent sections of this document.
18.2.5
TRANSMIT/RECEIVE SHIFT
REGISTER
18.2.1
18.2.6
CSCK PIN
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON2
SFR. When configured as an output, the serial clock is
provided by the dsPIC30F. When configured as an
input, the serial clock must be provided by an external
device.
18.2.2
CSDO PIN
The DCI module contains a buffer control unit for transferring data between the shadow buffer memory and
the serial shift register. The buffer control unit is a simple 2-bit address counter that points to word locations
in the shadow buffer memory. For the receive memory
space (high address portion of DCI buffer memory), the
address counter is concatenated with a 0 in the MSb
location to form a 3-bit address. For the transmit memory space (high portion of DCI buffer memory), the
address counter is concatenated with a 1 in the MSb
location.
Note:
Advance Information
DS70138C-page 115
dsPIC30F3014/4013
FIGURE 18-1:
Sample Rate
CSCK
Generator
FSD
Word Size Selection bits
Frame
Synchronization
Generator
COFS
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
Transmit Buffer
Registers w/Shadow
0
DCI Shift Register
CSDI
CSDO
DS70138C-page 116
Advance Information
dsPIC30F3014/4013
18.3
18.3.1
18.3.4
18.3.2
18.3.3
EQUATION 18-1:
COFSG PERIOD
Multi-Channel mode
I2S mode
AC-Link mode (16-bit)
AC-Link mode (20-bit)
18.3.5
Advance Information
DS70138C-page 117
dsPIC30F3014/4013
18.3.6
FIGURE 18-2:
CSDI/CSDO
FIGURE 18-3:
MSB
LSB
CSDO or CSDI
SYNC
FIGURE 18-4:
CSCK
CSDI or CSDO
MSB
LSB MSB
LSB
WS
Note:
A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length - this will
be system dependent.
DS70138C-page 118
Advance Information
dsPIC30F3014/4013
18.3.7
EQUATION 18-2:
TABLE 18-1:
FBCK =
FCY
2 (BCG + 1)
FS (KHz)
FCSCK/FS
FCSCK (MHz)(1)
FOSC (MHZ)
PLL
FCY (MIPS)
BCG(2)
256
2.048
8.192
8.192
12
256
3.072
6.144
12.288
32
32
1.024
8.192
16.384
44.1
32
1.4112
5.6448
11.2896
48
64
3.072
6.144
16
24.576
Note 1:
2:
When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
operation of the DCI module.
When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must
meet the device timing requirements.
Advance Information
DS70138C-page 119
dsPIC30F3014/4013
18.3.8
18.3.11
18.3.9
DATA JUSTIFICATION
CONTROL BIT
18.3.10
DS70138C-page 120
18.3.12
18.3.13
SYNCHRONOUS DATA
TRANSFERS
Advance Information
dsPIC30F3014/4013
18.3.14
18.3.15
18.3.16
Note:
18.3.17
Note:
The transmit status bits only indicate status for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
Advance Information
DS70138C-page 121
dsPIC30F3014/4013
18.3.18
18.4
The SLOT<3:0> status bits in the DCISTAT SFR indicate the current active time slot. These bits will correspond to the value of the frame sync generator counter.
The user may poll these status bits in software when a
DCI interrupt occurs to determine what time slot data
was last received and which time slot data should be
loaded into the TXBUF registers.
18.3.19
18.3.20
18.3.21
DS70138C-page 122
18.5
18.5.1
18.5.2
If the DCISIDL control bit is cleared (default), the module will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
18.6
18.6.1
Advance Information
dsPIC30F3014/4013
18.6.2
18.7.1
The 20-bit AC-Link mode allows all bits in the data time
slots to be transmitted and received but does not maintain data alignment in the TXBUF and RXBUF
registers.
The 20-bit AC-Link mode functions similar to the MultiChannel mode of the DCI module, except for the duty
cycle of the frame synchronization signal. The AC-Link
frame synchronization signal should remain high for 16
CSCK cycles and should be low for the following
240 cycles.
The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
18.7.2
Advance Information
DS70138C-page 123
DS70138C-page 124
RSE14
TSE14
RSE13
TSE13
DCISIDL
RSE12
TSE12
Bit 11
RSE11
TSE11
SLOT3
BLEN1
DLOOP
Bit 10
RSE10
TSE10
SLOT2
BLEN0
CSCKD
Bit 9
Bit 8
Bit 7
RSE8
TSE8
SLOT0
Bit 6
CSDOM
RSE7
TSE7
Bit 5
DJST
RSE6
TSE6
RSE5
TSE5
BCG<11:0>
COFSG<3:0>
COFSD UNFM
RSE9
TSE9
SLOT1
CSCKE
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
u = uninitialized bit
025A
TXBUF1
Legend:
0258
TXBUF0
025E
0256
RXBUF3
TXBUF3
0254
RXBUF2
025C
0252
RXBUF1
TXBUF2
0250
RXBUF0
RSE15
TSE15
0248
024C
TSCON
RSCON
0246
DCISTAT
0242
0244
DCICON2
DCICON3
DCIEN
Bit 12
0240
Bit 13
Bit 15
Addr.
SFR Name
DCICON1
Bit 14
TABLE 18-2:
TSE3
ROV
Bit 3
RSE4 RSE3
TSE4
Bit 4
RSE2
TSE2
RFUL
Bit 2
Bit 1
RSE1
TSE1
TUNF
WS<3:0>
COFSM1
Bit 0
Reset State
RSE0
TSE0
TMPTY
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
19.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The ADCON1, ADCON2 and ADCON3 registers control the operation of the A/D module. The ADCHS register selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
FIGURE 19-1:
Note:
VREF+
VREF-
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
DAC
0001
0010
12-bit SAR
0011
Conversion Logic
0100
16-word, 12-bit
Dual Port
RAM
0101
0110
0111
1000
Sample/Sequence
Control
Sample
Bus Interface
AN1
Comparator
0000
Data
Format
AN0
1001
1010
Input
Switches
1011
Input MUX
Control
1100
VREFAN1
S/H
CH0
Note: The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins.
Since these pins are not physically present on the device, conversion results from these pins will read 0.
Advance Information
DS70138C-page 125
dsPIC30F3014/4013
19.1
19.3
19.2
Conversion Operation
2.
3.
4.
5.
6.
7.
DS70138C-page 126
Advance Information
The ADCHS, ADPCFG and ADCSSL registers allow the application to configure
AN13-AN15 as analog input pins. Since
these pins are not physically present on
the device, conversion results from these
pins will read 0.
dsPIC30F3014/4013
19.4
EXAMPLE 19-1:
The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
TAD
1
TCY
667 nsec
=2
33.33 nsec
= 39
ADCS<5:0> = 2
Therefore,
Set ADCS<5:0> = 39
TCY
(ADCS<5:0> + 1)
2
33.33 nsec
=
(39 + 1)
2
Actual TAD =
= 667 nsec
If SSRC<2:0> = 111 and SAMC<4:0> = 00001
19.5
Aborting a Conversion
19.6
EQUATION 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
= 1 TAD + 14 TAD
= 15 x 667 nsec
Therefore,
Sampling Rate =
1
(15 x 667 nsec)
= ~100 kHz
19.7
Advance Information
DS70138C-page 127
dsPIC30F3014/4013
FIGURE 19-2:
Rs
VA
RIC 250
VT = 0.6V
ANx
Sampling
Switch
RSS 3 k
RSS
CPIN
VT = 0.6V
I leakage
500 nA
CHOLD
= DAC capacitance
= 18 pF
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
RSS
= sampling switch resistance
CHOLD
= sample/hold capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 2.5 k.
19.8
19.9
19.9.1
DS70138C-page 128
19.9.2
Advance Information
dsPIC30F3014/4013
FIGURE 19-3:
RAM Contents:
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Signed Integer
Integer
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
Advance Information
DS70138C-page 129
DS70138C-page 130
u = uninitialized bit
Advance Information
CSSL12
Bit 8
FORM<1:0>
Bit 9
CH0SB<3:0>
SAMC<4:0>
CSCNA
Bit 10
ADRC
BUFS
Bit 7
CSSL11
CSSL10 CSSL9
CSSL8
CSSL7
Bit 5
CSSL6
CSSL5
PCFG6 PCFG5
Bit 6
SSRC<2:0>
CH0NB
Bit 11
Bit 12
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
Legend:
ADSIDL
Bit 13
02A8
02AA
ADCSSL
02A6
ADCHS
VCFG<2:0>
ADPCFG
02A2
02A4
ADCON2
02A0
ADCON1
ADCON3
029E
ADCBUFF
ADCBUFE 029C
ADON
ADCBUFB
0294
ADCBUFA
ADCBUFD 029A
0292
ADCBUF9
0290
ADCBUF8
028E
ADCBUF7
ADCBUFC 0298
028C
ADCBUF6
028A
ADCBUF5
0288
ADCBUF4
0296
0286
ADCBUF3
0284
ADCBUF2
Bit 14
Bit 15
0280
0282
ADCBUF0
ADCBUF1
Addr.
SFR
Name
TABLE 19-1:
Bit 3
CSSL4
PCFG4
CH0NA
ASAM
Bit 2
BUFM
SAMP
Bit 1
CSSL3
CSSL2
CSSL1
CH0SA<3:0>
ADCS<5:0>
SMPI<3:0>
Bit 4
CSSL0
PCFG0
ALTS
DONE
Bit 0
Reset State
dsPIC30F3014/4013
dsPIC30F3014/4013
20.0
SYSTEM INTEGRATION
20.1
There are several features intended to maximize system reliability, minimize cost through elimination of
external components, provide Power Saving Operating
modes and offer code protection:
Oscillator Selection
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
Watchdog Timer (WDT)
Power Saving Modes (Sleep and Idle)
Code Protection
Unit ID Locations
In-Circuit Serial Programming (ICSP)
Advance Information
DS70138C-page 131
dsPIC30F3014/4013
TABLE 20-1:
Oscillator Mode
Description
XTL
XT
XT w/ PLL 4x
XT w/ PLL 8x
XT w/ PLL 16x
LP
HS
HS/2 w/ PLL 4x
HS/2 w/ PLL 8x
HS/3 w/ PLL 4x
HS/3 w/ PLL 8x
EC
ECIO
EC w/ PLL 4x
External clock input (0-40 MHz), OSC2 pin is I/O, 4x PLL enabled(1)
EC w/ PLL 8x
External clock input (0-40 MHz), OSC2 pin is I/O, 8x PLL enabled(1)
EC w/ PLL 16x
External clock input (0-40 MHz), OSC2 pin is I/O, 16x PLL enabled(1)
ERC
ERCIO
FRC
FRC w/ PLL 4x
FRC w/ PLL 8x
LPRC
Note 1:
2:
3:
DS70138C-page 132
Advance Information
dsPIC30F3014/4013
FIGURE 20-1:
OSC1
OSC2
FPLL
Primary
Oscillator
PLL
PLL
Lock
COSC<2:0>
Primary Osc
NOSC<2:0>
Primary
Oscillator
OSWEN
Stability Detector
POR Done
Oscillator
Start-up
Timer
Clock
Secondary Osc
SOSCO
SOSCI
32 kHz LP
Oscillator
Switching
and Control
Block
Secondary
Oscillator
Stability Detector
Programmable
Clock Divider System
Clock
2
POST<1:0>
TUN<3:0>
Internal Fast RC
Oscillator (FRC)
Internal Low
Power RC
Oscillator (LPRC)
FCKSM<1:0>
2
LPRC
Fail-Safe Clock
Monitor (FSCM)
CF
Oscillator Trap
To Timer1
Advance Information
DS70138C-page 133
dsPIC30F3014/4013
20.2
Oscillator Configurations
20.2.1
20.2.2
TABLE 20-2:
Oscillator Mode
ECIO w/ PLL 4x
Oscillator
Source
FOS<2:0>
OSC2
Function
FPR<4:0>
PLL
I/O
ECIO w/ PLL 8x
PLL
I/O
PLL
I/O
FRC w/ PLL 4x
PLL
I/O
FRC w/ PLL 8x
PLL
I/O
PLL
I/O
XT w/ PLL 4x
PLL
OSC2
XT w/ PLL 8x
PLL
OSC2
XT w/ PLL 16x
PLL
OSC2
HS2 w/ PLL 4x
PLL
OSC2
HS2 w/ PLL 8x
PLL
OSC2
PLL
OSC2
HS3 w/ PLL 4x
PLL
OSC2
HS3 w/ PLL 8x
PLL
OSC2
PLL
OSC2
ECIO
External
I/O
XT
External
OSC2
HS
External
OSC2
EXT
External
CLKOUT
ERC
External
CLKOUT
ERCIO
External
I/O
XTL
External
OSC2
LP
Secondary
(Notes 1, 2)
FRC
Internal FRC
(Notes 1, 2)
LPRC
Internal LPRC
(Notes 1, 2)
Note 1:
2:
DS70138C-page 134
Advance Information
dsPIC30F3014/4013
20.2.3
LP OSCILLATOR CONTROL
Note:
20.2.4
TABLE 20-3:
FIN
PLL
Multiplier
FOUT
4 MHz-10 MHz
x4
16 MHz-40 MHz
4 MHz-10 MHz
x8
32 MHz-80 MHz
4 MHz-7.5 MHz
x16
64 MHz-120 MHz
20.2.5
TABLE 20-4:
TUN<3:0>
Bits
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
20.2.6
FRC TUNING
FRC Frequency
+ 10.5%
+ 9.0%
+ 7.5%
+ 6.0%
+ 4.5%
+ 3.0%
+ 1.5%
Center Frequency (oscillator is
running at calibrated frequency)
- 1.5%
- 3.0%
- 4.5%
- 6.0%
- 7.5%
- 9.0%
- 10.5%
- 12.0%
Advance Information
DS70138C-page 135
dsPIC30F3014/4013
20.2.7
Primary
Secondary
Internal FRC
Internal LPRC
20.2.8
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
DS70138C-page 136
Advance Information
dsPIC30F3014/4013
20.3
Note:
REGISTER 20-1:
Upper Byte:
U-0
R-y
R-y
R-y
COSC<2:0>
U-0
R/W-y
R/W-y
R/W-y
NOSC<2:0>
bit 15
bit 8
Lower Byte:
R/W-0
R/W-0
POST<1:0>
bit 7
bit 15
R-0
LOCK
U-0
R/W-0
CF
U-0
R/W-0
LPOSCEN
R/W-0
OSWEN
bit 0
Unimplemented: Read as 0
Unimplemented: Read as 0
bit 10-8
bit 7-6
bit 5
bit 4
Unimplemented: Read as 0
Advance Information
DS70138C-page 137
dsPIC30F3014/4013
REGISTER 20-1:
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS70138C-page 138
Advance Information
dsPIC30F3014/4013
REGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER
Upper Byte:
U-0
bit 15
U-0
U-0
Lower Byte:
U-0
bit 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
bit 8
R/W-0
R/W-0
TUN<3:0>
R/W-0
bit 0
bit 15-4
Unimplemented: Read as 0
bit 3-0
TUN<3:0>: Lower two bits of TUN field. The four bit field specified by TUN<3:0> specifies the user tuning
capability for the internal fast RC oscillator (nominal 7.37 MHz).
0111 = Maximum Frequency
0110 =
0101 =
0100 =
0011 =
0010 =
0001 =
0000 = Center Frequency, Oscillator is running at calibrated frequency
1111 =
1110 =
1101 =
1100 =
1011 =
1010 =
1001 =
1000 =Minimum Frequency
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Advance Information
DS70138C-page 139
dsPIC30F3014/4013
REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER
Upper Byte:
U
bit 23
Middle Byte:
R/P
R/P
FCKSM<1:0>
bit 15
Lower Byte:
U
bit 7
R/P
bit 16
R/P
FOS<2:0>
R/P
bit 8
R/P
R/P
R/P
FPR<4:0>
R/P
R/P
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3-0
DS70138C-page 140
W = Writable bit
Advance Information
dsPIC30F3014/4013
20.4
Reset
The
PIC18F2220/2320/4220/4320
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
differentiates
FIGURE 20-2:
Different registers are affected in different ways by various Reset conditions. Most registers are not affected
by a WDT wake-up since this is viewed as the resumption of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in Table 20-4. These bits are
used in software to determine the nature of the Reset.
A block diagram of the On-Chip Reset Circuit is shown
in Figure 20-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
POR
VDD Rise
Detect
VDD
Brown-out
Reset
BOR
BOREN
R
SYSRST
Trap Conflict
Illegal Opcode/
Uninitialized W Register
20.4.1
Advance Information
DS70138C-page 141
dsPIC30F3014/4013
FIGURE 20-3:
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-4:
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
FIGURE 20-5:
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL Reset
DS70138C-page 142
Advance Information
dsPIC30F3014/4013
20.4.1.1
20.4.1.2
FIGURE 20-6:
20.4.2
VDD
D
Note 1:
2:
3:
Note:
2.0V
2.7V
4.2V
4.5V
Note:
R
R1
BOR: PROGRAMMABLE
BROWN-OUT RESET
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
MCLR
dsPIC30F
Advance Information
DS70138C-page 143
dsPIC30F3014/4013
Table 20-4 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table implies that all the
bits are negated prior to the action specified in the
condition column.
TABLE 20-4:
Condition
Program
Counter
Power-on Reset
0x000000
Brown-out Reset
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
PC + 2
WDT Wake-up
PC +
2(1)
0x000004
Trap Reset
0x000000
0x000000
0
1
0
0
0
0
0
0
0
u = unchanged, x = unknown, - = unimplemented bit, read as 0
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
TABLE 20-5:
Condition
Program
Counter
Power-on Reset
0x000000
Brown-out Reset
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
WDT Wake-up
PC + 2
PC + 2(1)
0x000004
Trap Reset
0x000000
0x000000
u
1
u
u
u
u
u
u
u
u = unchanged, x = unknown, - = unimplemented bit, read as 0
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70138C-page 144
Advance Information
dsPIC30F3014/4013
20.5
20.5.1
20.7
20.5.2
20.7.1
20.6
SLEEP MODE
Advance Information
DS70138C-page 145
dsPIC30F3014/4013
Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level
will be able to wake-up the processor. The processor will
process the interrupt and branch to the ISR. The Sleep
status bit in the RCON register is set upon wake-up.
Note:
20.7.2
IDLE MODE
20.8
The configuration bits in each device configuration register specify some of the Device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming (ICSP) feature of
the device. Each device configuration register is a
24-bit register, but only the lower 16 bits of each register are used to hold configuration data. There are four
device configuration registers available to the user:
1.
2.
3.
4.
DS70138C-page 146
Note:
Advance Information
dsPIC30F3014/4013
20.9
The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a
peripheral is disabled via the appropriate PMD control
bit, the peripheral is in a minimum power consumption
state. The control and status registers associated with
the peripheral will also be disabled so writes to those
registers will have no effect and read values will be
invalid.
A peripheral module will only be enabled if both the
associated bit in the the PMD register is cleared and
the peripheral is supported by the specific dsPIC variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding module is disabled after a delay of 1 instruction
cycle. Similarly, if a PMD bit is cleared, the
corresponding module is enabled after a
delay of 1 instruction cycle (assuming the
module control registers are already
configured to enable module operation).
Note:
2.
Advance Information
DS70138C-page 147
DS70138C-page 148
0772
PMD2
IC8MD
IC7MD
T2MD
T3MD
T4MD
T5MD
Bit 12
LVDEN
COSC<2:0>
T1MD
Bit 11
Bit 9
IC2MD
NOSC<2:0>
LVDL<3:0>
Bit 10
IC1MD
DCIMD
Bit 8
SWR
Bit 6
I2CMD
U2MD
POST<1:0>
EXTR
Bit 7
U1MD
LOCK
SWDTEN
Bit 5
F80002
F80004
F8000A
FWDT
FBORPOR
FGS
Bit 14
FWDTEN
MCLREN
FCKSM<1:0>
Bit 15
Bits 23-16
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
FOS<2:0>
Bit 8
Note: Refer to dsPIC30F Family Reference Manual (DS70046) for descriptions of register bit fields.
F80000
Addr.
FOSC
File Name
Bit 13
WDTO
Bit 4
TUN2
Idle
Bit 2
OC4MD OC3MD
SPI1MD
TUN3
CF
Sleep
Bit 3
BOREN
Bit 7
Bit 6
TUN1
Bit 4
OC2MD
C1MD
BORV<1:0>
FWPSA<1:0>
Bit 5
BOR
Bit 1
POR
Bit 0
(Note 2)
(Note 1)
Reset State
Bit 3
Bit 1
Bit 0
GCP
GWRP
FPWRT<1:0>
FWPSB<3:0>
FPR<4:0>
Bit 2
TUN0
LPOSCEN OSWEN
For the dsPIC30F3014 device, the DCIMD, T4MD, T5MD, OC3MD, OC4,MD, IC7MD and IC8MD bits do not perform any function.
TABLE 20-7:
3:
0770
PMD1
Bit 14
Bit 15
0744
OSCTUN
1:
2:
0742
Note
0740
OSCCON
Addr.
RCON
SFR
Name
TABLE 20-6:
dsPIC30F3014/4013
Advance Information
dsPIC30F3014/4013
21.0
Advance Information
DS70138C-page 149
dsPIC30F3014/4013
Most single word instructions are executed in a single
instruction cycle, unless a conditional test is true or
the program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA (unconditional/computed branch), indirect CALL/
GOTO, all table reads and writes, and RETURN/RETFIE
instructions, which are single word instructions but take
two or three cycles. Certain instructions that involve
skipping over the subsequent instruction require either
TABLE 21-1:
Field
Description
#text
(text)
[text]
{ }
<n:m>
.b
.d
.S
.w
Acc
AWB
bit4
C, DC, N, OV, Z
MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
lit1
lit4
lit5
lit8
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
lit16
lit23
None
DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
PC
Program Counter
Slit10
Slit16
Slit6
DS70138C-page 150
Advance Information
dsPIC30F3014/4013
TABLE 21-1:
Field
Description
Wb
Wd
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wm*Wm
Wm*Wn
Wn
Wnd
Wns
WREG
Ws
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
Wxd
Wy
Wyd
Advance Information
DS70138C-page 151
dsPIC30F3014/4013
TABLE 21-2:
Base
Instr
#
1
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
ADD
Acc
Add Accumulators
ADD
f = f + WREG
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
OA,OB,SA,SB
ADDC
f = f + WREG + (C)
C,DC,N,OV,Z
ADDC
f,WREG
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
C,DC,N,OV,Z
AND
f = f .AND. WREG
N,Z
AND
f,WREG
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
N,Z
ASR
C,N,OV,Z
ASR
f,WREG
C,N,OV,Z
ASR
Ws,Wd
C,N,OV,Z
ASR
Wb,Wns,Wnd
N,Z
ASR
Wb,#lit5,Wnd
N,Z
BCLR
f,#bit4
Bit Clear f
None
BCLR
Ws,#bit4
Bit Clear Ws
None
BRA
C,Expr
Branch if Carry
1 (2)
None
None
BRA
GE,Expr
1 (2)
BRA
GEU,Expr
1 (2)
None
BRA
GT,Expr
1 (2)
None
BRA
GTU,Expr
1 (2)
None
BRA
LE,Expr
1 (2)
None
BRA
LEU,Expr
1 (2)
None
BRA
LT,Expr
1 (2)
None
BRA
LTU,Expr
1 (2)
None
BRA
N,Expr
Branch if Negative
1 (2)
None
BRA
NC,Expr
1 (2)
None
BRA
NN,Expr
1 (2)
None
BRA
NOV,Expr
1 (2)
None
BRA
NZ,Expr
1 (2)
None
BRA
OA,Expr
1 (2)
None
BRA
OB,Expr
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1 (2)
None
BRA
SA,Expr
1 (2)
None
BRA
SB,Expr
1 (2)
None
BRA
Expr
Branch Unconditionally
None
BRA
Z,Expr
Branch if Zero
1 (2)
None
BRA
Wn
Computed Branch
None
BSET
f,#bit4
Bit Set f
None
BSET
Ws,#bit4
Bit Set Ws
None
BSW.C
Ws,Wb
None
BSW.Z
Ws,Wb
None
DS70138C-page 152
Advance Information
dsPIC30F3014/4013
TABLE 21-2:
Base
Instr
#
9
10
11
12
13
Assembly
Mnemonic
BTG
BTSC
BTSS
BTST
BTSTS
14
CALL
15
CLR
Assembly Syntax
f,#bit4
Bit Toggle f
Ws,#bit4
Bit Toggle Ws
None
BTSC
f,#bit4
1
(2 or 3)
None
BTSC
Ws,#bit4
1
(2 or 3)
None
BTSS
f,#bit4
1
(2 or 3)
None
BTSS
Ws,#bit4
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
Ws,#bit4
Bit Test Ws to C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
BTST.C
Ws,Wb
BTST.Z
Ws,Wb
BTSTS
f,#bit4
Z
C
BTSTS.C
Ws,#bit4
BTSTS.Z
Ws,#bit4
CALL
lit23
Call subroutine
None
CALL
Wn
None
CLR
f = 0x0000
None
CLR
WREG
WREG = 0x0000
None
CLR
Ws
Ws = 0x0000
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
OA,OB,SA,SB
WDTO,Sleep
f=f
N,Z
COM
f,WREG
WREG = f
N,Z
COM
Ws,Wd
Wd = Ws
N,Z
CP
C,DC,N,OV,Z
17
COM
COM
20
21
CP0
CP1
CPB
None
BTST.C
CLRWDT
19
Status Flags
Affected
BTG
CLRWDT
CP
# of
# of
Words Cycles
BTG
16
18
Description
CP
Wb,#lit5
C,DC,N,OV,Z
CP
Wb,Ws
C,DC,N,OV,Z
CP0
C,DC,N,OV,Z
CP0
Ws
C,DC,N,OV,Z
C,DC,N,OV,Z
CP1
CP1
Ws
C,DC,N,OV,Z
CPB
C,DC,N,OV,Z
CPB
Wb,#lit5
C,DC,N,OV,Z
CPB
Wb,Ws
C,DC,N,OV,Z
22
CPSEQ
CPSEQ
Wb, Wn
1
(2 or 3)
None
23
CPSGT
CPSGT
Wb, Wn
1
(2 or 3)
None
24
CPSLT
CPSLT
Wb, Wn
1
(2 or 3)
None
25
CPSNE
CPSNE
Wb, Wn
1
(2 or 3)
None
26
DAW
DAW
Wn
Wn = decimal adjust Wn
27
DEC
DEC
f = f -1
C,DC,N,OV,Z
28
DEC2
DEC
f,WREG
WREG = f -1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws - 1
C,DC,N,OV,Z
C,DC,N,OV,Z
DEC2
f = f -2
DEC2
f,WREG
WREG = f -2
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws - 2
C,DC,N,OV,Z
Advance Information
DS70138C-page 153
dsPIC30F3014/4013
TABLE 21-2:
Base
Instr
#
Assembly
Mnemonic
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
29
DISI
DISI
#lit14
None
30
DIV
DIV.S
Wm,Wn
18
N,Z,C,OV
DIV.SD
Wm,Wn
18
N,Z,C,OV
DIV.U
Wm,Wn
18
N,Z,C,OV
DIV.UD
Wm,Wn
18
N,Z,C,OV
N,Z,C,OV
31
DIVF
DIVF
Wm,Wn
18
32
DO
DO
#lit14,Expr
None
DO
Wn,Expr
None
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
OA,OB,OAB,
SA,SB,SAB
34
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
OA,OB,OAB,
SA,SB,SAB
35
EXCH
EXCH
Wns,Wnd
None
36
FBCL
FBCL
Ws,Wnd
37
FF1L
FF1L
Ws,Wnd
38
FF1R
FF1R
Ws,Wnd
39
GOTO
GOTO
Expr
Go to address
None
GOTO
Wn
Go to indirect
None
40
41
42
INC
INC2
IOR
INC
f=f+1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
C,DC,N,OV,Z
INC2
f=f+2
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
C,DC,N,OV,Z
IOR
f = f .IOR. WREG
N,Z
IOR
f,WREG
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
N,Z
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
OA,OB,OAB,
SA,SB,SAB
44
LNK
LNK
#lit14
None
45
LSR
LSR
C,N,OV,Z
LSR
f,WREG
C,N,OV,Z
LSR
Ws,Wd
C,N,OV,Z
LSR
Wb,Wns,Wnd
N,Z
LSR
Wb,#lit5,Wnd
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
OA,OB,OAB,
SA,SB,SAB
43
46
47
48
MAC
MOV
MOVSAC
MOV
f,Wn
Move f to Wn
None
MOV
Move f to f
N,Z
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
None
MOV.b
#lit8,Wn
None
MOV
Wn,f
Move Wn to f
None
MOV
Wso,Wdo
Move Ws to Wd
None
MOV
WREG,f
Move WREG to f
N,Z
MOV.D
Wns,Wd
None
MOV.D
Ws,Wnd
None
None
MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB
DS70138C-page 154
Advance Information
dsPIC30F3014/4013
TABLE 21-2:
Base
Instr
#
49
Assembly
Mnemonic
MPY
Assembly Syntax
Multiply Wm by Wn to Accumulator
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
None
OA,OB,OAB,
SA,SB,SAB
MPY.N
MPY.N
MSC
MSC
52
MUL
54
55
NOP
POP
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
MUL.SS
Wb,Ws,Wnd
None
MUL.SU
Wb,Ws,Wnd
None
MUL.US
Wb,Ws,Wnd
None
MUL.UU
Wb,Ws,Wnd
None
MUL.SU
Wb,#lit5,Wnd
None
MUL.UU
Wb,#lit5,Wnd
None
MUL
W3:W2 = f * WREG
None
NEG
Acc
Negate Accumulator
OA,OB,OAB,
SA,SB,SAB
NEG
f=f+1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
C,DC,N,OV,Z
NEG
Ws,Wd
C,DC,N,OV,Z
Wd = Ws + 1
NOP
No Operation
None
NOPR
No Operation
None
POP
None
POP
Wdo
None
POP.D
Wnd
None
All
None
None
POP.S
56
PUSH
Status Flags
Affected
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
50
NEG
# of
# of
Words Cycles
MPY
51
53
Description
PUSH
PUSH
Wso
PUSH.D
Wns
None
None
WDTO,Sleep
PUSH.S
57
PWRSAV
PWRSAV
58
RCALL
RCALL
Expr
Relative Call
None
RCALL
Wn
Computed Call
None
59
REPEAT
#lit1
REPEAT
#lit14
None
REPEAT
Wn
None
60
RESET
RESET
None
61
RETFIE
RETFIE
3 (2)
None
62
RETLW
RETLW
None
63
RETURN
RETURN
64
RLC
RLC
65
66
67
RLNC
RRC
RRNC
#lit10,Wn
3 (2)
3 (2)
None
C,N,Z
RLC
f,WREG
C,N,Z
RLC
Ws,Wd
C,N,Z
N,Z
RLNC
RLNC
f,WREG
N,Z
RLNC
Ws,Wd
N,Z
C,N,Z
RRC
RRC
f,WREG
C,N,Z
RRC
Ws,Wd
C,N,Z
N,Z
RRNC
RRNC
f,WREG
N,Z
RRNC
Ws,Wd
N,Z
Advance Information
DS70138C-page 155
dsPIC30F3014/4013
TABLE 21-2:
Base
Instr
#
68
Assembly
Mnemonic
SAC
69
SE
70
SETM
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
SAC
Acc,#Slit4,Wdo
Store Accumulator
SAC.R
Acc,#Slit4,Wdo
None
None
SE
Ws,Wnd
Wnd = sign-extended Ws
C,N,Z
SETM
f = 0xFFFF
None
SETM
WREG
WREG = 0xFFFF
None
SETM
Ws
Ws = 0xFFFF
None
SFTAC
Acc,Wn
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
OA,OB,OAB,
SA,SB,SAB
SL
f = Left Shift f
C,N,OV,Z
SL
f,WREG
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
C,N,OV,Z
SL
Wb,Wns,Wnd
N,Z
SL
Wb,#lit5,Wnd
N,Z
SUB
Acc
Subtract Accumulators
OA,OB,OAB,
SA,SB,SAB
SUB
f = f - WREG
C,DC,N,OV,Z
SUB
f,WREG
WREG = f - WREG
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn - lit10
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb - Ws
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb - lit5
C,DC,N,OV,Z
SUBB
f = f - WREG - (C)
C,DC,N,OV,Z
SUBB
f,WREG
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn - lit10 - (C)
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb - Ws - (C)
SUBB
Wb,#lit5,Wd
Wd = Wb - lit5 - (C)
SUBR
f = WREG - f
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG - f
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws - Wb
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 - Wb
C,DC,N,OV,Z
SUBBR
f = WREG - f - (C)
C,DC,N,OV,Z
SUBBR
f,WREG
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws - Wb - (C)
SUBBR
Wb,#lit5,Wd
Wd = lit5 - Wb - (C)
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
None
77
SWAP
SWAP
Wn
Wn = byte swap Wn
None
78
TBLRDH
TBLRDH
Ws,Wd
None
79
TBLRDL
TBLRDL
Ws,Wd
Read Prog<15:0> to Wd
None
80
TBLWTH
TBLWTH
Ws,Wd
None
81
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog<15:0>
None
82
ULNK
ULNK
None
83
XOR
XOR
f = f .XOR. WREG
N,Z
XOR
f,WREG
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
N,Z
84
ZE
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
C,Z,N
DS70138C-page 156
Advance Information
dsPIC30F3014/4013
22.0
DEVELOPMENT SUPPORT
The dsPIC and PICmicro microcontrollers are supported with a full range of hardware and software
development tools:
Integrated Development Environment
- MPLAB IDE Software
Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
In-Circuit Debugger
- MPLAB ICD 2
Device Programmers
- PRO MATE II Universal Device Programmer
- PICSTART Plus Development Programmer
Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
Evaluation Kits
- KEELOQ
- PICDEM MSC
- microID
- CAN
- PowerSmart
- Analog
22.1
22.2
MPASM Assembler
Advance Information
DS70138C-page 157
dsPIC30F3014/4013
22.3
22.4
22.5
22.7
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
22.8
DS70138C-page 158
22.6
Advance Information
dsPIC30F3014/4013
22.9
Advance Information
DS70138C-page 159
dsPIC30F3014/4013
22.14 PICDEM 1 PICmicro
Demonstration Board
DS70138C-page 160
Advance Information
dsPIC30F3014/4013
22.20 PICDEM 18R PIC18C601/801
Demonstration Board
Advance Information
DS70138C-page 161
dsPIC30F3014/4013
NOTES:
DS70138C-page 162
Advance Information
dsPIC30F3014/4013
23.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to dsPIC30F Family Reference Manual
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
Note:
23.1
All peripheral electrical characteristics are specified. For exact peripherals available on specific
devices, please refer the the Family Cross Reference Table.
DC Characteristics
TABLE 23-1:
VDD Range
Temp Range
dsPIC30FXXX-30I
dsPIC30FXXX-20I
dsPIC30FXXX-20E
30
20
4.5-5.5V
-40C to 85C
4.5-5.5V
-40C to 125C
20
3.0-3.6V
-40C to 85C
15
10
3.0-3.6V
-40C to 125C
10
2.5-3.0V
-40C to 85C
10
7.5
Advance Information
DS70138C-page 163
dsPIC30F3014/4013
TABLE 23-2:
Symbol
Min
TJ
Typ
Max
Unit
-40
+125
TA
-40
+85
TJ
-40
+150
TA
-40
+85
TJ
-40
+150
TA
-40
+125
dsPIC30F3014-30I
dsPIC30F4013-30I
dsPIC30F3014-20I
dsPIC30F4013-20I
dsPIC30F3014-20E
dsPIC30F4013-20E
Power Dissipation:
Internal chip power dissipation:
P INT = V DD ( I DD I O H)
PD
PINT + PI/O
PDMAX
(TJ - TA) / JA
TABLE 23-3:
Symbol
JA
JA
JA
Max
Unit
Notes
47
C/W
39.3
C/W
27.8
C/W
Junction to ambient thermal resistance, Theta-ja (JA) numbers are achieved by package simulations.
TABLE 23-4:
DC CHARACTERISTICS
Param
No.
Typ
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
Operating Voltage(2)
DC10
VDD
Supply Voltage
2.5
5.5
Industrial temperature
DC11
VDD
Supply Voltage
3.0
5.5
Extended temperature
Voltage(3)
DC12
VDR
1.5
DC16
VPOR
VSS
DC17
SVDD
0.05
Note 1:
2:
3:
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
This is the limit to which VDD can be lowered without losing RAM data.
DS70138C-page 164
Advance Information
dsPIC30F3014/4013
TABLE 23-5:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
mA
DC20a
TBD
mA
-40C
25C
DC20b
mA
85C
DC20c
mA
125C
DC20d
mA
-40C
DC20e
TBD
mA
25C
DC20f
mA
85C
DC20g
mA
125C
DC23
mA
-40C
DC23a
TBD
mA
25C
DC23b
mA
85C
DC23c
mA
125C
DC23d
mA
-40C
DC23e
TBD
mA
25C
DC23f
mA
85C
DC23g
mA
125C
DC24
mA
-40C
DC24a
TBD
mA
25C
DC24b
mA
85C
DC24c
mA
125C
DC24d
mA
-40C
DC24e
TBD
mA
25C
DC24f
mA
85C
DC24g
mA
125C
DC25
mA
-40C
DC25a
TBD
mA
25C
DC25b
mA
85C
DC25c
mA
125C
DC25d
mA
-40C
DC25e
TBD
mA
25C
DC25f
mA
85C
DC25g
mA
125C
Note 1:
2:
3.3V
1 MIPS EC mode
5V
3.3V
4 MIPS EC mode, 4X PLL
5V
3.3V
10 MIPS EC mode, 4X PLL
5V
3V
8 MIPS EC mode, 8X PLL
5V
Data in Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.
Advance Information
DS70138C-page 165
dsPIC30F3014/4013
TABLE 23-5:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
mA
-40C
DC27a
TBD
mA
25C
DC27b
mA
85C
DC27c
mA
-40C
DC27d
TBD
mA
25C
DC27e
mA
85C
DC27f
mA
125C
DC28
mA
-40C
DC28a
TBD
mA
25C
DC28b
mA
85C
DC28c
mA
-40C
DC28d
TBD
mA
25C
DC28e
mA
85C
DC28f
mA
125C
DC29
mA
-40C
DC29a
TBD
mA
25C
DC29b
mA
85C
DC29c
mA
125C
DC30
mA
-40C
DC30a
TBD
mA
25C
DC30b
mA
85C
DC30c
mA
125C
DC30d
mA
-40C
DC30e
TBD
mA
25C
DC30f
mA
85C
DC30g
mA
125C
DC31
mA
-40C
DC31a
TBD
mA
25C
DC31b
mA
85C
DC31c
mA
125C
DC31d
mA
-40C
DC31e
TBD
mA
25C
DC31f
mA
85C
DC31g
mA
125C
Note 1:
2:
3.3V
20 MIPS EC mode, 8X PLL
5V
3.3V
16 MIPS EC mode, 16X PLL
5V
5V
3.3V
FRC (~ 2 MIPS)
5V
3.3V
LPRC (~ 512 kHz)
5V
Data in Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data
Memory are operational. No peripheral modules are operating.
DS70138C-page 166
Advance Information
dsPIC30F3014/4013
TABLE 23-6:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
mA
-40C
DC40a
TBD
mA
25C
DC40b
mA
85C
DC40c
mA
125C
DC40d
mA
-40C
DC40e
TBD
mA
25C
DC40f
mA
85C
DC40g
mA
125C
DC43
mA
-40C
DC43a
TBD
mA
25C
DC43b
mA
85C
DC43c
mA
125C
DC43d
mA
-40C
DC43e
TBD
mA
25C
DC43f
mA
85C
DC43g
mA
125C
DC44
mA
-40C
DC44a
TBD
mA
25C
DC44b
mA
85C
DC44c
mA
125C
DC44d
mA
-40C
DC44e
TBD
mA
25C
DC44f
mA
85C
DC44g
mA
125C
DC45
mA
-40C
DC45a
TBD
mA
25C
DC45b
mA
85C
DC45c
mA
125C
DC45d
mA
-40C
DC45e
TBD
mA
25C
DC45f
mA
85C
DC45g
mA
125C
Note 1:
2:
3.3V
1 MIPS EC mode
5V
3.3V
4 MIPS EC mode, 4X PLL
5V
3.3V
10 MIPS EC mode, 4X PLL
5V
3.3V
8 MIPS EC mode, 8X PLL
5V
Data in Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with Core off, Clock on and all modules turned off.
Advance Information
DS70138C-page 167
dsPIC30F3014/4013
TABLE 23-6:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
mA
-40C
DC47a
TBD
mA
25C
DC47b
mA
85C
DC47c
mA
-40C
DC47d
TBD
mA
25C
DC47e
mA
85C
DC47f
mA
125C
DC48
mA
-40C
DC48a
TBD
mA
25C
DC48b
mA
85C
DC48c
mA
-40C
DC48d
TBD
mA
25C
DC48e
mA
85C
DC48f
mA
125C
DC49
mA
-40C
DC49a
TBD
mA
25C
DC49b
mA
85C
DC49c
mA
125C
DC50
mA
-40C
DC50a
TBD
mA
25C
DC50b
mA
85C
DC50c
mA
125C
DC50d
mA
-40C
DC50e
TBD
mA
25C
DC50f
mA
85C
DC50g
mA
125C
DC51
mA
-40C
DC51a
TBD
mA
25C
DC51b
mA
85C
DC51c
mA
125C
DC51d
mA
-40C
DC51e
TBD
mA
25C
DC51f
mA
85C
DC51g
mA
125C
Note 1:
2:
3.3V
20 MIPS EC mode, 8X PLL
5V
3.3V
16 MIPS EC mode, 16X PLL
5V
5V
3.3V
FRC (~ 2 MIPS)
5V
3.3V
LPRC (~ 512 kHz)
5V
Data in Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with Core off, Clock on and all modules turned off.
DS70138C-page 168
Advance Information
dsPIC30F3014/4013
TABLE 23-7:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
-40C
DC60a
TBD
25C
DC60b
85C
DC60c
125C
DC60d
-40C
DC60e
TBD
25C
DC60f
85C
DC60g
125C
DC61
-40C
DC61a
TBD
25C
DC61b
85C
DC61c
125C
DC61d
-40C
DC61e
TBD
25C
DC61f
85C
DC61g
125C
DC62
-40C
DC62a
TBD
25C
DC62b
85C
DC62c
125C
DC62d
-40C
DC62e
TBD
25C
DC62f
85C
DC62g
125C
DC63
-40C
DC63a
TBD
25C
DC63b
85C
DC63c
125C
DC63d
-40C
DC63e
TBD
25C
DC63f
85C
DC63g
125C
Note 1:
2:
3:
3.3V
Base Power Down Current(3)
5V
3.3V
Watchdog Timer Current: IWDT(3)
5V
3.3V
Timer 1 w/32 kHz Crystal: ITI32(3)
5V
3.3V
BOR On: IBOR(3)
5V
Data in the Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Advance Information
DS70138C-page 169
dsPIC30F3014/4013
TABLE 23-7:
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
-40C
DC66a
TBD
25C
DC66b
85C
DC66c
125C
DC66d
-40C
DC66e
TBD
25C
DC66f
85C
125C
DC66g
Note 1:
2:
3:
3.3V
Low Voltage Detect: ILVD(3)
5V
Data in the Typical column is at 5V, 25C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
DS70138C-page 170
Advance Information
dsPIC30F3014/4013
TABLE 23-8:
DC CHARACTERISTICS
Param
Symbol
No.
Min
Typ(1)
Max
Units
I/O pins:
with Schmitt Trigger buffer
VSS
0.2 VDD
DI15
MCLR
VSS
0.2 VDD
DI16
VSS
0.2 VDD
VIL
DI10
Characteristic
Conditions
(3)
DI17
VSS
0.3 VDD
DI18
SDA, SCL
TBD
TBD
SM bus disabled
SDA, SCL
TBD
TBD
SM bus enabled
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
VDD
DI25
MCLR
0.8 VDD
VDD
DI26
VDD
DI27
(3)
0.9 VDD
VDD
DI28
SDA, SCL
TBD
TBD
SM bus disabled
DI29
SDA, SCL
TBD
TBD
SM bus enabled
50
250
400
TBD
TBD
TBD
DI19
VIH
DI20
ICNPU
CNXX Pull-up
Current(2)
DI30
DI31
IIL
DI50
I/O ports
0.01
DI51
0.50
DI55
MCLR
0.05
DI56
OSC1
0.05
Note 1:
2:
3:
4:
5:
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Advance Information
DS70138C-page 171
dsPIC30F3014/4013
TABLE 23-9:
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
0.6
Conditions
VOL
DO10
I/O ports
TBD
DO16
OSC2/CLKOUT
0.6
TBD
VDD 0.7
TBD
VOH
DO20
I/O ports
DO26
OSC2/CLKOUT
(RC or EC Osc mode)
VDD 0.7
TBD
COSC2
OSC2/SOSC2 pin
15
pF
DO56
CIO
50
pF
RC or EC Osc mode
DO58
CB
SCL, SDA
400
pF
In I2C mode
Note 1:
2:
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
FIGURE 23-1:
LV10
LVDIF
(LVDIF set by hardware)
DS70138C-page 172
Advance Information
dsPIC30F3014/4013
TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
DC CHARACTERISTICS
Param
No.
LV10
Characteristic(1)
Symbol
VPLVD
Min
Typ
Max
Units
LVDL = 0001(2)
LVDL = 0010(2)
LVDL = 0100
2.50
2.65
LVDL = 0101
2.70
2.86
LVDL = 0110
2.80
2.97
LVDL = 0111
3.00
3.18
LVDL = 1000
3.30
3.50
LVDL = 1001
3.50
3.71
LVDL = 1010
3.60
3.82
LVDL = 1011
3.80
4.03
LVDL = 1100
4.00
4.24
LVDL = 1101
4.20
4.45
LVDL = 1110
4.50
4.77
LVDL = 1111
LVDL = 0011
LV15
Note 1:
2:
VLVDIN
(2)
Conditions
FIGURE 23-2:
BO10
(Device in Brown-out Reset)
BO15
Advance Information
DS70138C-page 173
dsPIC30F3014/4013
TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
VBOR
BO10
Min
Typ(1)
Max
Units
BORV = 00(3)
BORV = 01
2.7
2.86
BORV = 10
4.2
4.46
BORV = 11
4.5
4.78
mV
Characteristic
BOR Voltage(2) on
VDD transition high to
low
Conditions
Not in operating
range
BO15
VBHYS
Note 1:
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
00 values not in usable operating range.
2:
3:
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
ED
Byte Endurance
100K
1M
E/W
D121
VDRW
VMIN
5.5
-40C TA +85C
Using EECON to read/write
VMIN = Minimum operating
voltage
D122
TDEW
ms
D123
TRETD
Characteristic Retention
40
100
Year
D124
IDEW
10
30
mA
Row Erase
-40C TA +85C
(2)
EP
Cell Endurance
10K
100K
E/W
D131
VPR
VMIN
5.5
D132
VEB
4.5
5.5
D133
VPEW
3.0
5.5
D134
TPEW
ms
D135
TRETD
Characteristic Retention
40
100
Year
D136
TEB
ms
D137
IPEW
10
30
mA
Row Erase
D138
IEB
10
30
mA
Bulk Erase
Note 1:
2:
DS70138C-page 174
Advance Information
dsPIC30F3014/4013
23.2
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
AC CHARACTERISTICS
FIGURE 23-3:
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
5 pF for OSC2 output
VSS
FIGURE 23-4:
Q1
Q2
Q3
Q4
Q1
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKOUT
OS40
Advance Information
OS41
DS70138C-page 175
dsPIC30F3014/4013
TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
FOSC
OS10
Characteristic
Min
Typ(1)
Max
Units
DC
4
4
4
40
10
10
7.5
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
Oscillator Frequency(2)
DC
0.4
4
4
4
4
10
31
7.37
512
4
4
10
10
10
7.5
25
33
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
LP
FRC internal
LPRC internal
Conditions
OS20
TOSC
TOSC = 1/FOSC
OS25
TCY
33
DC
ns
OS30
TosL,
TosH
.45 x TOSC
ns
EC
OS31
TosR,
TosF
20
ns
EC
OS40
TckR
10
ns
OS41
TckF
10
ns
Note 1:
2:
3:
4:
Data in Typ column is at 5V, 25C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at min.
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
Max. cycle time limit is DC (no clock) for all devices.
Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin.
CLKOUT is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS70138C-page 176
Advance Information
dsPIC30F3014/4013
TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
OS50
FPLLI
10
MHz
OS51
FSYS
16
120
MHz
OS52
TLOC
20
50
OS53
DCLK
TBD
TBD
Note 1:
2:
FOSC
(MHz)(1)
TCY (sec)(2)
MIPS(3)
w/o PLL
EC
0.200
20.0
0.05
1.0
1.0
4.0
8.0
16.0
XT
Note 1:
2:
3:
MIPS(3)
w PLL x4
MIPS(3)
w PLL x8
MIPS(3)
w PLL x16
10
0.4
2.5
10.0
20.0
25
0.16
25.0
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
Advance Information
DS70138C-page 177
dsPIC30F3014/4013
TABLE 23-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Typ
Max
Units
Conditions
Note 1:
TBD
+25C
VDD = 3.0-3.6 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +85C
-40C TA +125C
VDD = 4.5-5.5 V
VDD = 4.5-5.5 V
Frequency calibrated at 25C and 5V. TUN bits can be used to compensate for temperature drift.
DS70138C-page 178
Advance Information
dsPIC30F3014/4013
TABLE 23-18: AC CHARACTERISTICS: INTERNAL RC JITTER
AC CHARACTERISTICS
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Note 1:
TBD
VDD = 3.0-3.6 V
+25C
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +125C
VDD = 4.5-5.5 V
-40C TA +85C
VDD = 4.5-5.5 V
TBD
+25C
VDD = 3.0-3.6 V
TBD
+25C
VDD = 4.5-5.5 V
TBD
-40C TA +85C
VDD = 3.0-3.6 V
TBD
TBD
-40C TA +85C
-40C TA +125C
VDD = 4.5-5.5 V
VDD = 4.5-5.5 V
Frequency calibrated at 25C and 5V. TUN bits can be used to compensate for temperature drift.
Param
No.
Characteristic
Typ
Max
Units
Conditions
TBD
TBD
-40C to +85C
VDD = 3V
TBD
TBD
-40C to +85C
VDD = 5V
Advance Information
DS70138C-page 179
dsPIC30F3014/4013
FIGURE 23-5:
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
AC CHARACTERISTICS
Param
No.
DO31
Symbol
TIOR
Characteristic(1)(2)(3)
Port output rise time
Min
Typ(4)
Max
Units
Conditions
10
25
ns
DO32
TIOF
10
25
ns
DI35
TINP
20
ns
TRBP
2 TCY
ns
DI40
Note 1:
2:
3:
4:
These parameters are asynchronous events not related to any internal clock edges
Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x TOSC.
These parameters are characterized but not tested in manufacturing.
Data in Typ column is at 5V, 25C unless otherwise stated.
DS70138C-page 180
Advance Information
dsPIC30F3014/4013
FIGURE 23-6:
VDD
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
OSC
Time-out
SY30
Internal
Reset
Watchdog
Timer
Reset
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 23-3 for load conditions.
Advance Information
DS70138C-page 181
dsPIC30F3014/4013
TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
SY10
TmcL
SY11
TPWRT
Min
Typ(2)
Max
Units
Conditions
-40C to +85C
TBD
TBD
TBD
TBD
0
4
16
64
TBD
TBD
TBD
TBD
ms
-40C to +85C
User programmable
-40C to +85C
SY12
TPOR
10
30
SY13
TIOZ
100
ns
SY20
TWDT1
1.8
2.0
2.2
ms
1.9
2.1
2.3
ms
SY25
TBOR
100
SY30
TOST
1024 TOSC
SY35
TFSCM
100
-40C to +85C
TWDT2
Note 1:
2:
3:
FIGURE 23-7:
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
AC CHARACTERISTICS
Param
No.
SY40
Note 1:
2:
Symbol
TBGAP
Characteristic(1)
Min
Typ(2)
Max
Units
20
50
Conditions
Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON<13>Status bit
DS70138C-page 182
Advance Information
dsPIC30F3014/4013
FIGURE 23-8:
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRX
AC CHARACTERISTICS
Param
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
TxCK High Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Asynchronous
10
ns
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Asynchronous
10
ns
TCY + 10
ns
Greater of:
20 ns or
(TCY + 40)/N
OS60
Ft1
TA20
Note:
20
ns
DC
50
kHz
6 TOSC
2 TOSC
N = prescale
value
(1, 8, 64, 256)
Timer1 is a Type A.
Advance Information
DS70138C-page 183
dsPIC30F3014/4013
TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
TB10
TB11
TB15
Symbol
TtxH
TtxL
TtxP
Characteristic
TxCK High Time
Min
Typ
Max
Units
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
Synchronous,
no prescaler
0.5 TCY + 20
ns
Synchronous,
with prescaler
10
ns
TCY + 10
ns
6 TOSC
TB20
Note:
Greater of:
20 ns or
(TCY + 40)/N
2 TOSC
Conditions
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
TABLE 23-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
TC10
TtxH
Synchronous
0.5 TCY + 20
ns
TC11
TtxL
Synchronous
0.5 TCY + 20
ns
TC15
TtxP
TCY + 10
ns
N = prescale
value
(1, 8, 64, 256)
6 TOSC
Synchronous,
with prescaler
TC20
Note:
Greater of:
20 ns or
(TCY + 40)/N
2 TOSC
DS70138C-page 184
Advance Information
dsPIC30F3014/4013
FIGURE 23-9:
IC10
IC11
IC15
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
IC10
TccL
No Prescaler
IC11
TccH
No Prescaler
IC15
TccP
Min
Max
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
With Prescaler
With Prescaler
Note 1:
10
ns
(2 TCY + 40)/N
ns
Conditions
N = prescale
value (1, 4, 16)
FIGURE 23-10:
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Param
Symbol
No.
Characteristic(1)
Typ(2)
Max
Units
Conditions
OC10
TccF
10
25
ns
OC11
TccR
10
25
ns
Note 1:
2:
Advance Information
DS70138C-page 185
dsPIC30F3014/4013
FIGURE 23-11:
OCFA/OCFB
OC15
OCx
AC CHARACTERISTICS
Param
Symbol
No.
OC15
OC20
Note 1:
2:
TFD
TFLT
Characteristic(1)
Min
Typ(2)
Max
Units
25
ns
VDD = 3V
TBD
ns
VDD = 5V
50
ns
VDD = 3V
TBD
ns
VDD = 5V
Conditions
-40C to +85C
-40C to +85C
DS70138C-page 186
Advance Information
dsPIC30F3014/4013
FIGURE 23-12:
CSCK
(SCKE = 0)
CS11
CS10
CS21
CS20
CS20
CS21
CSCK
(SCKE = 1)
COFS
CS55 CS56
CS35
CS51
CSDO
HIGH-Z
70
CS50
LSb
MSb
CS30
CSDI
MSb IN
HIGH-Z
CS31
LSb IN
CS40 CS41
Advance Information
DS70138C-page 187
dsPIC30F3014/4013
TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TcSCKL
CS10
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TCY / 2 + 20
ns
30
ns
TCY / 2 + 20
ns
30
ns
TcSCKH
CS11
CS20
TcSCKF
10
25
ns
CS21
TcSCKR
10
25
ns
CS30
TcSDOF
10
25
ns
Time(4)
CS31
TcSDOR
10
25
ns
CS35
TDV
10
ns
CS36
TDIV
10
20
ns
CS40
TCSDI
20
ns
CS41
THCSDI
20
ns
CS50
TcoFSF
10
25
ns
Note 1
CS51
TcoFSR
10
25
ns
Note 1
CS55
TscoFS
20
ns
CS56
THCOFS
20
ns
Note 1:
2:
3:
4:
DS70138C-page 188
Advance Information
dsPIC30F3014/4013
FIGURE 23-13:
BIT_CLK
(CSCK)
CS61
CS60
CS62
CS21
CS20
CS71
CS70
CS72
SYNC
(COFS)
CS76
CS75
CS80
SDO
(CSDO)
MSb
LSb
LSb
CS76
CS75
MSb IN
SDI
(CSDI)
CS65 CS66
AC CHARACTERISTICS
Param
No.
CS60
CS61
CS62
CS65
CS66
CS70
CS71
CS72
CS75
CS76
CS77
CS78
CS80
Note
Symbol
Characteristic(1)(2)
Min
Typ(3)
Max
Units
Conditions
TBCLKL
TBCLKH
TBCLK
TSACL
BIT_CLK Period
81.4
ns
Bit clock is input
Input Setup Time to
10
ns
10
ns
19.5
s
Note 1
1.3
s
Note 1
TSYNCHI SYNC Data Output High Time
SYNC Data Output Period
20.8
s
Note 1
TSYNC
TRACL
Rise Time, SYNC, SDATA_OUT
10
25
ns
CLOAD = 50 pF, VDD = 5V
TFACL
Fall Time, SYNC, SDATA_OUT
10
25
ns
CLOAD = 50 pF, VDD = 5V
Rise Time, SYNC, SDATA_OUT
TBD
TBD
ns
CLOAD = 50 pF, VDD = 3V
TRACL
Fall Time, SYNC, SDATA_OUT
TBD
TBD
ns
CLOAD = 50 pF, VDD = 3V
TFACL
15
ns
Advance Information
DS70138C-page 189
dsPIC30F3014/4013
FIGURE 23-14:
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
BIT14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb IN
LSb IN
BIT14 - - - -1
SP40 SP41
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
ns
TscL
TCY / 2
SP11
TscH
Time(3)
TCY / 2
ns
SP20
TscF
10
25
ns
SP21
TscR
10
25
ns
SP30
TdoF
10
25
ns
SP10
(4)
SP31
TdoR
10
25
ns
SP35
TscH2doV,
TscL2doV
30
ns
SP40
TdiV2scH,
TdiV2scL
20
ns
SP41
TscH2diL,
TscL2diL
20
ns
Note 1:
2:
3:
4:
DS70138C-page 190
Advance Information
dsPIC30F3014/4013
FIGURE 23-15:
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKX
(CKP = 1)
SP35
SDOX
BIT14 - - - - - -1
MSb
SP40
SDIX
LSb
SP30,SP31
MSb IN
BIT14 - - - -1
LSb IN
SP41
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscL
TCY / 2
ns
SP11
TscH
TCY / 2
ns
10
25
ns
10
25
ns
10
25
ns
10
25
ns
time(4)
SP20
TscF
SP21
TscR
SP30
TdoF
SP31
TdoR
SP35
30
ns
SP36
30
ns
SP40
20
ns
SP41
TscH2diL,
TscL2diL
20
ns
Note 1:
2:
3:
4:
Advance Information
DS70138C-page 191
dsPIC30F3014/4013
FIGURE 23-16:
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
BIT14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb IN
SP40
BIT14 - - - -1
LSb IN
SP41
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscL
30
ns
SP71
TscH
30
ns
25
ns
25
ns
10
25
ns
10
25
ns
Time(3)
SP72
TscF
SP73
TscR
SP30
TdoF
SP31
TdoR
SP35
30
ns
SP40
20
ns
SP41
TscH2diL,
TscL2diL
20
ns
SP50
120
ns
SP51
TssH2doZ
10
50
ns
ns
SP52
Note 1:
2:
3:
DS70138C-page 192
Advance Information
dsPIC30F3014/4013
FIGURE 23-17:
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SP52
MSb
SDOX
BIT14 - - - - - -1
LSb
SP30,SP31
SDIX
MSb IN
BIT14 - - - -1
SP51
LSb IN
SP41
SP40
Advance Information
DS70138C-page 193
dsPIC30F3014/4013
TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscL
30
ns
SP71
TscH
30
ns
SP72
TscF
25
ns
SP73
TscR
25
ns
10
25
ns
10
25
ns
(3)
SP30
TdoF
SP31
TdoR
SP35
30
ns
SP40
20
ns
SP41
20
ns
SP50
120
ns
SP51
10
50
ns
SP52
TscH2ssH
TscL2ssH
1.5 TCY + 40
ns
SP60
50
ns
Note 1:
2:
3:
4:
DS70138C-page 194
Advance Information
dsPIC30F3014/4013
FIGURE 23-18:
SCL
IM31
IM34
IM30
IM33
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 23-3 for load conditions.
FIGURE 23-19:
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM25
IM33
SDA
In
IM40
IM40
IM45
SDA
Out
Note: Refer to Figure 23-3 for load conditions.
Advance Information
DS70138C-page 195
dsPIC30F3014/4013
TABLE 23-35: I2C BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
Min(1)
Max
Units
Conditions
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
1 MHz mode(2)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
THI:SCL
IM11
Characteristic
TCY / 2 (BRG + 1)
300
ns
20 + 0.1 CB
300
ns
1 MHz mode(2)
100
ns
1000
ns
20 + 0.1 CB
300
ns
1 MHz mode(2)
300
ns
250
ns
100
ns
1 MHz mode(2)
TBD
ns
ns
0.9
1 MHz mode(2)
TBD
ns
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
1 MHz mode(2)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
1 MHz mode(2)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
1 MHz mode(2)
TCY / 2 (BRG + 1)
TCY / 2 (BRG + 1)
ns
TCY / 2 (BRG + 1)
ns
1 MHz mode(2)
TCY / 2 (BRG + 1)
ns
3500
ns
1000
ns
1 MHz mode
TF:SCL
IM20
TR:SCL
IM21
IM25
IM26
TSU:STA
IM30
Start Condition
Setup Time
IM31
IM33
IM34
Hold Time
TAA:SCL
IM40
Output Valid
From Clock
(2)
ns
4.7
1.3
1 MHz mode(2)
TBD
400
pF
1 MHz mode
TBF:SDA Bus Free Time
IM45
CB
IM50
Note 1:
2:
(2)
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
BRG is the value of the I2C Baud Rate Generator. Refer to Section 21 Inter-Integrated Circuit (I2C)
in the dsPIC30F Family Reference Manual.
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70138C-page 196
Advance Information
dsPIC30F3014/4013
FIGURE 23-20:
SCL
IS34
IS31
IS30
IS33
SDA
Stop
Condition
Start
Condition
FIGURE 23-21:
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS25
IS33
SDA
In
IS40
IS40
IS45
SDA
Out
Advance Information
DS70138C-page 197
dsPIC30F3014/4013
TABLE 23-36: I2C BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
IS10
IS11
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
Note 1:
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
TAA:SCL
TBF:SDA
CB
Characteristic
Clock Low Time
Min
Max
Units
4.7
1.3
1 MHz mode(1)
0.5
4.0
0.6
1 MHz mode(1)
0.5
300
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
100
ns
1000
ns
20 + 0.1 CB
300
ns
1 MHz mode(1)
300
ns
250
ns
100
ns
1 MHz mode(1)
100
ns
ns
0.9
1 MHz mode(1)
0.3
4.7
0.6
1 MHz mode(1)
0.25
4.0
0.6
1 MHz mode(1)
0.25
4.7
0.6
1 MHz mode(1)
0.6
Stop Condition
4000
ns
Hold Time
600
ns
1 MHz mode(1)
250
3500
ns
1000
ns
1 MHz mode(1)
350
ns
4.7
1.3
1 MHz mode(1)
0.5
400
pF
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Output Valid
From Clock
Bus Free Time
Bus Capacitive
Loading
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
ns
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70138C-page 198
Advance Information
dsPIC30F3014/4013
FIGURE 23-22:
CXTX Pin
(output)
New Value
Old Value
CA10 CA11
CXRX Pin
(input)
CA20
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
10
25
ns
CA11
TioR
10
25
ns
CA20
Tcwf
500
ns
Note 1:
2:
Advance Information
DS70138C-page 199
dsPIC30F3014/4013
TABLE 23-38: 12-BIT A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Greater of
VDD - 0.3
or 2.7
Lesser of
VDD + 0.3
or 5.5
AD02
AVSS
VSS - 0.3
VSS + 0.3
AD05
VREFH
AVDD
AD06
VREFL
AD07
VREF
Absolute Reference
Voltage
AD08
IREF
Current Drain
AD10
Reference Inputs
AVSS + 2.7
AVSS
AVDD - 2.7
AVSS - 0.3
AVDD + 0.3
200
.001
300
3
A
A
A/D operating
A/D off
VREFH
See Note
Analog Input
VREFL
AD11
VIN
AVDD + 0.3
AD12
Leakage Current
AVSS - 0.3
0.001
0.610
AD13
Leakage Current
0.001
0.610
AD15
RSS
Switch Resistance
3.2K
pF
AD16
CSAMPLE
Sample Capacitor
18
AD17
RIN
Recommended Impedance
of Analog Voltage Source
AD20
Nr
Resolution
AD21
INL
Integral Nonlinearity
0.75
TBD
LSb
AD21A INL
Integral Nonlinearity
0.75
TBD
LSb
AD22
DNL
Differential Nonlinearity
0.5
< 1
LSb
AD22A DNL
Differential Nonlinearity
0.5
< 1
LSb
GERR
Gain Error
1.25
TBD
LSb
AD23A GERR
Gain Error
1.25
TBD
LSb
2.5K
DC Accuracy
AD23
Note 1:
12 data bits
bits
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS70138C-page 200
Advance Information
dsPIC30F3014/4013
TABLE 23-38: 12-BIT A/D MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
EOFF
Offset Error
1.25
TBD
LSb
AD24A EOFF
Offset Error
1.25
TBD
LSb
AD25
Monotonicity(1)
AD26
CMRR
Common-Mode Rejection
TBD
dB
AD27
PSRR
TBD
dB
AD28
CTLK
Channel to Channel
Crosstalk
TBD
dB
AD30
THD
dB
AD31
SINAD
TBD
dB
AD32
SFDR
TBD
dB
AD33
FNYQ
50
kHz
AD34
ENOB
TBD
TBD
bits
AD24
Guaranteed
Dynamic Performance
Note 1:
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
Advance Information
DS70138C-page 201
dsPIC30F3014/4013
FIGURE 23-23:
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
TSAMP
AD55
DONE
ADIF
ADRES(0)
DS70138C-page 202
Advance Information
dsPIC30F3014/4013
TABLE 23-39: 12-BIT A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.7V to 5.5V
(unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
-40C TA +125C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
TAD
AD51
tRC
667
ns
1.2
1.5
1.8
Conversion Rate
AD55
tCONV
Conversion Time
14 TAD
ns
AD56
FCNV
Throughput Rate
100
ksps
AD57
TSAMP
Sampling Time
1 TAD
ns
AD60
tPCS
AD61
tPSS
AD62
AD63
VDD = VREF = 5V
VDD = 3-5.5V source
resistance
RS = 0-2.5 k
Timing Parameters
Note 1:
2:
TAD
ns
0.5 TAD
1.5 TAD
ns
tCSS
Conversion Completion to
Sample Start (ASAM = 1)
TBD
ns
tDPU
TBD
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
These parameters are characterized but not tested in manufacturing.
Advance Information
DS70138C-page 203
dsPIC30F3014/4013
NOTES:
DS70138C-page 204
Advance Information
dsPIC30F3014/4013
24.0
PACKAGING INFORMATION
24.1
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
Note:
dsPIC30F4013
-30I/P
0510017
Example
dsPIC
30F4013
-301/PT
0510017
Example
dsPIC
30F4013
-30I/ML
0510017
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
Advance Information
DS70138C-page 205
dsPIC30F3014/4013
40-Lead Plastic Dual In-line 600 mil Body (PDIP)
E1
2
1
n
E
A2
B1
A1
eB
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
40
.100
.175
.150
MAX
MILLIMETERS
NOM
40
2.54
4.06
4.45
3.56
3.81
0.38
15.11
15.24
13.46
13.84
51.94
52.26
3.05
3.30
0.20
0.29
0.76
1.27
0.36
0.46
15.75
16.51
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.160
.190
Molded Package Thickness
A2
.140
.160
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.595
.600
.625
Molded Package Width
E1
.530
.545
.560
Overall Length
D
2.045
2.058
2.065
Tip to Seating Plane
L
.120
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.030
.050
.070
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
.620
.650
.680
DS70138C-page 206
Advance Information
MAX
4.83
4.06
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
15
dsPIC30F3014/4013
44-Lead Plastic Thin Quad Flatpack 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
2
1
B
n
CH x 45
A
c
A1
A2
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
n1
A
A2
A1
L
(F)
E
D
E1
D1
c
B
CH
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.004
.012
.025
5
5
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039
3.5
.472
.472
.394
.394
.006
.015
.035
10
10
MAX
.047
.041
.006
.030
7
.482
.482
.398
.398
.008
.017
.045
15
15
MILLIMETERS*
NOM
44
0.80
11
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.09
0.15
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
15
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
Advance Information
DS70138C-page 207
dsPIC30F3014/4013
44-Lead Plastic Quad Flat No Lead Package 8x8 mm Body (QFN)
DS70138C-page 208
Advance Information
dsPIC30F3014/4013
INDEX
Numerics
12-bit Analog-to-Digital Converter (A/D) Module .............. 125
A
A/D .................................................................................... 125
Aborting a Conversion .............................................. 127
ADCHS Register ....................................................... 125
ADCON1 Register..................................................... 125
ADCON2 Register..................................................... 125
ADCON3 Register..................................................... 125
ADCSSL Register ..................................................... 125
ADPCFG Register..................................................... 125
Configuring Analog Port Pins.............................. 52, 129
Connection Considerations....................................... 129
Conversion Operation ............................................... 126
Effects of a Reset...................................................... 128
Operation During CPU Idle Mode ............................. 128
Operation During CPU Sleep Mode.......................... 128
Output Formats ......................................................... 128
Power-down Modes .................................................. 128
Programming the Sample Trigger............................. 127
Register Map............................................................. 130
Result Buffer ............................................................. 126
Sampling Requirements............................................ 127
Selecting the Conversion Clock ................................ 127
Selecting the Conversion Sequence......................... 126
AC Characteristics ............................................................ 175
Load Conditions ........................................................ 175
AC Temperature and Voltage Specifications .................... 175
AC-Link Mode Operation .................................................. 122
16-bit Mode ............................................................... 122
20-bit Mode ............................................................... 123
Address Generator Units .................................................... 35
Alternate Vector Table ........................................................ 59
Analog-to-Digital Converter. See A/D.
Assembler
MPASM Assembler................................................... 157
Automatic Clock Stretch...................................................... 92
During 10-bit Addressing (STREN = 1)....................... 92
During 7-bit Addressing (STREN = 1)......................... 92
Receive Mode ............................................................. 92
Transmit Mode ............................................................ 92
B
Bandgap Start-up Time
Requirements............................................................ 182
Timing Characteristics .............................................. 182
Barrel Shifter ....................................................................... 21
Bit-Reversed Addressing .................................................... 38
Example ...................................................................... 38
Implementation ........................................................... 38
Modifier Values Table ................................................. 39
Sequence Table (16-Entry)......................................... 39
Block Diagrams
12-bit A/D Functional ................................................ 125
16-bit Timer1 Module .................................................. 63
16-bit Timer2............................................................... 69
16-bit Timer3............................................................... 69
16-bit Timer4............................................................... 74
16-bit Timer5............................................................... 74
32-bit Timer2/3............................................................ 68
32-bit Timer4/5............................................................ 73
CAN Buffers and Protocol Engine............................. 106
C
C Compilers
MPLAB C17.............................................................. 158
MPLAB C18.............................................................. 158
MPLAB C30.............................................................. 158
CAN Module ..................................................................... 105
Baud Rate Setting .................................................... 110
CAN1 Register Map.................................................. 112
Frame Types ............................................................ 105
I/O Timing Characteristics ........................................ 199
I/O Timing Requirements.......................................... 199
Message Reception.................................................. 108
Message Transmission............................................. 109
Modes of Operation .................................................. 107
Overview................................................................... 105
CLKOUT and I/O Timing
Characteristics.......................................................... 180
Requirements ........................................................... 180
Code Examples
Data EEPROM Block Erase ....................................... 48
Data EEPROM Block Write ........................................ 50
Data EEPROM Read.................................................. 47
Data EEPROM Word Erase ....................................... 48
Data EEPROM Word Write ........................................ 49
Erasing a Row of Program Memory ........................... 43
Initiating a Programming Sequence ........................... 44
Loading Write Latches................................................ 44
Code Protection ................................................................ 131
Control Registers ................................................................ 42
NVMADR .................................................................... 42
NVMADRU ................................................................. 42
NVMCON.................................................................... 42
NVMKEY .................................................................... 42
Core Architecture
Overview..................................................................... 13
CPU Architecture Overview ................................................ 13
D
Data Accumulators and Adder/Subtractor .......................... 19
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ............................................................... 20
Write Back .................................................................. 20
Advance Information
DS70138C-page 209
dsPIC30F3014/4013
Data Address Space ........................................................... 28
Alignment .................................................................... 31
Alignment (Figure) ...................................................... 31
Effect of Invalid Memory Accesses (Table)................. 31
MCU and DSP (MAC Class) Instructions Example..... 30
Memory Map ......................................................... 28, 29
Near Data Space ........................................................ 32
Software Stack ............................................................ 32
Spaces ........................................................................ 31
Width........................................................................... 31
Data Converter Interface (DCI) Module ............................ 115
Data EEPROM Memory ...................................................... 47
Erasing ........................................................................ 48
Erasing, Block ............................................................. 48
Erasing, Word ............................................................. 48
Protection Against Spurious Write .............................. 50
Reading....................................................................... 47
Write Verify ................................................................. 50
Writing ......................................................................... 49
Writing, Block .............................................................. 49
Writing, Word .............................................................. 49
DC Characteristics ............................................................ 163
BOR .......................................................................... 174
Brown-out Reset ....................................................... 173
I/O Pin Input Specifications ....................................... 171
I/O Pin Output Specifications .................................... 172
Idle Current (IIDLE) .................................................... 167
Low-Voltage Detect................................................... 172
LVDL ......................................................................... 173
Operating Current (IDD)............................................. 165
Power-Down Current (IPD) ........................................ 169
Program and EEPROM............................................. 174
Temperature and Voltage Specifications .................. 163
DCI Module
Bit Clock Generator................................................... 119
Buffer Alignment with Data Frames .......................... 121
Buffer Control ............................................................ 115
Buffer Data Alignment ............................................... 115
Buffer Length Control................................................ 121
COFS Pin.................................................................. 115
CSCK Pin.................................................................. 115
CSDI Pin ................................................................... 115
CSDO Mode Bit ........................................................ 122
CSDO Pin ................................................................. 115
Data Justification Control Bit ..................................... 120
Device Frequencies for Common Codec CSCK Frequencies (Table) ....................................................... 119
Digital Loopback Mode ............................................. 122
Enable....................................................................... 117
Frame Sync Generator ............................................. 117
Frame Sync Mode Control Bits ................................. 117
I/O Pins ..................................................................... 115
Interrupts ................................................................... 122
Introduction ............................................................... 115
Master Frame Sync Operation .................................. 117
Operation .................................................................. 117
Operation During CPU Idle Mode ............................. 122
Operation During CPU Sleep Mode .......................... 122
Receive Slot Enable Bits........................................... 120
Receive Status Bits ................................................... 121
Register Map............................................................. 124
Sample Clock Edge Control Bit................................. 120
Slave Frame Sync Operation .................................... 118
Slot Enable Bits Operation with Frame Sync ............ 120
Slot Status Bits.......................................................... 122
DS70138C-page 210
E
Electrical Characteristics .................................................. 163
AC............................................................................. 175
DC ............................................................................ 163
Enabling and Setting Up UART
Alternate I/O ............................................................... 99
Setting Up Data, Parity and Stop Bit Selections ......... 99
Enabling the UART ............................................................. 99
Equations
A/D Conversion Clock............................................... 127
Baud Rate................................................................. 101
Bit Clock Frequency.................................................. 119
COFSG Period.......................................................... 117
Serial Clock Rate ........................................................ 94
Time Quantum for Clock Generation ........................ 111
Errata .................................................................................... 7
Evaluation and Programming Tools.................................. 161
Exception Sequence
Trap Sources .............................................................. 58
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 183
External Clock Timing Requirements ............................... 176
Type A Timer ............................................................ 183
Type B Timer ............................................................ 184
Type C Timer ............................................................ 184
External Interrupt Requests ................................................ 60
Advance Information
dsPIC30F3014/4013
F
Fast Context Saving............................................................ 60
Flash Program Memory ...................................................... 41
I
I/O Pin Specifications
Input .......................................................................... 171
Output ....................................................................... 172
I/O Ports .............................................................................. 51
Parallel (PIO) .............................................................. 51
I2C 10-bit Slave Mode Operation ........................................ 91
Reception.................................................................... 92
Transmission............................................................... 91
I2C 7-bit Slave Mode Operation .......................................... 91
Reception.................................................................... 91
Transmission............................................................... 91
I2C Master Mode Operation ................................................ 93
Baud Rate Generator.................................................. 94
Clock Arbitration.......................................................... 94
Multi-Master Communication, Bus Collision
and Bus Arbitration ............................................. 94
Reception.................................................................... 94
Transmission............................................................... 93
I2C Master Mode Support ................................................... 93
I2C Module .......................................................................... 89
Addresses ................................................................... 91
Bus Data Timing Characteristics
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
Bus Data Timing Requirements
Master Mode ..................................................... 196
Slave Mode ....................................................... 198
Bus Start/Stop Bits Timing Characteristics
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
General Call Address Support .................................... 93
Interrupts..................................................................... 93
IPMI Support ............................................................... 93
Operating Function Description .................................. 89
Operation During CPU Sleep and Idle Modes ............ 94
Pin Configuration ........................................................ 89
Programmers Model................................................... 89
Register Map............................................................... 95
Registers..................................................................... 89
Slope Control .............................................................. 93
Software Controlled Clock Stretching (STREN = 1).... 92
Various Modes ............................................................ 89
I2S Mode Operation .......................................................... 123
Data Justification....................................................... 123
Frame and Data Word Length Selection................... 123
Idle Current (IIDLE) ............................................................ 167
In-Circuit Serial Programming (ICSP) ......................... 41, 131
Input Capture (CAPX) Timing Characteristics .................. 185
Input Capture Module ......................................................... 77
Interrupts..................................................................... 78
Register Map............................................................... 79
Input Capture Operation During Sleep and Idle Modes ...... 78
CPU Idle Mode............................................................ 78
CPU Sleep Mode ........................................................ 78
Input Capture Timing Requirements ................................. 185
Input Change Notification Module ....................................... 54
dsPIC30F3014 Register Map (Bits 15-8) .................... 54
dsPIC30F3014 Register Map (Bits 7-0) ...................... 54
dsPIC30F4013 Register Map (Bits 15-8) .................... 54
dsPIC30F4013 Register Map (Bits 7-0) ...................... 54
L
Load Conditions................................................................ 175
Low Voltage Detect (LVD) ................................................ 145
Low-Voltage Detect Characteristics.................................. 172
LVDL Characteristics ........................................................ 173
M
Memory Organization ......................................................... 23
Core Register Map ..................................................... 32
Modes of Operation
Disable...................................................................... 107
Initialization............................................................... 107
Listen All Messages.................................................. 107
Listen Only................................................................ 107
Loopback .................................................................. 107
Normal Operation ..................................................... 107
Modulo Addressing ............................................................. 36
Applicability................................................................. 38
Incrementing Buffer Operation Example .................... 37
Start and End Address ............................................... 37
W Address Register Selection.................................... 37
MPLAB ASM30 Assembler, Linker, Librarian ................... 158
MPLAB ICD 2 In-Circuit Debugger ................................... 159
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator.................................................... 159
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator.................................................... 159
MPLAB Integrated Development Environment
Software ................................................................... 157
MPLINK Object Linker/MPLIB Object Librarian ................ 158
N
NVM
Register Map .............................................................. 45
O
OC/PWM Module Timing Characteristics ......................... 186
Operating Current (IDD) .................................................... 165
Operating Frequency vs Voltage
dsPIC30FXXXX-20 (Extended) ................................ 163
Oscillator
Configurations .......................................................... 134
Fail-Safe Clock Monitor .................................... 136
Fast RC (FRC).................................................. 135
Initial Clock Source Selection ........................... 134
Low Power RC (LPRC)..................................... 135
LP Oscillator Control......................................... 135
Advance Information
DS70138C-page 211
dsPIC30F3014/4013
Phase Locked Loop (PLL) ................................ 135
Start-up Timer (OST) ........................................ 134
Control Registers ...................................................... 137
Operating Modes (Table) .......................................... 132
System Overview ...................................................... 131
Oscillator Selection ........................................................... 131
Oscillator Start-up Timer
Timing Characteristics .............................................. 181
Timing Requirements ................................................ 182
Output Compare Interrupts ................................................. 83
Output Compare Module..................................................... 81
Register Map dsPIC30F3014...................................... 84
Register Map dsPIC30F4013...................................... 84
Timing Characteristics .............................................. 185
Timing Requirements ................................................ 185
Output Compare Operation During CPU Idle Mode............ 83
Output Compare Sleep Mode Operation............................. 83
P
Packaging Information ...................................................... 205
Marking ..................................................................... 205
Peripheral Module Disable (PMD) Registers .................... 147
PICkit 1 Flash Starter Kit................................................... 161
PICSTART Plus Development Programmer ..................... 159
Pinout Descriptions ............................................................. 11
PLL Clock Timing Specifications....................................... 177
POR. See Power-on Reset.
Port Register Map for dsPIC30F3014/4013 ........................ 53
Port Write/Read Example.................................................... 52
Power Saving Modes ........................................................ 145
Idle ............................................................................ 146
Sleep......................................................................... 145
Sleep and Idle ........................................................... 131
Power-Down Current (IPD) ................................................ 169
Power-up Timer
Timing Characteristics .............................................. 181
Timing Requirements ................................................ 182
PRO MATE II Universal Device Programmer ................... 159
Program Address Space ..................................................... 23
Construction ................................................................ 24
Data Access from Program Memory Using
Program Space Visibility ..................................... 26
Data Access From Program Memory Using
Table Instructions................................................ 25
Data Access from, Address Generation...................... 24
Data Space Window into Operation ............................ 27
Data Table Access (LS Word) .................................... 25
Data Table Access (MS Byte) ..................................... 26
Memory Map ............................................................... 23
Table Instructions
TBLRDH.............................................................. 25
TBLRDL .............................................................. 25
TBLWTH ............................................................. 25
TBLWTL.............................................................. 25
Program and EEPROM Characteristics ............................ 174
Program Counter................................................................. 14
Programmable................................................................... 131
Programmers Model........................................................... 14
Diagram ...................................................................... 15
Programming Operations .................................................... 43
Algorithm for Program Flash ....................................... 43
Erasing a Row of Program Memory ............................ 43
Initiating the Programming Sequence ......................... 44
Loading Write Latches ................................................ 44
Protection Against Accidental Writes to OSCCON ........... 136
DS70138C-page 212
R
Reset ........................................................................ 131, 141
BOR, Programmable ................................................ 143
Brown-out Reset (BOR)............................................ 131
Oscillator Start-up Timer (OST) ................................ 131
POR
Operating without FSCM and PWRT................ 143
With Long Crystal Start-up Time ...................... 143
POR (Power-on Reset)............................................. 141
Power-on Reset (POR)............................................. 131
Power-up Timer (PWRT) .......................................... 131
Reset Sequence ................................................................. 57
Reset Sources ............................................................ 57
Reset Sources
Brown-out Reset (BOR).............................................. 57
Illegal Instruction Trap ................................................ 57
Trap Lockout............................................................... 57
Uninitialized W Register Trap ..................................... 57
Watchdog Time-out .................................................... 57
Reset Timing Characteristics............................................ 181
Reset Timing Requirements ............................................. 182
Run-Time Self-Programming (RTSP) ................................. 41
S
Simple Capture Event Mode............................................... 77
Buffer Operation ......................................................... 78
Hall Sensor Mode ....................................................... 78
Prescaler .................................................................... 77
Timer2 and Timer3 Selection Mode............................ 78
Simple OC/PWM Mode Timing Requirements ................. 186
Simple Output Compare Match Mode ................................ 82
Simple PWM Mode ............................................................. 82
Input Pin Fault Protection ........................................... 82
Period ......................................................................... 83
Software Simulator (MPLAB SIM) .................................... 158
Software Simulator (MPLAB SIM30) ................................ 158
Software Stack Pointer, Frame Pointer .............................. 14
CALL Stack Frame ..................................................... 32
SPI Module ......................................................................... 85
Framed SPI Support ................................................... 85
Operating Function Description .................................. 85
Operation During CPU Idle Mode ............................... 87
Operation During CPU Sleep Mode............................ 87
SDOx Disable ............................................................. 85
Slave Select Synchronization ..................................... 87
SPI1 Register Map...................................................... 88
Timing Characteristics
Master Mode (CKE = 0).................................... 190
Master Mode (CKE = 1).................................... 191
Slave Mode (CKE = 1).............................. 192, 193
Timing Requirements
Master Mode (CKE = 0).................................... 190
Master Mode (CKE = 1).................................... 191
Slave Mode (CKE = 0)...................................... 192
Slave Mode (CKE = 1)...................................... 194
Word and Byte Communication .................................. 85
Status Bits, Their Significance and the Initialization
Condition for RCON Register, Case 1 ...................... 144
Status Bits, Their Significance and the Initialization
Condition for RCON Register, Case 2 ...................... 144
Status Register ................................................................... 14
Symbols Used in Opcode Descriptions ............................ 150
System Integration............................................................ 131
Register Map ............................................................ 148
Advance Information
dsPIC30F3014/4013
T
Table Instruction Operation Summary ................................ 41
Temperature and Voltage Specifications
AC ............................................................................. 175
DC............................................................................. 163
Timer1 Module .................................................................... 63
16-bit Asynchronous Counter Mode ........................... 63
16-bit Synchronous Counter Mode ............................. 63
16-bit Timer Mode....................................................... 63
Gate Operation ........................................................... 64
Interrupt....................................................................... 64
Operation During Sleep Mode .................................... 64
Prescaler..................................................................... 64
Real-Time Clock ......................................................... 64
Interrupts............................................................. 65
Oscillator Operation ............................................ 65
Register Map............................................................... 66
Timer2 and Timer3 Selection Mode .................................... 81
Timer2/3 Module ................................................................. 67
16-bit Timer Mode....................................................... 67
32-bit Synchronous Counter Mode ............................. 67
32-bit Timer Mode....................................................... 67
ADC Event Trigger...................................................... 70
Gate Operation ........................................................... 70
Interrupt....................................................................... 70
Operation During Sleep Mode .................................... 70
Register Map............................................................... 71
Timer Prescaler........................................................... 70
Timer4/5 Module ................................................................. 73
Register Map............................................................... 75
Timing Characteristics
A/D Conversion
Low-speed (ASAM = 0, SSRC = 000) .............. 202
Bandgap Start-up Time............................................. 182
CAN Module I/O........................................................ 199
CLKOUT and I/O....................................................... 180
DCI Module
AC-Link Mode ................................................... 189
Multichannel, I2S Modes ................................... 187
External Clock........................................................... 175
I2C Bus Data
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
I2C Bus Start/Stop Bits
Master Mode ..................................................... 195
Slave Mode ....................................................... 197
Input Capture (CAPX) ............................................... 185
OC/PWM Module ...................................................... 186
Oscillator Start-up Timer ........................................... 181
Output Compare Module........................................... 185
Power-up Timer ........................................................ 181
Reset......................................................................... 181
SPI Module
Master Mode (CKE = 0) .................................... 190
Master Mode (CKE = 1) .................................... 191
Slave Mode (CKE = 0) ...................................... 192
Slave Mode (CKE = 1) ...................................... 193
Type A, B and C Timer External Clock ..................... 183
Watchdog Timer........................................................ 181
Timing Diagrams
CAN Bit ..................................................................... 110
Frame Sync, AC-Link Start of Frame........................ 118
Frame Sync, Multi-Channel Mode ............................ 118
I2S Interface Frame Sync.......................................... 118
PWM Output ............................................................... 83
U
UART Module
Address Detect Mode ............................................... 101
Auto Baud Support ................................................... 102
Baud Rate Generator ............................................... 101
Enabling and Setting Up............................................. 99
Framing Error (FERR) .............................................. 101
Idle Status................................................................. 101
Loopback Mode ........................................................ 101
Operation During CPU Sleep and Idle Modes.......... 102
Overview..................................................................... 97
Parity Error (PERR) .................................................. 101
Receive Break .......................................................... 101
Receive Buffer (UxRXB)........................................... 100
Receive Buffer Overrun Error (OERR Bit) ................ 100
Receive Interrupt ...................................................... 100
Receiving Data ......................................................... 100
Receiving in 8-bit or 9-bit Data Mode ....................... 100
Reception Error Handling ......................................... 100
Transmit Break ......................................................... 100
Transmit Buffer (UxTXB) ............................................ 99
Transmit Interrupt ..................................................... 100
Transmitting Data ....................................................... 99
Transmitting in 8-bit Data Mode ................................. 99
Transmitting in 9-bit Data Mode ................................. 99
Advance Information
DS70138C-page 213
dsPIC30F3014/4013
UART1 Register Map ................................................ 103
UART2 Register Map ................................................ 103
UART Operation
Idle Mode .................................................................. 102
Sleep Mode ............................................................... 102
Unit ID Locations............................................................... 131
Universal Asynchronous Receiver Transmitter (UART)
Module ........................................................................ 97
DS70138C-page 214
W
Wake-up from Sleep ......................................................... 131
Wake-up from Sleep and Idle ............................................. 60
Watchdog Timer
Timing Characteristics .............................................. 181
Timing Requirements................................................ 182
Watchdog Timer (WDT)............................................ 131, 145
Enabling and Disabling ............................................. 145
Operation .................................................................. 145
WWW, On-Line Support ....................................................... 7
Advance Information
dsPIC30F3014/4013
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Internet Explorer. Files are also available for FTP
download from our FTP site.
Advance Information
DS70138C-page 215
dsPIC30F3014/4013
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Would you like a reply?
Device: dsPIC30F3014/4013
N
Literature Number: DS70138C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS70138C-page 216
Advance Information
dsPIC30F3014/4013
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
d s P I C 3 0 F 4 0 1 3 AT- 3 0 I / P T- E S
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
Package
P = 40-pin PDIP
PT = 44-pin TQFP (10x10)
ML = 44-pin QFN (8x8)
S = Die (Waffle Pack)
W = Die (Wafers)
Flash
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Temperature
I = Industrial -40C to +85C
E = Extended High Temp -40C to +125C
Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID
Example:
dsPIC30F4013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
Advance Information
DS70138C-page 217
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10/20/04
DS70138C-page 218
Advance Information