TNVXLVDK V3 20-02-2014

I HC QUC GIA TP.
HCM
TRNG I HC BCH KHOA
KHOA KHOA HC V K THUT MY TNH
TH NGHIM
VI X L - VI IU KHIN
BM K thut My tnh
2012
Trng H. Bch Khoa TP.HCM
Bi 1 :
Khoa KH & KTMT
Gii thiu MPLAB IDE v KIT PIC
Ni dung:
a.To project trn MPLAB IDE.Vit chng trnh ASM.
Dch v np chng trnh vo vi iu khin PIC. Chy v g ri chng trnh.
b.c b nh chng trnh.ghi c b nh EEPROM v xut ra LED.
1.1 Phn cng th nghim ICD2 v PICDEM 2 PLUS.
B h tr lp trnh dng vi my tnh ICD2 (In-Circuit Debugger).
Cng ni tip
ICD2
USB
Ni vi card
PICDEM
Ni vi
my tnh
S kt ni ICD2
Kit th nghim PICDEM 2 Plus c cc c im nh hnh sau :
1.
2.
3.
4.
5.
6.
7.
8.
9.
cm DIP 18, 28 v 40 chn (c th cm 3 linh kin nhng ch dng 1 mi ln).

n p +5V dng cho ngun 9V, 100 mA AC/DC hay pin 9V.
u cm DB-9 theo chun giao tip RS-232.
u cm qua b lp trnh In-Circuit Debugger (ICD).
Bin tr 5K dng cho tn hiu nhp tng t.
Ba nt nhn dng to tn hiu kch t bn ngoi v reset.
LED ngun.
Bn LED ch th cho PORTB.
Jumper J6 ngt LED ch th RB0 (khi nhp tn hiu t nt nhn RB0).
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Thc hnh Vi x l Vi iu khin
Khoa KH & KTMT
10. B dao ng (OSC) 4 MHz.

11. Ni lp thm thch anh dao ng nu cn.
12. Thch anh dao ng 32.768 kHz to xung clock cho Timer1.
13. Jumper J7 ngt dao ng RC c sn (khong 2 MHz).
14. EEPROM ni tip 32K x 8 bit.
15. Mn hnh LCD.
16. Kn Piezo.
17. Vng lp thm linh kin.
18. Cm bin nhit TC74.
1.2 Mi trng pht trin MPLAB
Bc 1. Chy phn mm MPLAB:
Start_|All Programs_|Microchip_|MPLAB IDE v8.00_|MPLAB IDE.
Bc 2. Chn Menu :
Project_|Project Wirazd
Chn Next ca s Welcome
Bc 3. Chn s hiu PIC cn s dng (PIC18F4520) ri bm Next:
Bc 4. Chn tool Microchip MPASM Toolsuite ti Active Toolsuite.
B mn K Thut My Tnh
Khoa KH & KTMT
Chn MPASM Assembler (mpasmwin.exe) ti Tollsuite Contents.
Click Next qua ca s k.

Bc 5. Nhn Browse chn th mc v nh tn project.
Chn th vin thng qua file .INC v .LKR thm vo project

B mn K Thut My Tnh
Khoa KH & KTMT
C:\Program Files\Microchip\MPASM Suite\LKR\18f4520.lkr

C:\Program Files\Microchip\MPASM Suite\P18F4520.INC
Click Next s thy nh sau :
Click Finish. Ta s c mt project nh hnh sau:
B mn K Thut My Tnh
Khoa KH & KTMT
Bc 6. Thm file vo d n theo cc bc sau :

Mt project n gin nht phi gm c 2 thnh phn Source files v Hearder Files.
Th mc Source files cha file text *.asm hoc file *.c cha code lp trnh. Th mc
Hearder Files cha file *.h hoc *.INC: file c sn ca microchip.
Nu bn qun khng thm cc file cn c vo th lm theo hng dn sau :
ADD header file: ( Copy header file vo th mc cha project tin cho vic s
dng sau ny).
ca s la chn
Chn header file ph hp vi PIC

mnh chn. Open.
ADD source file: Click chn New
trn toolbar:
Ca s hin ln nh sau: T Menu
bar chn File_|Save lu.
Thc hin Save, t tn vi

ui .asm vo th mc cha d
n.
Nhp phi vo Source Files
chn Add file >>> chn file
chng ta va to xong.
Chng ta hon tt vic
thm file vo cc th mc
Source files v Header files.
B mn K Thut My Tnh
Khoa KH & KTMT
Cng vic tip theo l vit code (trong ca s text editor ca source file).
i vi project ln dng nhiu source file v header file, ta lm li qu trnh thm file
vo d n nhiu ln.
1.3 Np file hex vo vi iu khin PIC
Sau khi to c mt project, ta tin hnh build n to ra *.hex. C th m t cng
vic nh sau:
V d, ta c mt chng trnh cho PIC nh sau:
list
#include
code
goto
p=18f4520
p18f4520.inc
0
start
;vung dinh nghia du lieu

udata
;vung dinh nghia cac chuong trinh con
PRG
code
start
call
init
;chuong trinh chinh
main
btfsc
PORTA,RA4 ;cho nhan nut RA4
bra
main
bsf
LATB,RB0
;Bat LED RB0
swoff
btfss
PORTA,RA4 ;cho nhan nut RA4
bra
swoff
bcf
LATB,RB0
;tat LED RB0
bra
main
;Lap lai cong viec
;chuong trinh khoi dong ban dau
init
bcf
TRISB,RB0
;khoi dong RB0 la cong xuat
bsf
TRISA,RA4
;khoi dong RA4 la cong nhap
return
end
By gi chng ta lu chng trnh va vit thnh BaiTN1.asm vo mt th mc
to project pha trn. compile chng trnh ta vo menu Project_|Build All nh hnh
bn di.
B mn K Thut My Tnh
Khoa KH & KTMT
Nu vic build tht bi, nhng vic ny th khng mong mun, ta c thy kt qu nh
hnh sau:
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Khoa KH & KTMT
Nu thnh cng, ta s thy hnh sau:
Nu vic build thnh cng, chng trnh s dch BaiTN1.asm thnh BaiTN1.hex
trong cng th mc chng trnh BaiTN1.asm. Sau khi c c file hex, cng vic
tip theo l lm th no np c file Hex xung board. u tin, chn mch np bng
cch vo menu Programmer_|Select Programmer_|Mplab ICD2 nh hnh sau :
Sau khi chn Mplab ICD2 xong th ta s thy giao din nh sau:
B mn K Thut My Tnh
Khoa KH & KTMT
Mt thao tc cn lm gip ta c th dch chng trnh, np v chy t ng l vo

menu Programmer_|Settings_|Program chn mc Automatically nh hnh sau :
By gi ta c th dch, np v chy d n vi thao tc menu Project_|Build All (hoc

nhn Ctrl-F10).
Nu thnh cng th chng trnh s c dch, np ra card PICDEM v chy ngay.
B mn K Thut My Tnh
Khoa KH & KTMT
Nu tht bi, xem thng tin bo li trong ca s Output khc phc v lm li t

bc Build All.
Trng hp thnh cng m chng trnh chy khng ng, ta phi s dng cng c
Debugger tm li theo mt trong hai cch sau.
1.4 Debug dng MpLab SIM
Bc 1. Chn Debugger bng menu
Debugger_|Select Debugger_|Mplab SIM
Bc 2. Tham kho menu Debugger. Xut hin nhiu chc nng h tr debug.
T y ta c th m phng c chng trnh ca mnh mt cch d dng.

Cc chc nng thng dng :
Run (F9): chy chng trnh, chng trnh s chy lin tc n khi no c
breakpoint th dng.
Breakpoints (F2): to ra breakpoint ti v tr hin ti ca con tr (cng c th
"double click" vo hng code mnh mong mun t Breakpoint).
Step Into (F7): chy tng bc, vo trong chng trnh con (nu gp).
Step Over (F8): chy tng bc, gi chng trnh con cng xem nh 1 bc.
Reset: tr v u chng trnh.
B mn K Thut My Tnh
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Khoa KH & KTMT
Bc 3. Khi debug th ta cng cn phi bit gi tr ca cc thanh ghi cng nh b nh

ca chip nh th no, xem c cc gi tr ny th chng ta qua menu View.
xem c gi tr ca cc thanh ghi trong PIC ta chn menu View_|File registers
s xut hin ca s nh hnh sau:
xem c gi tr ca cc thanh ghi SFR th ta chn View_|Special Function

Registers s xut hin ca s nh hnh sau:
Hay xem mt v thanh ghi m ta quan tm th c th dng Watch xem bng

cch vo menu View_|Watch th hnh sau s xut hin:
Mun xem thanh ghi no, ta ch vic chn thanh ghi tng ng trong combobox bn
trn, sau nhn Add SFR.
B mn K Thut My Tnh
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Khoa KH & KTMT
1.5 Debug onchip dng Mplab ICD2.

Cng ging nh debug trn Mplab SIM, Mplab ICD2 cng c nhng tnh nng
tng t, nhng khi s dng Mplab ICD2 th cn phi c mch debug, v cc hin tng
xy ra ging nh khi chy thc t.
1.6 Bi tp.
a) c 1 byte b nh chng trnh ti a ch 0x00 vit vo b nh EEPROM ti a
ch 0x10 ri c EEPROM xut ra cng RB3 n RB0. Ch na byte cao xut ra trc,
na byte thp xut ra sau.
B mn K Thut My Tnh
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Bi 2 :
Khoa KH & KTMT
Kho st cng xut nhp song song
Ni dung:
Kho st hot ng ca nt nhn, LED.
Kho st cc thanh iu khin cng xut nhp song song.
Tnh ton thi gian thc thi lnh, vit chng trnh con lm nhim v delay.
Vit chng trnh kim tra nt nhn v hin th kt qu kim tra ra LED.
Yu cu:
a.Vit chng trnh xut d liu ra 4 led n m t 0000 -> 1111 -> 0000.
Thi gian gia cc ln m ln 1 n v l 1s.
b. Vit chng trnh xut d liu ra 4 led m theo h m O,D
2.1 Kin thc lin quan

2.1.1 Cc thanh ghi iu khin cng xut nhp
Mi Port c ba thanh ghi iu khin hot ng chnh:
Cc bit trong thanh ghi TRIS: thit lp chn tng ng l ng vo (logic 1) hoc
ng ra (logic 0).
Cc bit trong thanh ghi PORT: c mc logic t chn tng ng.
Cc bit trong thanh ghi LAT: ghi mc logic ra chn tng ng.
2.1.2 Kt ni mch
V tr LED hin th v nt nhn trn board nh hnh di y:
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Khoa KH & KTMT
LED hin th c kt ni nh sau:
Mun cc LED sng, cc chn RBi tng ng phi ln mc 1. Ring LED D2 cn

phi ni jumper J6 li mi sng c khi RB0=1.
L do c jumper JP6 l do chn RB0 cn c dng lm ng nhp nt nhn RB0.
Nh vy, lc no mun dng chn RB0 l ng xut LED th ng jumper JP6 li.
Ngc li, h JP6 s dng RB0 lm ng nhp nt nhn.
Cc nt nhn c kt ni nh sau:
Nt nhn RA4, RB0 khi c nhn s lm cho chn tng ng mc logic 0.

Cn thit lp cc chn RA4 v RB0 l ng vo.
B dao ng chnh l b dao ng ngoi tn s 4 MHz c kt ni nh sau:
Trn kit th nghim, thch anh Y2 c s dng cho tt c cc bi th nghim.
2.2 Cc bc hin thc yu cu 1

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Led_don,
to file led_don.asm v chn chip 18f4520. Ta c hnh sau:
B mn K Thut My Tnh
14
Khoa KH & KTMT
Bc 2. Include file p18f4520.inc vo file led_don.asm.

Bc 3. Khi to PORTB l cng xut cc bit RB0-RB3.
init
clrf
PORTB
;
bcf
TRISB,RB0
; RB0 xut
bcf
TRISB,RB1
; RB1 xut
bcf
TRISB,RB2
; RB2 xut
bcf
TRISB,RB3
; RB3 xut
return
Bc 4. To hm delay1ms c s dng bin delay (nh ngha trong udata) nh sau :
udata
delay
res
1
; nh ngha bin delay
...
delay1ms
; Gn ng 1 ms vi xung clock 4 MHz
clrf
delay
; xa bin delay (vng lp 256 ln)
dl_1
nop
decfsz
delay
bra
dl_1
return
Bc 5. T y ta c th to ra c hm delay1s bng cch gi hm delay1ms 1000 ln
delay1s
.4
movlw
movwf
delay_1sa
dl_2
movlw
.250
; bt u vng lp ngoi
B mn K Thut My Tnh
15
dl_3
movwf
call
decfsz
bra
decfsz
bra
return
delay_1sb
delay1ms
delay_1sb
dl_3
delay_1sa
dl_2
Khoa KH & KTMT
; bt u vng lp trong
; kt thc vng lp trong (250 lan)
; kt thc vng lp ngoi (4 ln)
Bc 6. Vit chng trnh cho hm begin thc hin cc yu cu ca bi :

begin
incf
LATB
delay1s
call
begin
; lp li sau mi giy
bra
2.3 Chng trnh mu yu cu 1

list
p=18f4520
#include p18f4520.inc
code
0
goto
start
; Vung du lieu
udata
delay
1
res
1
delay_1sa res
1
delay_1sb res
PRG
code
start
call
init
; chuong trinh chinh
begin
incf
LATB
call
delay1s
bra
begin
; Ham khoi dong ban dau
init
clrf
PORTB
bcf
TRISB,RB0
bcf
TRISB,RB1
bcf
TRISB,RB2
bcf
TRISB,RB3
return
B mn K Thut My Tnh
; lap lai sau moi giay

;
; cau hinh RB0 xuat
; cau hinh RB1 xuat
; cau hinh RB2 xuat
; cau hinh RB3 xuat
16
Khoa KH & KTMT
; Ham lam tre 1ms voi tan so dao dong 4MHz

delay1ms
; Gan dung voi xung clock 4 MHz
clrf
delay
; xoa bien delay (vong lap 256 lan)
dl_1
nop
decfsz
delay
bra
dl_1
return
; Ham lam tre 1s = 1000 x 1ms
delay1s
movlw
.4
movwf
delay_1sa
dl_2
movlw
.250
; bat dau vong lap ngoai (4 lan)
movwf
delay_1sb
dl_3
call
delay1ms
; bat dau vong lap trong (250 lan)
decfsz
delay_1sb
bra
dl_3
; ket thuc vong lap trong
decfsz
delay_1sa
bra
dl_2
; ket thuc vong lap ngoai
return
end
Sau khi c chng trnh mu ta thc hin vic compile chng trnh v np xung
mch chy chng trnh nh hng dn chng 1.

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Nut_nhan
v chn chip 18f4520. Ta c hnh sau:
B mn K Thut My Tnh
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Khoa KH & KTMT
Bc 2. Include file p18f4520.inc vo file nut_nhan.asm.

Bc 3. Khi to PORTB bit RB0 l cng xut (jumper JP6 ng) v PORTA bit RA4
l cng nhp.
init
clrf
PORTB
bcf
TRISB,RB0
; RB0 xut
bsf
TRISA,RA4
; RA4 nhp
return
Bc 4. Vit chng trnh cho hm main thc hin yu cu ca bi
main
PORTA,RA4
; ch n khi RA4 c nhn
btfsc
bra
Main
bsf
LATB,RB0
; bt sng LED RB0
swoff
btfss
PORTA,RA4
; ch n khi RA4 c nh
bra
Swoff
bcf
LATB,RB0
; tt LED RB0
bra
Main
; lp li qu trnh
2.5 Chng trnh mu yu cu 2

list
p=18f4520
#include p18f4520.inc
code
0
goto
start
; Vung du lieu
udata
; Chuong trinh nay khong su dung bien
; Vung bat dau code
PRG
code
start
call
init
; chuong trinh chinh
main
btfsc
PORTA,RA4
bra
main
bcf
LATB,RB0
swoff
btfss
PORTA,RA4
bra
swoff
bcf
PORTB,RB0
goto
main
init
clrf
PORTB
bcf
TRISB,RB0
B mn K Thut My Tnh
; c RA4 den khi RA4=0

0=====1==duoc nhan
; bat sang LED RB0
; cho den khi RA4 duoc nha
; tat LED RB0
; lap lai qua trinh
; RB0 xuat
18
Khoa KH & KTMT
bsf
TRISA,RA4
; RA4 nhap
return
end
2.6 Bi tp
a) Vit chng trnh khi nhn RA4 th cc led s sng m ln, mi ln nhn m
ln 1 n v theo h m H v h m O.
b) Vit chng trnh khi nhn RA4 th cc led s sng m ln, mi ln nhn m
ln 1 n v theo h m D.
c) Cho s mch loa
RC2
J9
R11
++
-
22
BZI
- Value
BUZZER- AST124MLTRQ
Vit chng trnh pht xung 1KHz ra loa khi nhn RA4 v ngng pht xung khi
nhn RA4 ln 2.
B mn K Thut My Tnh

19
Khoa KH & KTMT
Bi 3 : Kho st c ch c trng thi Timer, xut d liu

ra LCD k t
Ni dung:
Kho st cc ch hot ng ca cc b nh thi.
Kho st cc thanh ghi iu khin b nh thi.
Bit c trng thi ca b nh thi trong chng trnh (phng php polling).
Xut thi gian thc ca b nh thi ra LCD
Yu cu:
1. S dng b timer 1 c sau 1s m ln 1 n v ri xut gi tr ra LED.
2. Vit chng trnh thc hin ng h thi gian thc.
3. Vit chng trnh hin th ng h thi gian thc ln LCD.

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l
timer_polling v chn chip 18f4520. Ta c hnh sau:
Bc 2.
Include file p18f4520.inc vo file timer _polling.asm
B mn K Thut My Tnh

20
Bc 3.
Khoa KH & KTMT
Khi to Port B
init
movlw
0x0e
; PortB Digital output
movwf
ADCON1
clrf
PORTB
; ton b PORTB l cng xut
clrf
TRISB
return
Bc 4. Khi to ngt timer0 pht ra ngt 100ms (vi xung clock 4 MHz, chn prescaler
2:1, s m 50000).
init_timer0
.10
movlw
movwf
tmr0_var1
bcf
INTCON,TMR0IF
clrf
T0CON
movlw
0x3c
movwf
TMR0H
movlw
0xaf
movwf
TMR0L
bsf
T0CON,TMR0ON
return
; xoa co ngat timer0

; prescaler 2:1
; nap so dem 50000 cho timer0
; cho phep timer0 dem
Bc 5. Vit chng trnh con chy trong timer, sau 1s tng gi tr hin th ra ngoi led
n.
V c 100ms th c ngt mt ln, do sau 1s ta tng ln mt gi tr th cn 10 ln
ngt nh vy, nn ban u ta phi khi to cho bin delay = 10. V y l hm chnh thc
hin chc nng ca bi tp 1.
timer0_ routine
bcf
decfsz
bra
incf
movlw
movwf
timer0_isr_1
bcf
movlw
movwf
movlw
movwf
bsf
return
INTCON,TMR0IF
tmr0_var1
timer0_isr_1
PORTB
.10
tmr0_ var1
T0CON,TMR0ON
0x3c
TMR0H
0xaf
TMR0L
T0CON,TMR0ON
B mn K Thut My Tnh
; nap lai so dem 50000 cho timer0
; cho phep timer0 dem lai

21
Khoa KH & KTMT
B mn K Thut My Tnh

22
[Trng H. Bch Khoa TP.HCM
Khoa KH & KTMT
3.2 Chng trnh mu

#include
code
goto
; Vung du lieu
udata
tmr0_var1 res
; Vung bat dau code
PRG
code main
rcall
rcall
tmr0_loop
btfss
bra
rcall
bra
init
p18f4520.inc
0
main
init
init_timer0
INTCON,TMR0IF
tmr0_loop
timer0_routine
tmr0_loop

movlw
0x0e
movwf
ADCON1
clrf
PORTB
clrf
TRISB
return
init_timer0
; Kiem tra trang thai co IF

; Nap lai bo dem

movlw
movwf
bcf
clrf
movlw
movwf
movlw
movwf
bsf
return
.10
tmr0_var1
INTCON,TMR0IF
T0CON
0x3c
TMR0H
0xaf
TMR0L
INTCON,TMR0IF
bcf
decfsz
bra
INTCON,TMR0IF
tmr0_var1,1
timer0_isr_1
incf
movlw
movwf
LATB
.10
tmr0_var1
bcf
movlw
T0CON,TMR0ON
0x3c
timer0_routine
timer0_isr_1
B mn K Thut My Tnh
Thc hnh Vi x l- Vi iu khin

23
movwf
movlw
movwf
bsf
return
Khoa KH & KTMT
TMR0H
0xaf
TMR0L
T0CON,TMR0ON
3.3 LCD k t 2x16

3.3.1 Hnh dng v ngha cc chn:
Tn chn
GND
VCC
VEE
RS
R/W
D0
D1
D2
D3
D4
D5
D6
D7
A
K
Mc logic
0
1
0
1
M t
t (0V)
Ngun (+5V)
Chnh contrast (0 VCC)
D0-D7 l gi tr lnh
D0-D7 l gi tr d liu
Ghi gi tr vo LCD
c gi tr ra t LCD
0
1
T 1 xung 0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
-
Cm truy xut LCD

LCD hot ng trao i d liu
D liu/Lnh a vo LCD
Bit 0/LSB
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7/MSB
Chn Anode ca n nn
Chn Cathode ca n nn
3.2.2 T chc vng nh ca LCD

B mn K Thut My Tnh

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Khoa KH & KTMT
Display Data Ram (DDRAM): lu tr m k t hin th ra mn hnh. M ny ging

vi m ASCII. C tt c 80 nh DDRAM. Vng hin th tng ng vi ca s gm 16
nh hng u tin v 16 nh hng th hai. Chng ta c th to hiu ng dch ch
bng cch s dng lnh dch (m t sau), khi ca s hin th s dch em li hiu ng
dch ch.
Character Generator Ram (CGRAM): lu tr tm mu k t do ngi dng nh

ngha. Tm mu k t ny tng ng vi cc m k t D7-D0 = 0000*D2D1D0 (* mang
gi tr ty nh 0 hay 1).
Character Generator Rom (CGROM): lu tr cng cc mu k t tng ng vi m

ASCII. Di y l bng nh x gia m k t v mu k t.
Chng ta mun hin th ch CE gia hng u tin, gi s ca s hin th ang
bt u t v tr u tin (hng th nht hin th d liu ca nh t 0x00 n 0x0f,
hng th hai hin th d liu ca nh t 0x40 n 0x4f, y l v tr home). Gi tr
ca nh
0x07 l 0x43 (k t C), ca nh 0x08 l 0x45 (k t E).
Chng ta mun hin th ch gi hng th hai, gi s c s hin th ang v
tr home. Trong bng mu k t chng ta thy khng c mu . Lc ny chng ta
phi nh ngha mu 5x8 im, gm c 8 byte, sau lu vo v tr ca mu k t
CGRAM th nht. Lc ny gi tr ca nh 0x47 l 0x00 hoc 0x08 (v tr ca mu
k t CGRAM th nht ).
B mn K Thut My Tnh

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Khoa KH & KTMT
B mn K Thut My Tnh

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Khoa KH & KTMT
3.3.3 Cc lnh giao tip vi LCD

Lnh
Clear display
Return home
Entry mode set
Display on/off
Control
Cursor/Display
Shift
Function set
Set CGRAM
Address
Set DDRAM
Address
Read BUSY flag
(BF)
Write to
DDRAM or
CGRAM
Read from
DDRAM or
CGRAM
RS
RW
D7
D6
D5
D4
D3
D2
D1
D0
Thi gian
thc thi
1.52ms
1.52ms
37s
S/
C
R/
L
37s
DL
37s
DDRAM address
37s
BF
DDRAM address
0s
D7
D6
D5
D4
D3
D2
D1
D0
43s
D7
D6
D5
D4
D3
D2
D1
D0
43s
I/D SH
CGRAM address
37s
37s
Cc bit trn bng tm tt cc lnh c ngha nh sau:

I/D
SH
S/C
R/L
DL
N
F
BF
1
1
1
1
1
1
1
1
Increment
Entire shift on
Display shift
Shift to the Right
8 bits
2 Lines
5x10 dots Font
Internally operating
0
0
0
0
0
0
0
0
Decrement
Entire shift off
Cursor move
Shift to the Left
4 bits
1 Lines
5x8 dots Font
Can accept instruction
Trn kit th nghim LCD k t 2x16 c kt ni vo Port D ch 4 bit. ch

4 bit, c hay ghi mt byte phi tin hnh ci d liu hai ln, ln u l 4 bit cao, ln
th hai l 4 bit thp.
B mn K Thut My Tnh
27
Khoa KH & KTMT
3.3.4 Khi to LCD

S kt ni LCD:
VCC
R20
2.2K
RD7
Q2
MMBT2222A
LCD1
RD4
RD5
RD6
RD0
RD1
RD2
RD3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vss
Vdd
Vee
RS
R/W
E
D0
D1
D2
D3
D4
D5
D6
D7
A
K
LCD k t 2x16
Trc khi xut k t ra mn hnh LCD, LCD controller phi c khi to khi mi
c cp ngun. Trnh t khi to nh lc sau. Trn lc , lnh Display clear c
gi tr 0x01 c gi hai ln, ln u l 4 bit cao c gi tr 0x0, ln th hai l bn bit thp
c gi tr 0x01. Lnh Function set gi hai ln gi tr 0x2.
B mn K Thut My Tnh
28
Khoa KH & KTMT
Bt ngun
(chn PD7 out ra mc logic 1)
Ch ti thiu 30ms
(i VDD > 4.5V)
Ch ti thiu 39s
Gi lnh
Display clear
Gi lnh
Function set
RS RW D7
D6
D5
D4
RS RW D7
D6
D5
D4
*
Gi lnh
Entry mode set
Ch ti thiu 39s
RS RW D7
Gi lnh
Display on/off control
RS RW D7
D6
D5
D4
D6
D5
D4
I/D
SH
Kt thc khi to

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l LCD, to
file lcd.asm v chn chip 18f4520. Ta c hnh sau:
B mn K Thut My Tnh
29
Khoa KH & KTMT
Bc 2. Include file p18f4520.inc vo file lcd.asm

Bc 3. Da vo s nguyn l kt ni vi iu khin vi LCD k t ta define li d
dng s dng hn.
LATD, RD0
; LCD data bits
#define
LCD_D4
LATD,
RD1
#define
LCD_D5
LATD, RD2
#define
LCD_D6
LATD, RD3
#define
LCD_D7
; LCD data bits
#define
LCD_D4_DIR TRISD, RD0
#define
#define
#define
#define
#define
#define
LCD_E
LCD_RW
LCD_RS
LATD, RD6
LATD, RD5
LATD, RD4
#define
#define
#define
#define
#define
#define
LCD_E_DIR
LCD_RW_DIR
LCD_RS_DIR
LCD_D
LCD_ON
LCD_ON_DIR
TRISD, RD6
TRISD, RD5
TRISD, RD4
PORTD
LATD,RD7
TRISD, RD7
; LCD E clock
; LCD read/write line
; LCD register select line
Bc 4. Vit hm xut d liu 4 bit trong bin data_4bit ra cho LCD k t :
B mn K Thut My Tnh
30
Khoa KH & KTMT
Write4bit_to_portD
tt1
tt2
tt3
tt4
set_bit_0
set_bit_1
set_bit_2
set_bit_3
btfsc
bra
bcf
btfsc
bra
bcf
btfsc
bra
bcf
btfsc
bra
bcf
return
bsf
bra
bsf
bra
bsf
bra
bsf
bra
data_4bit,0
set_bit_0
LCD_D4
data_4bit,1
set_bit_1
LCD_D5
data_4bit,2
set_bit_2
LCD_D6
data_4bit,3
set_bit_3
LCD_D7
LCD_D4
tt1
LCD_D5
tt2
LCD_D6
tt3
LCD_D7
tt4
Bc 5. Tip tc ta vit hm truyn lnh (command) cho lcd k t.

lcd_write_cmd
;----- trong bin command

rcall
lcd_wait_busy ; LCD san sang
bcf
LCD_RS
; Cho phep lenh
movff
command,data_4bit
swapf
data_4bit
rcall
lcd_write_4bits
; Xuat 4bit lenh cao
movff
command,data_4bit
rcall
lcd_write_4bits
; Xuat 4bit lenh thap
return
lcd_wait_busy ;----- Cho LCD san sang

bsf
LCD_D7_DIR
bsf
LCD_D6_DIR
bsf
LCD_D5_DIR
bsf
LCD_D4_DIR
bcf
LCD_RS
bsf
LCD_RW
rcall
delay1us
bsf
LCD_E
rcall
delay1us
wait1
btfsc
LCD_D,3
bra
wait1
bcf
LCD_E
B mn K Thut My Tnh
31
; RD3 input
; RD2 input
; RD1 input
; RD0 input
; Cho phep lenh
; Cho phep doc
; Cho xong
; Cho phep LCD hoat dong
; Giu cham phan cung
; Kiem tra LCD xong chua ?
; Xong, cam LCD

bcf
bcf
bcf
bcf
return
Khoa KH & KTMT

LCD_D7_DIR
LCD_D6_DIR
LCD_D5_DIR
LCD_D4_DIR
; RD3 output
; RD2 output
; RD1 output
; RD0 output
;----- Lay 4bit thap trong bin data_4bit

bcf
LCD_RW
; Cho phep viet
bsf
LCD_E
rcall
write_4bit_to_portD ; Xuat 4bit data
rcall
delay10us
; Giu cham 10 usec
bcf
LCD_E
; CAM LCD hoat dong
rcall
delay10us
; Giu cham 10 usec
return
lcd_write_4bits
Bc 6 Sau vit thm hm truyn d liu hin th ra LCD k t.

Chng trnh con lcd_print_char truyn d liu trong bin char hin th ln mn hnh
LCD. Nh trn ta cp, trong ng dng ny ta s dng LCD ch 4 bt, nn data y
c truyn theo th t l 4 bit cao truyn trc sau 4 bt thp c truyn sau.
;-------trong bin char
movlw
.0
cpfseq
row
bra
print1
movlw
.16
; current_row = 0
cpfseq
col
bra
print1
movlw
.1
; current_col = 16
movwf
row
movlw
.0
movwf
col
rcall
lcd_goto_xy ; Chuyen cursor ve 1,0
movlw
.1
lcd_print_char
print1
cpfseq
print2
row
bra
movlw
cpfseq
bra
movlw
movwf
movwf
rcall
rcall
movlw
addwf
return
B mn K Thut My Tnh
print2
.16
;current_row = 1
col
print2
.0
; current_col = 16
row
col
; Xoa LCD
lcd_clear
lcd_write_data ;Xuat data ra LCD
.1
col
; Tang col len 1
32

lcd_write_data ;----- trong char
bsf
movff
swapf
rcall
movff
rcall
return
lcd_clear
movlw
movwf
rcall
call
movlw
movwf
movlw
movwf
rcall
return
Khoa KH & KTMT
LCD_RS
; Cho phep xuat data
char,data_4bit ; Xuat 4 bit data cao ra
data_4bit
lcd_write_4bits
char,data_4bit ;Xuat 4 bit data thap ra
lcd_write_4bits
0x01
command
lcd_write_cmd ; Xoa man hinh LCD
delay5ms
; Giu cham 5msec
.0
row
.0
col
lcd_goto_xy
; Cursor ve toa do 0,0
Bc 7.Vit chng trnh khi ng LCD

Hm quan trng nht ca LCD k t chnh l hm khi to LCD. Trc khi s dng c lcd
ta phi khi to cho n theo nh gin khi to lcd trn phn hng dn l thuyt. Port B
v timer c khi to nh trong yu cu 1 Ngoi ra do thit k mch, LCD c th hin th
bnh thng trc tin ta phi bt ngun ca LCD ln, chn ngun ca LCD c iu khin
bi PortD.7 tch cc mc cao, nn trc khi mun s dng LCD ta phi bt PortD.7 ln 1.
;------- Bien cho LCD ---------;
delay
res
delay_1
res
command
res
data_4bit
res
row
res
col
res
addr
res
char
res
;------- Bien cho Timer0 -------;

tmr0_var1
res
decode_var
res
;-------------------------------;
B mn K Thut My Tnh
33
1
1
1
1
1
1
1
1
1
1

init_lcd
init_portD
lcd_goto_xy
Khoa KH & KTMT
rcall
movlw
movwf
movwf
call
bcf
movlw
movwf
rcall
call
rcall
call
rcall
movlw
movwf
rcall
movlw
movwf
rcall
movlw
movwf
rcall
movlw
movwf
rcall
return
init_portD
.0
col
row
delay15ms
LCD_RS
0x03
data_4bit
lcd_write_4bits
delay5ms
lcd_write_4bits
delay100us
lcd_write_4bits
0x02
data_4bit
lcd_write_4bits
0x28
command
lcd_write_cmd
0x0c
command
lcd_write_cmd
0x06
command
lcd_write_cmd
clrf
bcf
bcf
bcf
bcf
bcf
bcf
bcf
bcf
bsf
return
LATD
LCD_D4_DIR
LCD_D5_DIR
LCD_D6_DIR
LCD_D7_DIR
LCD_E_DIR
LCD_RW_DIR
LCD_RS_DIR
LCD_ON_DIR
LCD_ON
; Giu cham 15msec

; Cho phep gui lenh
;
;
;
;Lenh bat dau 4bit
; Hien thi 2 hang, ma tran 5x7
; Display = on
; Set mode : dich phai tang dan
; Data Output
; Control output
; Cap nguon cho LCD
;---- Thiet lap cursor toi toa do x.y

movlw
.0
movwf
addr
movlw
.20
cpfslt
col
B mn K Thut My Tnh
34
bra
movlw
cpfslt
bra
movlw
cpfslt
bra
movlw
mulwf
movff
movf
addwf
bsf
movff
rcall
call
return
movlw
mulwf
movff
movf
addwf
bsf
bsf
bra
xy2
xy3
xy1
Khoa KH & KTMT
xy3
.4
row
xy3
.2
row
xy1
0x40
row
PRODL,addr
col,w
addr
addr,7
addr,command
lcd_write_cmd
delay5ms
; Qua 16 cot
0x40
row
PRODL,addr
col,w
addr
addr,4
addr,2
xy2
; Hang lon hon hay bang 2
; Qua 2 hang
; Hang nho hon 2
; Thiet lap bit7 cua lenh

; Phat lenh
; Giu cham 5msec
Bc 8. n y ta c th vit chng trnh hin th k t ln lcd k t.

tng thc hin y l lc u ta khai bo mt vng nh gm 32 nh tng
ng vi 32 v tr trn lcd k t. Hm lcd_display ca chng ta s thc hin mt vic n gin
l ly d liu cha trong vng nh ny ra hin th ln lcd k t. Cn ngi dng mun
hin th ln lcd th ch cn update gi tr vo vng nh ny l xong.
3.5 Chng trnh mu

#include
radix
p18f4520.inc
dec
B mn K Thut My Tnh
35
Khoa KH & KTMT
#define
#define
#define
#define
#define
#define
#define
#define
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_D4_DIR
LCD_D5_DIR
LCD_D6_DIR
LCD_D7_DIR
LATD, RD0
LATD, RD1
LATD, RD2
LATD, RD3
TRISD, RD0
TRISD, RD1
TRISD, RD2
TRISD, RD3
; LCD data bits
#define
#define
#define
LCD_E
LCD_RW
LCD_RS
LATD, RD6
LATD, RD5
LATD, RD4
; LCD E clock
; LCD read/write line
; LCD register select line
#define
#define
#define
#define
#define
#define
LCD_E_DIR
LCD_RW_DIR
LCD_RS_DIR
LCD_D
LCD_ON
LCD_ON_DIR
TRISD, RD6
TRISD, RD5
TRISD, RD4
PORTD
LATD,RD7
TRISD, RD7
code
0
goto
; LCD data bits
start
udata
;------- Bien cho LCD ---------;
delay
res
delay_1
res
command
res
data_4bit
res
row
res
col
res
addr
res
char
res
;------- Bien cho Timer0 -------;
tmr0_var1
res
decode_var
res
;-------------------------------;
PRG
start
code
call
rcall
rcall
tmr0_loop btfss
bra
rcall
B mn K Thut My Tnh
init_lcd
init_portB
init_timer0
1
1
1
1
1
1
1
1
1
1
; Khoi dong LCD

; Khoi dong portB
; Khoi dong timer0
INTCON,TMR0IF ; Kiem tra trang thai co IF

tmr0_loop
timer0_routine
; Nap lai bo dem
36
tmr0_1
movlw
cpfseq
bra
rcall
call
bra
decode_ascii
movff
movlw
andwf
movlw
cpfslt
bra
movlw
decode_2 addwf
movff
return
decode_1 movlw
bra
init_timer0
Khoa KH & KTMT
.10
tmr0_var1
tmr0_loop
decode_ascii
lcd_print_char
tmr0_loop
; Kiem tar bo dem 10

; Giai ma binary sang ma ASCII
; Xuat ra LCD
PORTB,decode_var
0x0f
decode_var
0x0a
decode_var
decode_1
; Lon hon 9
0x30
; Nho hon hay bang 9
decode_var
decode_var,char
0x37
decode_2
movlw
movwf
bcf
clrf
movlw
movwf
movlw
movwf
bsf
return
.10
tmr0_var1
INTCON,TMR0IF
T0CON
0x3c
TMR0H
0xaf
TMR0L
INTCON,TMR0IF
bcf
decfsz
bra
incf
movlw
movwf
bcf
movlw
movwf
movlw
movwf
bsf
return
INTCON,TMR0IF
tmr0_var1,1
timer0_isr_1
LATB
.10
tmr0_var1
T0CON,TMR0ON
0x3c
TMR0H
0xaf
TMR0L
T0CON,TMR0ON
movlw
movwf
0x0e
ADCON1
timer0_routine
timer0_isr_1
init_portB
B mn K Thut My Tnh

37

clrf
clrf
return
Khoa KH & KTMT

PORTB
TRISB
lcd_print_char;-------trong bin char

movlw
.0
cpfseq
row
print1
cpfseq
print2
bra
movlw
cpfseq
bra
movlw
movwf
movlw
movwf
rcall
movlw
print1
.16
col
print1
.1
row
.0
col
lcd_goto_xy
.1
; current_col = 16
; Chuyen cursor ve 1,0
row
bra
movlw
cpfseq
bra
movlw
movwf
movwf
rcall
rcall
movlw
addwf
return
lcd_write_data ;----- trong char

bsf
movff
swapf
rcall
movff
rcall
return
lcd_clear
; current_row = 0
movlw
movwf
rcall
call
movlw
movwf
movlw
movwf
B mn K Thut My Tnh
print2
16
col
print2
.0
row
col
lcd_clear
lcd_write_data
.1
col
LCD_RS
char,data_4bit
data_4bit
lcd_write_4bits
char,data_4bit
lcd_write_4bits
0x01
command
lcd_write_cmd
delay5ms
.0
row
.0
col
38
;current_row = 1
; current_col = 16
; Xoa LCD
;Xuat data ra LCD
; Tang col len 1
; Cho phep xuat data

; Xuat 4 bit data cao ra
;Xuat 4 bit data thap ra
; Xoa man hinh LCD

; Giu cham 5msec

rcall
return
lcd_goto_xy
xy2
xy3
xy1
init_lcd
lcd_goto_xy
Khoa KH & KTMT

;---- Thiet lap cursor toi toa do x.y

movlw
.20
cpfslt
col
bra
xy3
; Qua 19 cot
movlw
cpfslt
bra
movlw
cpfslt
bra
movlw
mulwf
movff
movf
addwf
bsf
movff
call
return
movlw
mulwf
movff
movf
addwf
bsf
bsf
bra
.4
row
xy3
.2
row
xy1
0x40
row
PRODL,addr
col,w
addr
addr,7
addr,command
lcd_write_cmd
rcall
movlw
movwf
movwf
call
bcf
init_portD
.0
col
row
delay15ms
LCD_RS
movlw
movwf
rcall
call
rcall
call
B mn K Thut My Tnh
0x40
row
PRODL,addr
col,w
addr
addr,4
addr,2
xy2
0x03
data_4bit
lcd_write_4bits
delay5ms
lcd_write_4bits
delay100us
39
; Qua 3 hang
; Hang nho hon 2
; Thiet lap bit7 cua lenh

; Phat lenh
; Hang lon hon hay bang 2
; Giu cham 15msec

; Cho phep gui lenh
;3
;3
init_portD
Khoa KH & KTMT
rcall
movlw
movwf
rcall
movlw
movwf
rcall
lcd_write_4bits
0x02
data_4bit
lcd_write_4bits
0x28
command
lcd_write_cmd
;3
movlw
movwf
rcall
movlw
movwf
rcall
return
0x0c
command
lcd_write_cmd
0x06
command
lcd_write_cmd
clrf
bcf
bcf
bcf
bcf
bcf
bcf
bcf
bcf
bsf
return
LATD
LCD_D4_DIR ; Data Output
LCD_D5_DIR
LCD_D6_DIR
LCD_D7_DIR
LCD_E_DIR
; Control output
LCD_RW_DIR
LCD_RS_DIR
LCD_ON_DIR
LCD_ON
; Cap nguon cho LCD
;Lenh bat dau 4bit 2
; Hien thi 2 hang, ma tran 5x7 28
; Display = on
; Set mode : dich phai tang dan
lcd_write_cmd ;----- trong bin command

rcall
lcd_wait_busy
; LCD san sang
bcf
LCD_RS
; Cho phep lenh
movff
command,data_4bit
swapf
data_4bit
rcall
lcd_write_4bits ; Xuat 4bit lenh cao
movff
command,data_4bit
rcall
lcd_write_4bits ; Xuat 4bit lenh thap
return
lcd_wait_busy ;----- Cho LCD san sang
bsf
LCD_D7_DIR
bsf
bsf
bsf
bcf
bsf
B mn K Thut My Tnh
; RD3 input
LCD_D6_DIR
LCD_D5_DIR
LCD_D4_DIR
; RD2 input
; RD1 input
; RD0 input
LCD_RS
LCD_RW
; Cho phep lenh

; Cho phep doc
40
wait1
Khoa KH & KTMT
rcall
bsf
rcall
btfsc
bra
bcf
bcf
bcf
delay1us
LCD_E
delay1us
LCD_D,3
wait1
LCD_E
LCD_D7_DIR
LCD_D6_DIR
; Cho xong
; Giu cham phan cung
; Kiem tra LCD xong chua ?
bcf
bcf
return
LCD_D5_DIR
LCD_D4_DIR
; RD1 output
; RD0 output
; Xong, cam LCD

; RD3 output
; RD2 output
lcd_write_4bits ;----- Lay 4bit thap trong bin data_4bit

bcf
LCD_RW
; Cho phep viet
bsf
LCD_E
rcall
write_4bit_to_portD; Xuat 4bit data
rcall
delay10us
; Giu cham 10 usec
bcf
LCD_E
; CAM LCD hoat dong
rcall
delay10us
; Giu cham 10 usec
return
Write4bit_to_portD
btfsc
bra
bcf
tt1
btfsc
bra
bcf
tt2
btfsc
bra
bcf
tt3
btfsc
bra
bcf
tt4
return
set_bit_0
bsf
bra
set_bit_1
bsf
bra
set_bit_2
bsf
bra
set_bit_3
bsf
bra
delay15ms
dl_15ms
movlw
movwf
rcall
decfsz
B mn K Thut My Tnh
data_4bit,0
set_bit_0
LCD_D4
data_4bit,1
set_bit_1
LCD_D5
data_4bit,2
set_bit_2
LCD_D6
data_4bit,3
set_bit_3
LCD_D7
LCD_D4
tt1
LCD_D5
tt2
LCD_D6
tt3
LCD_D7
tt4
.15
delay_1
delay1ms
delay_1
41
delay5ms
dl_5ms
delay1ms
dl_1ms
delay100us
dl100us
delay10us
dl10us
delay1us
bra
return
movlw
movwf
rcall
decfsz
bra
return
dl_15ms
movlw
movwf
rcall
decfsz
bra
return
.248
delay
delay1us
delay
dl_1ms
movlw
movwf
rcall
decfsz
bra
return
.98
delay
delay1us
delay
dl100us
movlw
movwf
rcall
decfsz
bra
return
.9
delay
delay1us
delay
dl10us
Khoa KH & KTMT
.5
delay_1
delay1ms
delay_1
dl_5ms
nop
nop
return
; Tan so 16MHz
; 1 chu ky
; 2 chu ky
3.6 Bi tp
a ) Vit chng trnh ng h thi gian thc hh:mm:ss trn LCD. Nhn nt RA4 th
chn ch nhp gi, pht, giy v bt u chy, Nhn nt RB0 tng gi, pht giy ln
cng 1.
B mn K Thut My Tnh
42
Khoa KH & KTMT
Bi 4 : Kho st c ch ngt qung

Ni dung:
Kho st cc nguyn nhn gy ngt qung, cch x l ngt qung, tnh u tin
gia cc ngt ca vi iu khin PIC 18F4520.
Kho st ngt ngoi v ngt timer ca vi iu khin PIC 18F4520.
Xut d liu ra LCD k t 2 x 16.
Yu cu:
1. Vit chng trnh khi to 2 ngt:
Ngt ngoi INT0 (nhn ngt qua nt nhn RB0, Jumper JP6 h) vi u tin
cao. Ngt timer 0 vi u tin thp.
Trong chng trnh ngt ngoi INT0 bt led n RB1, RB2, RB3 sng cng lc.
Trong chng trnh timer 0 sau 1s khi 3 led c bt trong ngt ngoi th tt 3
led n RB1, RB2, RB3 cng lc.
2. Vit chng trnh ng h th thao hin th ln LCD.
4.1 Kin thc lin quan

4.1.1 Tm tt cc thanh ghi iu khin ngt
Thanh ghi INTCON:
Thanh ghi PIE1:
Thanh ghi PIE2:
Thanh ghi PIR1:
Thanh ghi PIR2:
B mn K Thut My Tnh
43
Khoa KH & KTMT
S iu khin ngt:
4.2 Cc bc hin thc yu cu

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Interrupt,
to file interrupt.asm v chn chip 18f4520. Ta c hnh sau:
ADCS2 - ADC Conversion Clock Select bit
PCFG ADC Port Configuration Control bits (see Table below)
ADCON1
ADCS2
0
0
1
X
1
1
0
1
Bc
1 2. Include file p18f4520.inc vo file ext_timer0_int.asm
Bc 3. Khi to PortB l output s dng cc lnh clrf, bcf
initFRC
clrf
LATB
; RB1-RB3 la cong xuat
bcf
TRISB,RB1
FOSC/64
B mn K Thut My Tnh
FOSC/32
44
Khoa KH & KTMT
TRISB,RB2
bcf
bcf
TRISB,RB3
movlw
.10
; khoi dong bien delay=10
movwf
delay
return
Bc 4. Khi to timer 0 to ngt 100 ms (vi xung clock 4 MHz, chn prescaler 2:1, s
m 50000), cho ngt timer 0 c u tin thp.
init_timer0
bsf
RCON,IPEN
; cho phep uu tien ngat.
bcf
INTCON2,TMR0IP
; timer0 uu tien thap
bcf
INTCON,TMR0IF
; xoa co ngat timer0
bsf
INTCON,TMR0IE
; cho phep ngat timer0
bsf
INTCON,GIEH
; cho phep ngat uu tien cao
bsf
INTCON,GIEL
; cho phep ngat uu tien thap
clrf
T0CON
; prescaler 2:1
movlw
HIGH (-50000)
; nap so dem 50000 cho timer0
movwf
TMR0H
movlw
LOW (-50000)
movwf
TMR0L
bsf
T0CON,TMR0ON
; cho phep timer0 dem
return
Bc 5. Khi to ngt ngoi 0 tch cc cnh xung.
i vi ngt ngoi INT1 v INT2, u tin ph thuc vo 2 bit INT1IP v INT2IP
trong thanh ghi INTCON3. Cn vi ngt ngoi INT0 th u tin lun l cao.
init_int0
bcf
INTCON2,INTEDG0 ; tac dong canh xuong
bcf
INTCON,INT0IF
; xoa co ngat
bsf
INTCON,INT0IE
; cho phep ngat ngoai INT0
return
Bc 6.
Vit chng trnh cho ngt ngoi 0, bt 3 n led n cng sng v khi to li
gi tr cho bin delay 1s sau th ngt timer s tt 3 n .
int0_isr
bcf
INTCON,INT0IF
bsf
LATB,RB1
bsf
LATB,RB2
bsf
LATB,RB3
movlw
.10
movwf
delay
return
Bc 7.
Vit chng trnh cho ngt timer0, sau 1s sau khi led c bt sng th n s
lm cho led tt. Kt ni vi chng trnh LCD d hin th.
Thi gian timer m ln 1 n v c tnh bng cng thc :
t = (1/(Focs/4))*prescaler = (1/(4Mhz/4))*2) =2s
Nh vy, mun c thi khong 100 ms (100000s), ta cn m 50000 ln.
timer0_isr
bcf
INTCON,TMR0IF
B mn K Thut My Tnh
45
Trng H Bch Khoa TP.HCM
decfsz
bra
movlw
movwf
timer0_isr_1
Khoa KH & KTMT
delay,1
timer0_isr_1 bcf
LATB,RB1 bcf
LATB,RB2 bcf
LATB,RB3
.10
delay
ADCS2 - ADC Conversion Clock Select bit

PCFG ADC Port Configuration Control bits (see Table below)
ADCON1
ADCS2
0
0
4.3 Chng trnh
mu yu cu
1
#include
radix
X
p18f4520.inc
dec
code1
goto
org 1
goto
0
org
goto1
0
start
08h
isr_high
18h
isr_low
1
udata
FRC cho Timer0 -------;
;------- Bien
tmr0_var1 res
FOSC/64
decode_var
res
1
1
FOSC/32
; Bien cho thoi gian thuc ;

secsFOSC/16 res
mins
res
F
OSC
/8
run_ena
res
1
1
1
FOSC/2
; Xuat giay (so HEX) ra LCD va dung khi nhan nut S3

FOSC/4
PRG
code
Start
rcall0
init
; Khoi dong he thong
int_loop
setf
WREG
1
0
1
0
46
cpfseq
bra
movff
swapf
rcall
call
movff
rcall
call
movlw
movwf
movwf
call
bra
Khoa KH & KTMT
run_ena
int_loop
secs,decode_var
decode_var
decode_ascii
lcd_print_char
secs,decode_var
decode_ascii
lcd_print_char
.0
row
col
lcd_goto_xy
int_loop
; Kiem tra trang thai

;
; Lay byte cao
; Xuat byte1 ra LCD
; Lay byte thap
; Xuat byte2 ra LCD
; Tro ve dau hang
decode_ascii ;----- Giai ma 4bit du lieu trong decode_var ra char -----;

movlw
0x0f
andwf
decode_var
movlw
0x0a
cpfslt
decode_var
bra
decode_1
; Lon hon 9
movlw
0x30
; Nho hon hay bang 9
decode_2 addwf
decode_var
movff
decode_var,char
return
decode_1 movlw
0x37
bra
decode_2
init
init_portB
call
rcall
rcall
rcall
rcall
return
init_lcd init
init_portB
init_timer0
init_int0
init_real_time
; Khoi dong LCD

; Khoi dong portB
; Khoi dong timer0
; Khoi dong ngat ngoai
; Khoi dong dong ho
movlw
movwf
clrf
bsf
bcf
bcf
bcf
bcf
bcf
bsf
0x0e
ADCON1
LATB
TRISB,RB0
TRISB,RB1
TRISB,RB2
RISB,RB3
INTCON2,INTEDG0
INTCON,INT0IF
INTCON,IN
; PortB output digital

; RB0 input
47
; RB1 output
; RB2 output
; RB3 output return init_int0
; Tac dong canh xuong
; Xoa co ngat canh xuong
; Cho phep ngat ngoai INT0
Khoa KH & KTMT
return
init_timer0
movlw
movwf
bsf
bcf
bcf
bsf
bsf
bsf
clrf
movlw
movwf
movlw
movwf
bsf
return
.10
tmr0_var1
RCON,IPEN
INTCON2,TMR0IP
INTCON,TMR0IF
INTCON,TMR0IE
INTCON,GIEH
INTCON,GIEL
T0CON
0x3c
TMR0H
0xaf
TMR0L
T0CON,TMR0ON
; Cho phep uu tien ngat

; timer0 muc uu tien thap
; Xoa co trang thai
; Cho phep timer0 ngat
; Cho phep ngat toan cuc cao
; Cho phep ngat toan cuc thap
; Nap so dem 100msec
; Cho phep dem
init_real_time clrf
clrf
clrf
return
secs
mins
run_ena
timer0_isr
bcf
decfsz
bra
;incf
btg
incf
movlw
movwf
bcf
movlw
movwf
movlw
movwf
bsf
return
INTCON,TMR0IF
tmr0_var1
tmr0_r_1
PORTB
LATB,RB3
secs
.10
tmr0_var1
T0CON,TMR0ON
0x3c
TMR0H
0xaf
TMR0L
T0CON,TMR0ON
; Xoa co trang thai

; Dem = 10 ?
bcf
clrf
cpfseq
bra
clrf
setf
INTCON,INT0IF
WREG
run_ena
int0_1
secs
run_ena
; Xoa co gay ngat
tmr0_r_1
int0_isr
48
; Xuat ra LED
; Nhay D5
; Nap lai so dem 10

; Cam dem
; Nap lai dem 100msec
; Cho phep dem
int0_2
call
return
clrf
bra
delay15ms
isr_high
call
retfie
int0_isr
isr_low
call
retfie
timer0_isr
int0_1
Khoa KH & KTMT
run_ena
int0_2
end
4.4 Bi tp
Vit chng trnh hin th ng h th thao mm:ss trn LCD. Khi nhn nt RA4 bt u
m, bm tip th dng, bm na th chy li t u.
49
Khoa KH & KTMT
Bi 5 : Giao tip ni tip I2C v 24LC256

Mc ch:
Tm hiu chun giao tip I2C v module I2C ca PIC18F.
Tm hiu IC EEPROM 24LC256.
Yu cu:
Vit chng trnh ghi, c v hin th ni dung b nh 24LC256 ln LCD.
5.1 Gii thiu I2C

I2C l 1 chun truyn ni tip theo m hnh Master Slave. Mt Master c th giao
tip vi nhiu Slave. Mun giao tip vi slave no, master phi gi ng a ch tch cc
slave ri mi c php ghi hoc c d liu t slave.
Hnh 5.1 : I2C interface
Bus I2C gm 2 dy tn hiu SCL (Serial Clock Line) v SDA (Serial Data Line) u
c ko ln ngun. D liu c truyn tng bit SDA theo tng clock ca SCL.
Hnh 5.2 : I2C Protocol
Hnh 11.2 l giao thc I2C. Trc khi truyn d liu, ta cn khi ng I2C bng cch
ko ln lt SDA v SCL xung mc thp. Sau 8 bit d liu s c ra tun t theo tng
cnh xung chn SCL. Clock th 9 s dnh cho bit ACK. Bit ACK ny c th l do master
gi xung hoc do slave gi v. Khi kt thc giao tip I2C, ta phi stop n bng cch ko 2
chn SCL v SDA ln mc cao.
50
Khoa KH & KTMT
5.2 I2C trong PIC18F4520

Module I2C trong PIC18F4520 h tr mode master v c slave (7bit a ch v 10bit
a ch). Trong ti liu ny chng ti ch gii thiu mode master ca PIC18F4520 giao
tip vi IC EEPROM 24LC256.
STOP
START
R/W = 0
condition
condition
for write
7 bit address of
Internal address,
Data to be written
Data to be written
Data to be written
peripheral chip
into
address
N
+
1
into
address
N
into
address N + 2 A
A
A N, in peripheral
A
A
C
WK
SDA S
C
K
C
K
C
K
C
K P
Acknowledge
by peripheral
(a) General foemat to write to several pepripheral interal registers or addresses
R/W = 1
START
RESTART
R/W = 0
for write
condition
condition
for write
Internal address,
7 bit address of
7 bit address of
peripheral chip
N,
in
peripheral
peripheral
chip
A
A
A
C
SDA S
WK
STOP
condition
Data read
from addess N
C
K S
RK
Acknowledge
by peripheral
Data read
A from addess N + 1
C
K
Acknowledge by PIC
No acknowledge by PIC, set out as a
signal to terminate further transfers
(b) General format to read format several pepripheral interal registers or addresses
Figure 5- 3 nh dng chui thng tin I2C c bn.

Used to set the IC clock rate
SSPADD
SSPADD = 24 to derive 100 kH

IC clock From Fosc/4 = 2.5 MH
51
NP
O
A
C
K
TRISC
Khoa KH & KTMT
X X X 1 1 X X X
SDA anh SCL pins configured as inputs so that

I2C control circuitry can control I/O direction
SSPCON1 0
0 1 1 1 0 0 0
Select I2C master mode

Enable SCK
SSPEN = 1 : Enable I2C control SDA and SCL pins
SSPSTAT X X X X X X X X Status bits unused by I2C master mode

(a) Initialization
SSPCON2
X
Set SEN to initiate START condition

SEN
Automatically cleared.
RSEN
Set RSEN to initiate RESTART condition

PEN
Set PEN to initiate STOP condition

RCEN
Set RCEN to initiate reception of a byte

ACKEN
Set ACKEN after completion of RCEN to

Ac knowledge with ACKDT bit
ACKDT
1: No acknowledge
See ACKEN anh RCEN
0: Acknowledge
ACKSTAT
1: Acknowledge was not received from peripheral

0: Acknowledge was received from peripheral
52
Write tWrite to SSPBUF to send an address or data byte.

ReadSRead SSPBUF after completion of RCEN commanh
To rea To read the received byte
SSPBUF
PIRI
Khoa KH & KTMT
X X X X
X X X
SSPIE
(b)
1: Operation complete
0: Must be cleared before operation is initiated
Registers used for each message transfer
Figure 5-4 Cc thanh ghi c dng trong ch I2C ch ( master mode ).
5.2.1 Hm i2c_init
u tin ta phi thit lp chiu input cho 2 chn SCL v SDA bng cch thit lp 2 bit
tng ng trong thanh ghi TRISC l 1.
PIC18F4520 s ng vai tr l master gi clock, ni dung trong thanh ghi SSPADD
s c dng cho b sinh clock. Tn s cho giao tip I2C s c tnh theo cng thc sau y
f = Fosc/(4*(SSPADD + 1))
Ta s chn tn s cho SCL l 100kHz v phi np vo thanh ghi ny gi tr 9 (0x09)
cho thnh anh 4MHz.
Tip theo l chn mode master cho PIC18F4520, thit lp SSPM3:SSPM0 = 1000
v enable bit SSPEN trong thanh ghi SSPCON1.
init_I2C
movlw
andwf
clrf
movwf
movwf
movlw
iorwf
bsf
bsf
movlw
movwf
bsf
return
0x3f
SSPSTAT
WREG
SSPCON1
SSPCON2
b'00011000'
SSPCON1
I2C_SCL_DIR
I2C_SDA_DIR
0x09
SSPADD
SSPCON1,SSPEN
53
; bit6,7 = 0
; Xoa 2thanh ghi
; I2C Master mode
; SCL input
; SDA input
; Fscl=100Khz
; Thanh ghi clock
; Cho phep I2C
Khoa KH & KTMT
Hnh 5.5 : Khi ng I2C

5.2.2 Hm i2c_start
khi ng I2C (Start condition) ta ch cn set bit Start Enable, SEN (SSPCON2<0>) v ch
cho n khi qu trnh ny kt thc. Qu trnh khi ng I2C gm nhiu gian on, kt thc
mi giai on s c cc c bo hiu.
Ban u 2 chn SDA v SCL mc cao. Khi SEN = 1, b sinh baudrate bt u m
v khi ht time out, chn SDA ko xung mc thp, bit S (SSPSTAT<3>) bt ln 1 bo hiu
giai on 1 ca qu trnh khi ng I2C kt thc. Sau b sinh baudrate c load li v
bt u m. Khi ht time out, chn SCL s c ko xung thp, kt thc qu trnh khi
ng I2C. Lc ny bit SEN c xa bng phn cng v bit SSPIF c bt ln 1.
I2C_wait
I2C_start
btfss
bra
bcf
return
PIR1,SSPIF
I2C_wait
PIR1,SSPIF
; Cho SSPIF = 1
bsf
call
return
SSPCON2,SEN
I2C_wait
; Thiet lap start enable bit

; Cho xong
; Xoa SSPIF
Hm khi ng li RESTART condition trong nh dng c d liu:

I2C_restart bsf
call
return
SSPCON2,RSEN
I2C_wait
5.2.3 Hm i2c_stop
54
; Thiet lap restart enable bit

; Cho xong
Khoa KH & KTMT
Hnh 5.6 : Stop I2C

Qu trnh kt thc I2C c bt u bng cch set bit PEN (SSPCON2<2>). Cng
ging nh qu trnh khi ng, qu trnh kt thc gm 2 giai on chnh v mi giai on
u c bit bo hiu nhng ta c th lp trnh n gin bng cch set bit PEN v ch cho n
khi SSPIF c set ln 1.
I2C_stop
bsf
call
return
SSPCON2,PEN
I2C_wait
; Thiet lap stop enable bit

; Cho xong
5.2.4 Hm i2c_write_byte
Vic gi 1 byte d liu t master xung slave c bt u khi c lnh gn vo thanh
ghi SSPBUF. Ngay lc ny c BF (Buffer Full) s bt ln 1. Qu trnh gi d liu bt u
theo tng xung clock chn SCL.
Sau 8 clock, 8 bit d liu trong thanh ghi SSPBUF c shift ht v c BF bt xung
0. Master s th chn SDA slave c th gi tn hiu ACK v master. Nu nhn c ACK,
bit ACKSTAT s c xa, ngc li bit ny s c bt ln 1. Gi tr ACK c lu trong
bit ACKDT.
Qu trnh gi ACK t slave ln master c thc hin trong clock th 9 ca SCL v
sau bit SSPIF c set ln 1.
Ngi lp trnh c th check qua cc c BF, ACKSTAT v sau cng l SSPIF
kim tra li. on code di y ch kim tra c nhn c ACK hay khng ch cha kim
tra ACK ng hay sai.
I2C_write_byte ;---- Ghi tu bien I2C_abyte ----;

movff
I2C_abyte,SSPBUF
I2C_w_1
btfsc
SSPSTAT,BF
55
; Truyen ky tu
; Cho truyen xong
bra
btfsc
bra
call
return
I2C_w_2
Khoa KH & KTMT
I2C_w_1
SSPCON2,ACKSTAT
I2C_w_2
I2C_wait
;Slave nhan duoc ?
5.2.5 Hm i2c_read_byte
Hm ny dng c 1 byte d liu t slave v. Khi bit RCEN (SSPCON2<3>) c
set ln 1, d liu t slave bt u gi vo thanh ghi SSPBUF. Sau 8 clock d liu s c
shift vo thanh ghi SSPBUF v c BF s c bt ln 1. ng thi c SSPIF cng c
set v RCEN c clear bng phn cng.
Khi c xong, c SSPIF s c xa, ta cn set ACKEN ln 1 (SSPCON2<4>) gi
ACK v cho slave. Bit ACK l 0 hay 1 c quy nh trong bit ACKDT (SSPCON2<5>).
Khi gi xong ACK clock th 9, c SSPIF s c bt ln li.
I2C_read_byte ;---- Doc dua vao bien I2C_abyte ----;
bsf
SSPCON2,RCEN
call
I2C_wait
clrf
WREG
cpfseq
I2C_Ack_bit
bra
I2C_r1
bcf
SSPCON2,ACKDT
I2C_r2
bsf
SSPCON2,ACKEN
call
I2C_wait
movff
SSPBUF,I2C_abyte
return
I2C_r1
bsf
SSPCON2,ACKDT
bra
I2C_r2
5.3 I2C CMOS Serial EEPROM

Hnh 5-7 S mch
+5v
+5V
U4
8
R8
R9
6
4.7K
ADC
S2 AD
ADC
CS2
Conv
ersio
AD
n
C
Cloc
Con
k
versi
Selec
on
t bit
Cloc
k
PCF
Sele
G
ct bit
ADC
Port
PCF
Conf
G
igura
AD
tion
4.7K
ADCS2
- ADC
Convers
ion
Clock
Select
24LC256
bit
PCFG
ADC
Port
Configu
ration
Control
bits (see
Table
below)
56
ADCO
N1
ADCS
2
1
2
3
4
; Khoi dong nhan = 1

; Cho xong
; Kiem tra Ack or NoAck
; Ack
; Cho phep Ack
; Cho
; No Ack
Khoa KH & KTMT
Figure 9.7 Address sequence bit assignments

Control Byte
1 0 1 0
Address Low Byte
Address High Byte
A A A
2 1 0 R/W
A A A A A A A
14 13 12 11 10 9 8
Chip
Select
Bits
Control
Code
A
0
A
7
x = dont care bit
Figure 5.8 BYTE WRITE

S
T
A
R
T
Bus Activity
Master
SDA Line
Control Byte
S10
Bus Activity
Address
High Byte
AAA
0 2 10 0
x = dont care bit
Address
Low Byte
S
T
O
P
Data
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 5-9 Page write

Bus Activity
Master
SDA Line
S
T
A
R
T Control Byte
Address
High Byte
Address
Low Byte
S
T
O
P
Data Byte 1
Data Byte 0
A AA
Bus Activity
S 1 0 1 0 2 1 0 0A
x = dont care bit
C
K
P
A
C
K
57
A
C
K
A
C
K
A
C
K
Khoa KH & KTMT
Figure 5.10 RANDOM READ

S
Bus Activity T
A
Master
R
T
SDA Line
Address
High Byte
Control Byte
A AA
S1 0 1 02 100
Bus Activity
x = dont care bit
S
T
A
R
T
Address
Low Byte
x
A
C
K
A
C
K
A
C
K
S
T
O
P
Data
Byte
Control
. Byte
A AA
S1 01 02 10 1
P
N
O
A
C
A
C
K
Figure 5.11 SEQUENTIAL READ
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
A
C
K
A
C
K
58
S
T
O
P
Data (n + x)
A
C
K
N
O
A
C
K
Khoa KH&KTMT
5.4 Xy dng chng trnh

y s gii thiu chng trnh mu ghi vo b nh 24LC256 sau kt hp vi chng trnh LCD
hin th thng tin c c ln LCD.
#include
radix
p18f4520.inc
dec
#define
#define
#define
#define
I2C_SCL_DIR TRISC
I2C_SDA_DIR TRISC
SLAVE_WRITE
SLAVE_READ
code
goto
0
start
,RC3
,RC4
0xA0
0xA1
; input and output
udata
;------- Bien cho I2C -------;
I2C_abyte res
I2C_data
res
decode_var res
1
1
1
addr_24C256res
I2C_Ack_bit res
;-------------------------------;
2
1
PRG
code
call
init_lcd
rcall
init_I2C
movlw
0xaa
movwf
I2C_data
clrf
WREG
movwf
addr_24C256
addr_24C256 +1
rcall
Viet trong I2C_data
rcall
Doc vao I2C_data
movff
I2C_data,decode_var
swapf
decode_var
call
decode_ascii
call
lcd_print_char
movff
I2C_data,decode_var
call
decode_ascii
call
lcd_print_char
bra
$
start
; Khoi dong LCD

; Khoi dong I2C
; Nap du lieu kiem tra
; Dia chi kiem tra
; Nap dia chi thap
movwf
; nap dia chi cao
WriteArrayIntAddr_24C256
ReadArrayIntAddr_24C256
; Dua vao bien giai ma

; Lay 4bit cao
; Giai ma binary - ASCII
; Xuat ra LCD
; Lay 4bit thap
; Giai ma binary - ASCII
; Xuat ra LCD
;------ Chuong trinh cua I2C -------;

init_I2C
movlw
andwf
clrf
movwf
movwf
movlw
iorwf
bsf
bsf
movlw
movwf
bsf
return
0x3f
SSPSTAT
WREG
SSPCON1
SSPCON2
b'00011000'
SSPCON1
I2C_SCL_DIR
I2C_SDA_DIR
0x09
SSPADD
SSPCON1,SSPEN
; bit6,7 = 0
; Xoa 2thanh ghi
; I2C Master mode
; SCL input
; SDA input
; Fscl=100Khz
; Thanh ghi clock
; Cho phep I2C
59
Khoa KH&KTMT
WriteArrayIntAddr_24C256; Viet 1 byte trong I2C_data vao dia chi addr_24C256

call
I2C_start
; Khoi dong
movlw
SLAVE_WRITE ;0xA0
movwf
I2C_abyte
; Xuat dieu khien
call
I2C_write_byte
movff
addr_24C256 + 1,I2C_abyte` ; Phat dia chi cao
call
I2C_write_byte
movff
addr_24C256,I2C_abyte
; Phat dia chi thap
call
I2C_write_byte
movff
I2C_data,I2C_abyte
; Xuat du lieu
call
I2C_write_byt
call
I2C_stop
call
delay15ms
return
ReadArrayIntAddr_24C256; Doc 1 byte co dia chi addr_24C256 vao I2C_data
Call
I2C_start
; Khoi dong
movlw
SLAVE_WRITE
movwf
I2C_abyte
; byte dieu khien
call
I2C_write_byte
movff
addr_24C256 + 1,I2C_abyte ; Phat dia chi cao
call
I2C_write_byte
movff
addr_24C256,I2C_abyte
; Phat dia chi thap
call
call
movlw
I2C_write_byte
I2C_restart
SLAVE_READ
movwf
call
setf
call
call
movff
return
I2C_abyte
I2C_write_byte
I2C_Ack_bit
I2C_read_byte
I2C_stop
I2C_abyte,I2C_data
; Khoi dong lai

; Nap byte DK
I2C_read_byte ;---- Doc dua vao bien I2C_abyte ----;

bsf
SSPCON2,RCEN
call
I2C_wait
clrf
WREG
cpfseq
I2C_Ack_bit
bra
I2C_r1
bcf
SSPCON2,ACKDT
I2C_r2
bsf
SSPCON2,ACKEN
call
I2C_wait
movff
SSPBUF,I2C_abyte
return
I2C_r1
bsf
SSPCON2,ACKDT
bra
I2C_r2
I2C_write_byte ;---- Ghi tu bien I2C_abyte ----;
movff
I2C_abyte,SSPBUF
I2C_w_1
btfsc
SSPSTAT,BF
bra
I2C_w_1
I2C_w_2
btfsc
SSPCON2,ACKSTAT
bra
I2C_w_2
call
I2C_wait
return
I2C_wait
I2C_start
;
; Phat byte DK
; No Ack : byte cuoi
; chuyen vao I2C_data
; Khoi dong nhan = 1
; Cho xong
; Kiem tra Ack or NoAck
; Ack
; Cho phep Ack
; Cho
; No Ack
; Truyen ky tu
; Cho truyen xong
;Slave nhan duoc ?
btfss
bra
bcf
return
PIR1,SSPIF
I2C_wait
PIR1,SSPIF
; Cho SSPIF = 1
bsf
call
return
SSPCON2,SEN
I2C_wait
; Thiet lap start enable bit

; Cho xong
; Xoa SSPIF
60
Khoa KH&KTMT
I2C_restart bsf
call
return
SSPCON2,RSEN
I2C_wait
; Thiet lap restart enable bit

; Cho xong
I2C_stop
SSPCON2,PEN
I2C_wait
; Thiet lap stop enable bit

; Cho xong
bsf
call
return
end
5.5 Bi tp:
Vit vo 256 byte ca EEPROM 24LC256 bt u t a ch 0000 vi ni dung t 00 n
0xFF. c li ni dung v xut d liu mi ln 32 byte ln LCD.
61
Khoa KH&KTMT
Bi 6 : Giao tip ni tip SPI

6.1 Gii thiu v SPI
SPI (Serial Peripheral Interface) l mt dng giao thc truyn ni tip c dng
giao tip vi cc thit b ngoi vi(EEPROM,SDcard) v cc vi iu khin khc.
6.1.1 Ch SPI trong vi iu khin PIC

Giao tip SPI c hin thc qua 4 chn ca vi iu khin:
SDI( Serial Data In ): Tn hiu ni tip c a vo vi iu khin SDO(
Serial Data Out): Tn hiu ni tip t vi iu khin i ra CLK(Clock): xung
clock to ra bi master
SS(Slave Select): tch cc mc thp, dng chn slave truyn d liu
Hnh 6-1 S khi ca SPI
6.1.2 Cc thanh ghi iu khin SPI

Ch SPI c iu khin bng 4 thanh ghi sau
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register(SSPBUF)
MSSP Shift Register(SSPSR) thanh ghi ny khng c truy xut bi ngi dng
Hai thanh ghi SSPCON1 v SSPSTAT l hai thanh ghi iu khin, cn than ghi
62
Khoa KH&KTMT
SSPSR l thanh ghi dng dch d liu ra/vo vi iu khin, SSPBUF l thanh ghi dng
c d liu t ngoi vo hoc ghi d liu truyn ra ngoi. ch nhn, 2 thanh SSPBUF v SSPSR
l 1 b buffer i, khi d liu t ngoi truyn vo c lu y trong SSPSR(8 bits) th d liu ny
AD
c truyn ti thanh ghi SSPBUF ngi dng
CS ly ra. Cn ch truyn th khi d liu c ghi
vo thanh ghi SSPBUF th cng lc d liu cng
2 - c ghi vo thanh ghi SSPSR dch ra ngoi.
AD
C
6.1.2.1 Thanh ghi SSPSTAT
Con
Bit
vers
7
6
5
4 ion
3
Read/Write ADCS2 - ADC Conversion Clock Select bit Clo
ck
PCFG
ADC
Port
Configuration
Control
bits
(see
R/W
R/W
R
R SelTable below)
R
ect
Initial Value ADCON1
0
0
0
0
0
bit
R
0
R
0
R
R
0
Bit 7 ADCS2
SMP Sample bit
PC
SPI Master mode
FG
01 = d liu vo s c ly cui chu
k xung clock
AD
00 = d liu vo s c ly gia chu
C k cung clock
Port
SPI Slave mode
Con
1SMP phi c gn bng 0
figu
Bit 6 XCKE SPI Clock Select bit
rati
Bit 0 BF BuFffer Full Status bit(dnh choonqu trnh nhn)
Con y
11 = qu trnh nhn hon thnh, SSPBUF
trol
0 = qu trnh nhn ang thc hin, SSPBUF
trng
bits
1
6.1.2.2
Thanh
ghi SSPCON1
0
(see
Tab
le
4 bel
3
SSPM3ow) SSPM2
Bit
7
6
5
2
1
0
1
WCOL
SSPOV SSPEN
CKP
SSPM1 SSPM0
Read/Write
R/W
R/W
R
R
R
R
R
1
AD
Initial Value 0
0
0
0
0
0
0
CO
F
RC
Bit 7 WCOL Write Collision Detect bit(ch dng ch truyn tn hiu)
N1
R
0
1 =/64
thanh ghi SSPBUF c ghi d liu trong khi d liu c truyn cha ht
FOSC
AD
0 = khng c ng
CS
/32
Bit 6 FOSC
SSPOV
Receive Overflow Indicator
bit(dng ch nhn tn hiu)
2
1 = c d liu mi nhn v ghi ln thanh ghi SSPBUF trong khi d liu trc
FOSC/16
0
cha c c.
FOSC
0 =/8d liu khng b ghi
0
Bit 5 SSPEN Synchronous Serial Port Enable bit
FOSC/2
1 SDO, SCK, SS c cu hnh tng ng.
1 = bt ch SPI v cc chn SDI,
0 =/4tt ch SPI
FOSC
X
Bit 4 CKP Clock Polarity Select bit
0
1 = thit lp trng thi rnh khi xung
1 clock mc cao
1 0 = thit lp trng thi rnh khi xung clock mc thp
1
Bit 3-0 SSPM3:SSPM0 Synchronous Serial Port Mode Select bit
0 0101 = ch slave, clock = chn SCK, tt chc nng ca chn SS
0
1
0
0
63
1
1
Khoa KH&KTMT
0100 = ch slave, clock = chn SCK, bt chc nng ca chn SS

0011 = ch master, clock = tn s ca timer 2 /2
0010 = ch master, clock = Fosc / 64

6.1.3 Cu hnh SPI
cu hnh ch SPI cho vi iu khin PIC ta s dng cc bit SSPCON1<5:0> v SSPSTAT<7:6>,
khi cu hnh cc bit ny SPI ca PIC s c cu hnh ch master hoc slave, cung clock cho SPI, v
thit lp vic nhn d liu xy ra cnh ln hoc xung ca xung clock. Thanh ghi SSPSR c chc nng
dch d liu ra v vo vi iu khin v lun l bit trng s cao trc. trong ch truyn, thanh ghi
SSPBUF s ch cho n khi thanh ghi SSPSR sn sng nhn d liu ri mi ghi d liu ln thanh ghi
SSPSR, nu c hnh ng ghi d liu vo thanh ghi SSPBUF trong lc d liu truyn cha xong th hnh
ng c b qua v bit WCOL c bt ln bo hiu c xy ra ng . trong ch nhn, sau khi
SSPSR nhn 8 bit d liu s c chuyn n thanh ghi SSPBUF v bit BF c bt ln bo hiu,
nu d liu trc c lu trong thanh ghi SSPBUF cha c c m li c thm d liu mi th d
liu mi s ghi ln d liu c v bit SSPOV c bt ln.
Hnh 6-2 Kt ni SPI master/slave
Hm cu hnh ch SPI master cho vi iu khin PIC

init_SPI
init_Port
bsf
bsf
bsf
bcf
bcf
bcf
bcf
return
movlw
movwf
bcf
bsf
bcf
SSPSTAT,CKE
SSPCON1,CKP
SSPCON1,SSPEN
SSPCON1,SSPM0
SSPCON1,SSPM1
SSPCON1,SSPM2
SSPCON1,SSPM3
; Cho phep truyen o canh len clock

; clock first, second data
; Cho phep SPI chu
;
;
;
; preacaler
1:4
0x0f
ADCON1
SPI_LAT_DIR
SPI_LATCH
SPI_SCK_DIR
; Port digital
; PortBx output
;=1
; SCK output
64
Khoa KH&KTMT
bcf
bcf
SPI_SDO_DIR
SPI_SCK
; SDO output
return
7 6 5 4 3 2 1 0
0 X0 X X
TRISC X0 X
SCK = Output
SDI =
1 if used by SPI
0 if not used by SPI; RC4 = output pin
SDO =
1 if used by SPI
0 if not used by SPI; RC4 = input pin
7 6 5 4 3 2 1 0
SSPCON1 X0 X 1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
SPI clock = FOSC/4

SPI clock = FOSC/16
SPI clock = FOSC/64
SPI clock = TMR2 output/2
SPI master mode
Unused in SPI mode

SSPEN = 1 to enable SPI
Status bits, unused by SPI
SPI
7 6 5 4 3 2 1 0
SSPSTAT
0 0 0 0 0 0
Unused in SPI mode

CKE- see Figure 15-3
SMP- see Figure 15-3
(a) Control registers needing initialization
7 6 5 4 3 2 1 0
X X X
PIR1 X0 X X1XX
SSPIE =
7 6 5 4 3 2 1 0
SSPBUF
1: Transfer completed
0: Must be cleared before transfer
A write to SSPBUF initiates both ADO and SDI transfers.

At completion, SSPBUF holds the SDI input.
(b) Operational registers for effecting trasfers
Hnh6-3 Tp thanh ghi s dng trong ch SPI

65
Khoa KH&KTMT
6.2 : iu khin 74HC595 v led 7 on bng SPI

6.2.1 Kt ni phn cng
6.2.1.1 Kt ni phn cng led 7 on
LED 7 on gm c 7 on c nh du: a, b, c, d, e, f, g v mt im dp.
A
D
C
S
2
A
A D
A
A
D
A D D C C
S2
C
D
S l
- 7 on c C
LED
hai
loi
- Common Anode v Common
S
C S
2 A
Anode
2
S
2
A
D
2
- C
D
PIC18F452
C
Co
A nv
A
A
D ers
SPI C
D clock
A11 Serial
D
C io
o
RC3/SCK
D C C
n
RC5/SDO C14 Data in n
C Cl
v
C
C
o
e
D
D
D
D
C o o nD oc
r
k
n Q
Q
Q
Q
Q
o
n
v Se
s
AD
v
n
v
e lec
i
e
C
v
e
r t
o
12 Latch
r
e
Clo
r
s bit
n RB5
clock
s
(arbitrary
r
ck
s
iD
D
D
D
D
i
s
output
pin)
AD
i
o
C
P
Q
Q
Q
Q
Q
o
i
o
n C
CO
l
n
o
n
RAM
N0
o
F
n
1
15
4
2
3
C G
OUT c
AD
C
C
l
k
CO
C l l o
A
N1
o
l
o
c D b1
b3
b4
S
b2
b0
c
o
c
k
e
C
k
c
k
l
Po
Fre
k
S rt
e
S
que
S
e Co
c
e
S
ncy
e
l
t
nfi
l
e
AD
l
e gu
e
l
CS
e
c rat
b
c
e
c
t
1
i
io
t
c
t
t
n
AD
Out
t
b
b Co
CS
(c)
Circuit
b
b
i
i
ntr
0
i
i
t
P
t
ol
t
t
C
bit
P
F
s
P
AD
C
P (se
G
66
C F P C
CS
e
C
F
G
F Ta
2
F
G
G bl
G
A
e
be
D
A
AD
C
Cathode, ta s dng loi common
74HC595
Data out
D
Q
D
Q
D
Q
Vcc
Reset
+5V
16
10
0.1uF
D
Q
D
Q
D
Q
b5
b6
b7
OE
GND
13
8
Khoa KH & KTMT
7 6 5 4 3 2 1 0
TRISC X X 0 X 0 X X X
SDO and SCK are outputs
TRISB X X 0 X X X X X
RB5 is an output for latch clock
SSPCON1 X X 0 X X X X X
SSPSTAT X X 0 X X X X X
SPI master mode with SCK = PICs internal clock

CKP = 0
CKE = 1
SMP = 1
(b) Ininitialization
SSPIE
SCK
SDO
bit 1 bit 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2

RB5
1
bcf PIR1, SSPIF

movff OUT, SSPBUF
Wait for SSPIF = 1
bcf PORTB, RB5
bsf PORTB, RB5
(c) Timing and instruction sequence
Hnh 6-4 S kt ni PIC 18F4520 v 74HC595 dng SPI m rng cng xut
bi ny chng ta s s dng mch ph gm 1 led 7 on c s dng giao tip vi

vi iu khin thng qua giao thc SPI vi 74HC595. Vi iu khin PIC ng vai tr l master
v IC 74HC595 ng vai tr l slave vi chc nng dch bit, m v o tn hiu u vo
Cch thc hot ng ca mch l vi iu khin s dch d liu cn xut ra ngoi n IC
dch, v khi no dch d liu cn xut ra ngoi vi iu khin s kha d liu li bng cch
to mt xung t thp ln cao trn chn LATCH ca IC dch ny, lc ny IC dch s ly d liu
c ct trong b m trong qu trnh dch d liu ca vi iu khin v xut ra ngoi.
6.2.2 Xy dng chng trnh

Ngoi hm cu hnh ch SPI cho PIC nhu bi trn, chng ta cn hin thc thm
hm to tn hiu LATCH.
B mn K Thut My Tnh
67
Thc hnh Vi x l-Vi iu khin
Khoa KH & KTMT
6.2.2.1 Hm to tn hiu LATCH

latch_SPI
bcf
call
bsf
call
return
SPI_ LATCH
delay1us
SPI_LATCH
delay1us
;=0
;=1
6.2.2.2 Hm xut led 7 on
AD
CS2
Vi cng gii thut qut led nh bi
trn ch khc l trong chng trnh ngt
timer ta gi hm xut trc tip d liu ra cc AD
port ca vi iu khin th ra gi hm dch d
C
t vi iu khin ra cc IC ngoi vi.Chi tit hm dch nh sau:
Con
vers
ion
xuat_du_lieu;------ Xuat du lieu tu SPI_var -------;
Clo
ck
movff
SPI_var,SSPBUF
Sele
xuat1
btfss
SSPSTAT,BF
ct
bra
xuat1
bit
call
return
6.3 Xy dng chng trnh
#include
radix
#define
#define
#define
#define
#define
#define
code
goto
udata
;------- Bien cho SPI ---------;

SPI_var
PRG
start
rcall
rcall
movlw
movwf
call
bra
latch_SPI
PC
FG
AD
mu
C
Port
Con
figu
p18f4520.inc
ratio
dec
n
SPI_SCK_DIR
TRISC,RC3
Con
SPI_SDO_DIR
trol
TRISC,RC5
bits
SPI_LAT_DIR
TRISB,RB4
(see
SPI_LATCH
LATB,RB4
SPI_SCKTabl
LATC,RC3
SPI_SDOe
LATC,RC5
belo
0
w)
start
AD
CO
N1
res
1
code
AD
init_Port CS
init_SPI 2
b'11111110'
SPI_var 0
xuat_du_lieu
0
$
; Khoi dong portB,C

; Khoi dong SPI
; Nap du lieu test
B mn K Thut My Tnh
68X
1
ca
liu
Khoa KH & KTMT
;------ Chuong trinh cua SPI -------;

init_SPI
bsf
bsf
bsf
bcf
bcf
bcf
bcf
return
SSPSTAT,CKE
SSPCON1,CKP
SSPCON1,SSPEN
SSPCON1,SSPM0
SSPCON1,SSPM1
SSPCON1,SSPM2
SSPCON1,SSPM3
; Cho phep truyen o canh len clock

; clock first, second data
; Cho phep SPI chu
;
;
;
; preacaler
1:4
Latch_SPI
bcf
call
bsf
call
return
SPI_LATCH
delay1us
SPI_LATCH
delay1u
;=0
;=1
xuat_du_lieu;------ Xuat du lieu tu SPI_var -------;

movff
SPI_var,SSPBUF
xuat1
btfss
SSPSTAT,BF
bra
xuat1
call
latch_SPI
return
delay1us
nop
; Tan so 4MHz
nop
; 1 chu ky
return
; 2 chu ky
end
6.4 Bi tp
a) Vit chng trnh xut ra led 7 on cc gi tr t 0 n 9, t A n F.
b) Xc nh tc cao nht v tc nh nht ca giao tip SPI vi tn s hot ng ca thch
anh l 4Mhz.
B mn K Thut My Tnh
69
Bi 7 :
Khoa KH & KTMT
Kho st b truyn nhn ni tip
Ni dung:
Kho st b truyn ni tip ca PIC.
Tm hiu mch truyn nhn ni tip t h e o c h u n R S 2 3 2 .
Yu cu:
Vit chng trnh giao tip truyn v nhn 32 byte d liu ca vi iu khin
PIC.18F4520 t TXD sang RXD. Tc d liu thay i t 1200Hz n 56KHz.
C hay khng c parity.
Hnh 7-1 Giao tip UART ca PIC kt ni vi my tnh

dn gin, th nghim ni tt 2 chn 2 v 3 ca DE9S FRS, sau kt ni vi my
tnh thng qua chng trnh Terminal.
TRISC 1 0 X X X X X X
RC6/TX set up as an output
RC7/TX set up as an output
B mn K Thut My Tnh
70
SBRG
TXSTA
Khoa KH & KTMT
Serial port baud-rate generator ( Figure 18-4)
0 0 1 0 0
0 0
BRGH, high/low baud rate select ( Figure 18-4)

TXEN = 1 : Enable transmit function
RCSTA
1 0 0 1 0
OERR
1: Overrun error has occurred; clear

. by clearing, then setting, CREN bit
0: No overrun error
1: Framing error has occurred; clear

FERR . by clearing, RCREG
0: No framing error
CREN = 1 : Enable receive function
SPEN = 1 : Enable serial port (configures RC7/RX
.
and RC6/TX pins as UART pins)
TXREG
Transmit register
RCREG
Receive register
PIR1 X X
X X X X
1: Set when TXREG is empty and ready

TXIF . for more data to be transmitted
0: Clear when TXREG is full, waiting as
. TSR is cleared out
1: Set when a byte is available in RCREG
RCIF 0: When FIFO has been cleared out by
one or two reads of RCREG
IPE1 X X
X X X X
B mn K Thut My Tnh
TXIF
1: Enable interrupt when TXIF = 1

0: Disable TX interrupts
RCIF
1: Enable interrupt when RCIF = 1

0: Disable RX interrupts
71
Khoa KH & KTMT
IPR1 X X 0 0 X X X X
TXIP high/low priority select for TX interrupts
RCIE high/low priority select for RX interrupts
RCON 1 X X X X X X X
IPEN = 1: Enable high/low interrupt structure
INTCON 1 1 X X X X X X
GIEL, global enable for low-priority interrupts
GIEH, global enable for all interrupts
Hnh 7-2 Tp thanh ghi UART

Trnh t cc bc thit lp truyn nhn ni tip nh sau :
Np gi tr vo 2 thanh ghi BRGH: BRG thit lp tc truyn theo cng
thc Baudrate = Fosc/ (16 * ([BRGH : BRG] + 1)).
Enable serial port bng cch clear bit SYNC v set bit SPEN
Nu mun thit lp interrupt, th set thm TXIE, GIE v PEIE.
Set bit TXEN cho php truyn.
Np d liu vo thanh ghi TXREG.
Khi truyn xong c TXIF s bt ln 1, ta s kim tra c ny trc khi truyn
d liu mi.
7.1 Cc bc hin thc.

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l Uart v
chn chip 18f4520. Ta c hnh sau:
B mn K Thut My Tnh
72
Khoa KH & KTMT
Bc 2. Include file p18f4520.inc vo file uart.asm

Bc 3. Khi to PORTC.6 l output, PORTC.7 l input.
Init_port_RC67
bcf
bsf
TRISC,6
TRISC,7
; Make RC6 an output

; Make RC7 an input
Bc 4.
Khi to cc vector ngt
code
goto
org
goto
B mn K Thut My Tnh
0
start
08h
isr_high
73
Khoa KH & KTMT
Bc 5. Khi to cho ngt UART, tc 9600baud ti tn s 4Mhz.

init_UART
movlw
19h
; 9600 bauds @ 4MHz
movwf
SPBRG
bsf
TXSTA,TXEN
; Cho phep truyen
bsf
TXSTA,BRGH
; Chon toc do baud cao
bsf
RCSTA,SPEN
; Cho phep cong noi tiep
bsf
RCSTA,CREN
; Cho phep nhan dong thoi
bcf
PIR1,RCIF
; Xoa co ngat RCIF
bsf
PIE1,RCIE
; Cho phep nhan ngat
bsf
INTCON,PEIE
; Cho phep ngoai vi ngat
bsf
INTCON,GIE
; Cho phep ngat toan cuc
return
Bc 6. Vit chng trnh trong ngt thc hin nhim v nhn mt d liu t TX truyn
xung qua.
UART_isr
ISREnd
RcvError
btfss
bra
movlw
andwf
btfss
bra
movff
movff
swapf
rcall
call
movff
rcall
call
return
bcf
bsf
movlw
movwf
call
bra
PIR1,RCIF
ISREnd
06h
RCSTA,W
STATUS,Z
RcvError
RCREG,UART_var
UART_var,decode_var
decode_var
decode_ascii
lcd_print_char
UART_var,decode_var
decode_ascii
lcd_print_char
; Co phai USART gay ngat ?
RCSTA,CREN
RCSTA,CREN
'L'
decode_var
lcd_print_char
ISREnd
; Xoa trang thai nhan

;?
; Kiem tra loi

; Co loi khong ?
; Co loi
; Dua du lieu vao bien
; Xuat du lieu ra LCD
; Lay byte cao
; Xuat byte1 ra LCD
; Lay byte thap
; Xuat byte2 ra LCD
; Xuat byte1 ra LCD
7.2 Chng trnh mu

#include
radix
p18f4520.inc
dec
code
0
goto
start
org
08h
goto
isr_high
B mn K Thut My Tnh
74
Thc hnh Vi x l
Khoa KH & KTMT
udata
;------- Bien cho UART ---------;
decode_var res
UART_var res
PRG
start
main1
code
call
rcall
rcall
movlw
movwf
btfss
bra
bcf
bra
1
1
init_lcd
init_RC67
init_UART
0x0f
TXREG
PIR1,TXIF
main1
PIR1,TXIF
$
; Khoi dong LCD

; Khoi dong Port RC6,RC7
; Khoi dong UART
; Gui ky tu qua cong phat
; Truyen xong chua ?
;------ Chuong trinh cua UART -------;

init_RC67 bcf
bsf
return
init_UART
movlw
movwf
bsf
bsf
bsf
bsf
bcf
bsf
bsf
bsf
return
TRISC,6
TRISC,7
; RC6 output
; RC7 input
19h
SPBRG
TXSTA,TXEN
TXSTA,BRGH
RCSTA,SPEN
RCSTA,CREN
PIR1,RCIF
PIE1,RCIE
INTCON,PEIE
INTCON,GIE
; 9600 bauds @ 4MHz

; Cho phep truyen
; Chon toc do baud cao
; Cho phep cong noi tiep
; Cho phep nhan dong thoi
; Xoa co ngat RCIF
; Cho phep nhan ngat
; Cho phep ngoai vi ngat
UART_isr
btfss
bra
movlw
andwf
btfss
bra
movff
movff
swapf
rcall
call
B mn K Thut My Tnh
PIR1,RCIF
; Co phai USART gay ngat ?
ISREnd
06h
RCSTA,W
; Kiem tra loi
STATUS,Z
; Co loi khong ?
RcvError
; Co loi
RCREG,UART_var ; Dua du lieu vao bien
UART_var,decode_var; Xuat du lieu ra LCD
decode_var
; Lay byte cao
decode_ascii
lcd_print_char
; Xuat byte1 ra LCD
75
Thc hnh Vi x l
Khoa KH & KTMT
movff
rcall
call
ISREnd return
RcvError bcf
bsf
movlw
movwf
call
bra
UART_var,decode_var; Lay byte thap

decode_ascii
lcd_print_char
; Xuat byte2 ra LCD
isr_high
UART_isr
call
retfie
RCSTA,CREN
RCSTA,CREN
'L'
decode_var
lcd_print_char
ISREnd
; Xoa trang thai nhan

;?
; Xuat byte1 ra LCD
end
7.3 Bi tp
a) Vit chng trnh bng hp ng gi 1 chui d liu t 0 n 31 qua cng TxD
v nhn qua RxD ri hin th ln LCD.
b) Thay i tc truyn t 1200 bauds ln 56Kbauds.
c) Thay i kim tra parity.
B mn K Thut My Tnh
76
Thc hnh Vi x l
Bi 8 :
Khoa KH & KTMT
Kho st khi chuyn i A-D
Ni dung:
Kho st hot ng khi chuyn i A-D.
Kho st cc thanh ghi iu khin hot ng khi chuyn i A-D.
Yu cu:
Vit chng trnh c v hin th gi tr in p thay i bi bin tr.
8.1 Cc bc hin thc

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l a2d v chn
chip 18f4520. Ta c hnh sau:
Bc 2. Include file p18f4520.inc vo file a2d.asm

Bc 3. Khi to module ADC ta c th s dng mt cch d dng.
InitializeAD
movlw
movwf
movlw
movwf
movlw
movwf
call
bsf
return
B'00000100'
ADCON1
B'11000001'
ADCON0
0x01
ADCON2
SetupDelay
ADCON0,GO
B mn K Thut My Tnh
; Make RA0,RA1,RA4 analog inputs selected

; Select RC osc, AN0
; A/D enabled
; delay for 15 instruction

; Start first A/D conversion
77
Thc hnh Vi x l
Khoa KH & KTMT
khi to c module ADC ta ch cn quan tm ch yu ti cc thanh ghi

ADCCON1, ADCCON0, ADCON2. Nh chng trnh khi to trn ta thy u tin phi
cu hnh cho cc pin tng ng phi l chn AN0, mc nh ca cc chn ny c chc
nng l Input/Output digital. Sau ta phi chn knh ADC tng ng, y ta s dng
knh AD0. V mt im quan trng na chnh l bit GO trong thanh ghi ADCON0, khi
bt ny c bt ln th module AD mi bt u chuyn i tn hiu.
Bc 4. Tip theo l hm c gi tr ADC:
Update_adc
bsf
btfsc
bra
movf
return
ADCON0,GO ;start conversion

ADCON0,GO
$-2
ADRESH,W
Sau khi chuyn i tn hiu A-D, gi tr s s c lu vo thanh ghi ADRESH. n

y ty vo ng dng c th m ta c th bin i gi tr ny ty theo yu cu m
ta mong mun.
ADCON 0
- 1
ADON =
1:ADC is powered up
0:ADC is shut off to save power
Set to begin conversion

GO_DONE Automatically cleared to signal when
conversion has been completed
000
001
010
011
100
101
110
111
Select AN0 (RA0)

Select AN1 (RA1)
Select AN2 (RA2)
Select AN3 (RA3)
Select AN4 (RA4)
Select AN5 (RA5)
Select AN6 (RA6)
Select AN7 (RA7)
ADCS1, ADCS0 (See Figure 10-9)
B mn K Thut My Tnh
78
Thc hnh Vi x l
PIC18F452
PORTE
Power to I/O
circuitry for
individual pins
controlled by
ADCON1 selection
(Power turned off at
reset)
ADC
Ten-bit
converter
Khoa KH & KTMT
PORTA
RE2
RE2/AN7
RE1
RE1/AN6
RE0
RE0/AN5
RE5
RE5/AN4
RE4
RA4
RE3
RA3/AN3/VREF+
RE2
RA2/AN2/VREF -
RE1
RA1/AN1
RE0
RA0/AN0
ADC multiplexer
controlled by
ADCON0 selection
Analog
input
voltage
VDC
VREF +
Reference
voltage
VREF Reference voltage
switch controlled by
ADCON0 selection
0 1
ADCON0
ADCON1
ADCS0
ADCS1
B mn K Thut My Tnh
1
ADCS2
79
Thc hnh Vi x l
Khoa KH & KTMT
ADC Clock
ADCON0
ADCON1
Frequency ADCS1 ADCS0 ADCS2
FOSC /2
FOSC /4
FOSC /8
FOSC /16
FOSC /32
FOSC /64
FRC
FOSC is the oscillator frequency

(i.e.,four time the chips internal clock rate)
FRC is the frequency of an internal RC
oscillator. (167 kHz < FRC <500kHz)
ADCON1 1 1 - PCFG-ADC port configuration control bits (see table below)
ADCS2-ADC conversion clock select bit (see Figure 10-9)
ADFM-ADC result format select bit (see Figure 10-9)
AN3
(RA3)
AN2
(RA2)
AN1
(RA1)
VREF
+
VREF
+
0100
0101
010X
1000
1001
1010
PCFG
AN7
(RE2)
AN6
(RE1))
0000
0001
0010
0011
AN5
(RE0)
AN4
(RA5)
AN0
(RA0)
VREF +
VREF -
VDD
VSS
AN3
VSS
VDD
VSS
AN3
VSS
VDD
VSS
VREF
+
AN3
VSS
VREF
+
VREF
-
AN3
AN2
VDD
VSS
AN3
VSS
1011
AN3
AN2
1100
AN3
AN2
1101
VREF
VREF
VREF
-
AN3
AN2
1110
VDD
VSS
1111
VREF
+
VREF
-
AN3
B mn K Thut My Tnh
A
VREF
+
VREF
+
VREF
+
VREF
+
80
VSS
Thc hnh Vi x l
Khoa KH & KTMT
8.2 Chng trnh mu

#include
radix
code
goto
p18f4520.inc
dec
0
start
udata
PRG
start
code
rcall
rcall
bra
init_A_D
A_D_isr
$
; Khoi dong A_D

; Doc bien doi A_D
;------ Chuong trinh cua A_D -------;

init_A_D
A_D_isr
movlw
movwf
movlw
movwf
movlw
movwf
call
bsf
return
b'00000100'
ADCON1
b'11000001'
ADCON0
0x01
ADCON2
delay100us
ADCON0,GO
; RA0,RA1,RA4 analog input
bsf
btfsc
bra
movff
return
ADCON0,GO
; Bat dau bien doi
ADCON0,GO
$-2
ADRESH,A_D_var
; Chon RC osc, AN0 input

; Cho phep A_D
; Giu cham > 15 cycles

; Bat dau bien doi A_D
8.3 Bi tp
+5V
R1
6
5
K
R2
RA
470
Tch hp module LCD, ly gi tr in th t bin tr hin th ln LCD.
B mn K Thut My Tnh
81
Thc hnh Vi x l
Bi 9 :
Khoa KH & KTMT
Kho st khi chc nng capture Mode
Ni dung:
Kho st khi chc nng CCP2/Timer3 capture mode .
Yu cu:
Vit chng trnh s dng chc nng capture mode o tn s v rng xung
ca mch giao ng 555.
9.1 Cc bc hin thc capture mode

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l capture
v chn chip 18f4520. Ta c hnh sau:
Bc 2. Include file p18f4520.inc vo file capture.asm.

Bc 3. Tch hp module LCD vo project capture, tham kho bi tp v LCD.
Bc 4. Khi to init_capture ta c th s dng capture mode d dng.
B mn K Thut My Tnh
82
Thc hnh Vi x l
TRISC
Khoa KH & KTMT
T3CON
CCP2CON
1 0
X X X X X X 1 X
If CCP2is assigned to RC1
TRISB
x X X X 1 X X x
If CCP2is assigned to RB3
1 0 0 1
P=1
0
1
1
1
0
1
P=2
P=4
P=8
CCPR2H
0 0 0 0 0 1
Timer3
prescaler
divider
0 Capture evey falling edge
1 Capture evey rising edge
0 Capture evey 4 rising edge
1 Capture evey 16 rising edge
th
th
Edge counter and

edge selsction
CCPR2L
CCP2 pin
Prescaler
Transfer
P
P = 1, 2, 4, or 8
TMR3L
TMR3H
Fosc/4
(internal clock)
Set
PIR2
X X Xx X X X X
Generate a high priority interupt
CCP2IF
Generate a low priority interupt
CCP2IE
PIE2
GIEH
X X Xx X X X X
GIEL
CPP2IP
X X X X X x
INTCON
RCON 1X X Xx X X X X x
IPR2 X X Xx X X X X
IPEN = 1 : Enable priority levels
Figure 9 CCP2/Timer3 capture mode

+5V
R
A
R8
6
B mn K Thut My Tnh
output
555
time
r
RC
1
2
0.1uF
83
Thc hnh Vi x l
Khoa KH & KTMT
Hnh 9-1: Tp thanh ghi s dng trong ch capture mode v mch giao ng 555
init_capture
clrf
bsf
movlw
movwf
movlw
movwf
bsf
bsf
bcf
movlw
movwf
movwf
bsf
bsf
bsf
return
capture_var
TRISC,RC1
0xb8
T3CON
0x05
CCP2CON
RCON,IPEN
IPR2,CCP2IP
PIR2,CCP2IF
0
TMR3H
TMR3L
T3CON,TMR3ON
PIE2,CCP2IE
INTCON,GIEH
; Nap capture_var = 0
; RC1 input
; Prescaler = 8
; Khoi dong T3CON
; Capture every ricing edge
; Khoi dong CCP2CON
; Enable priority level
; high level
; Xoa co ngat
; Nap bo dem
; Timer3 Bat dau dem
; Cho phep CCP2 ngat
khi to chc nng capture, u tin ta phi cu hnh cho PORTC1 l input. Tip
theo khi to h s chia Prescaler thng qua vic cu hnh thanh ghi T3CON. Sau ta
khi dng ch capture bng cch cu hnh thanh ghi CCP2CON v cc thanh ghi ngt.
9.2 Chng trnh mu

List
p=18f4520
#include
code
goto
org
goto
"p18f4520.inc"
0
start
08h
isr_high
udata
;------- Bien cho capture mode ---------;
decode_var
res
capture_var
res
thuong_so
res
so_bi_chia
res
so_chia
res
so_bcd
res
start
PRG
call
call
B mn K Thut My Tnh
1
1
3
3
3
3
code
init_lcd
init_capture
; Khoi dong LCD

; Khoi dong capture
84
Thc hnh Vi x l

bra
init_capture
clrf
bsf
movlw
movwf
movlw
movwf
bsf
bsf
bcf
movlw
movwf
movwf
bsf
bsf
bsf
return
Khoa KH & KTMT
capture_var
TRISC,RC1
0xb8
T3CON
0x05
CCP2CON
RCON,IPEN
IPR2,CCP2IP
PIR2,CCP2IF
0
TMR3H
TMR3L
T3CON,TMR3ON
PIE2,CCP2IE
INTCON,GIEH
; Nap capture_var = 0
; RC1 input
; Prescaler = 8
; Khoi dong T3CON
; Capture every ricing edge
; Khoi dong CCP2CON
; Enable priority level
; high level
; Xoa co ngat
; Nap bo dem
; Cho phep CCP2 ngat
capture_isr;---- Frequency = 1000000/(8 * N) -------;

bcf
PIR2,CCP2IF
bcf
T3CON,TMR3ON
tstfsz
capture_var
bra
cap1
setf
capture_var
clrf
TMR3L
clrf
TMR3H
bsf
T3CON,TMR3ON
return
cap 1 bcf
INTCON,GIEH
bcf
PIR2,CCP2IE
movff
CCPR2L,so_chia+2
movff
CCPR2H,so_chia+1
clrf
so_chia
movlw
0x48
movwf
so_bi_chia+2
movlw
0xe8
movwf
so_bi_chia+1
movlw
0x01
movwf
so_bi_chia
call
chia_24bit
call
hexa_to_bcd
movff
so_bcd,decode_var
swapf
decode_var
call
decode_ascii
call
lcd_print_char
movff
so_bcd,decode_var
call
decode_ascii
call
lcd_print_char
movff
so_bcd+1,decode_var
swapf
decode_var
call
decode_ascii
call
lcd_print_char
movff
so_bcd+1,decode_var
call
decode_ascii
call
lcd_print_char
movff
so_bcd+2,decode_var
swapf
decode_var
B mn K Thut My Tnh
85
; Xoa co ngat
; Dung dem Timer3
; Ngat lan 1
; = 0xff
; Xoa bo dem
; Cam ngat toan cuc cao

; Cam CCP2 ngat
; Nap so chia
; Nap so bi chia
; Little Endian
; Nap so bi chia
; Nap so bi chia
; 125000 : so dem
; Doi sang BCD
; Lay byte cao
; Xuat byte1 ra LCD
; Lay byte thap
; Xuat byte2 ra LCD
; Xuat du lieu+1 ra LCD
; Lay byte cao
; Xuat byte1 ra LCD
; Lay byte thap
; Xuat byte2 ra LCD
; Xuat du lieu+2 ra LCD
; Lay byte cao
Thc hnh Vi x l
Khoa KH & KTMT
call
call
movff
decode_ascii
lcd_print_char
so_bcd+2,decode_var

; Xuat byte1 ra LCD
; Lay byte thap
call
call
decode_ascii
lcd_print_char

; Xuat byte2 ra LCD
movlw
movwf
call
movlw
movwf
call
movlw
movwf
call
bra
''
char
lcd_print_char
'H'
char
lcd_print_char
'z'
char
lcd_print_char
$
isr_high
call
retfie
chia_24bit
clrf
clrf
clrf
tstfsz
bra
tstfsz
bra
tstfsz
bra
return
chia_24_1
movf
subwf
movf
subwfb
movf
subwfb
btfss
bra
incfsz
bra
incfsz
bra
incfsz
bra
chia_24_2
return
;
;
;
;
;
;
;
capture_isr
thuong_so+2
thuong_so+1
thuong_so
so_chia+2
chia_24_1
so_chia+1
chia_24_1
so_chia
chia_24_1
; Nap ket qua = 0
so_chia+2,w
so_bi_chia+2
so_chia+1,w
so_bi_chia+1
so_chia,w
so_bi_chia
STATUS,C
chia_24_2
thuong_so+2
chia_24_1
thuong_so+1
chia_24_1
thuong_so
chia_24_1
; Tru so bi chia cho so chia

; Little Endian
hexa_to_bcd
clrf
so_bcd+2
clrf
so_bcd+1
clrf
so_bcd
hexa2 tstfsz
thuong_so+2
bra
hexa5
tstfsz
thuong_so+1
bra
hexa3
tstfsz
thuong_so
bra
hexa4
return
hexa5 decf
thuong_so+2
bra
hexa1
hexa3 decf
thuong_so+1
B mn K Thut My Tnh
; Bo truong hop so_chia = 0
; So bi chia nho hon so chia

; Tang ket qua len 1
; Nap gia tri ban dau
86
Thc hnh Vi x l

setf
bra
hexa4 decf
setf
setf
hexa1 incf
movf
daw
movwf
tstfsz
bra
incf
movf
daw
movwf
tstfsz
bra
incf
movf
daw
movwf
bra
Khoa KH & KTMT
thuong_so+2
hexa1
thuong_so
thuong_so+1
thuong_so+2
so_bcd+2
so_bcd+2,w
so_bcd+2
so_bcd+2
hexa2
so_bcd+1
so_bcd+1,w
so_bcd+1
so_bcd+1
hexa2
so_bcd
so_bcd,w
so_bcd
hexa2
9.3 Bi tp
Vit chng trnh s dng chc nng capture mode o rng xung mc 1 ca
mch giao ng 555
B mn K Thut My Tnh
87
Thc hnh Vi x l
Khoa KH & KTMT
Bi 10 : Kho st cc khi chc nng PWM, LVD

Ni dung:
Kho st khi chc nng PWM.
Kho st khi chc nng LVD.
Yu cu:
Vit chng trnh s dng chc nng PWM iu khin sng ca LED.
Vit chng trnh s dng chc nng LVD a vi iu khin vo ch sleep
khi in p ngoi nh hn hay bng 4,03V.
10.1 Cc bc hin thc PWM

Bc 1. To project mi ging nh hng dn chng 1 ly tn project l pwm v
chn chip 18f4520. Ta c hnh sau:
Bc 2. Include file p18f4520.inc vo file pwm.asm.

Bc 3. Tch hp module LCD vo project pwm.
Bc 4. Khi to module PWM ta c th s dng mt cch d dng.
B mn K Thut My Tnh
88
Thc hnh Vi x l
Khoa KH & KTMT
470
RC2
J
9
RC2
BZI
R11
+
22
Valu
e
BUZZER- ASTI2 MLTRQ
Hnh 10-1 Cng xut tn hiu PWM

init_pwm
bcf
movlw
movwf
movlw
movwf
movff
bcf
bcf
movlw
movwf
movlw
movwf
return
TRISC,2
0x80
PR2
0x40
CCPR1L
CCPR1L,PWM_var
CCP1CON,CCP1X
CCP1CON,CCP1Y
0x05
T2CON
0x0f
CCP1CON
; RC2 output
; initialize PWM cycle
; Khoi dong PWM duty cycle
; Cho hien thi ra LCD
; bit 4
; bit 5
; postcale 1:1
; prescale 4, Timer2 ON
; turn buzzer on
khi to chc nng pwm, u tin ta phi cu hnh cho PORTC2 l output. Tip theo khi
to chu k ca PWM thng qua vic cu hnh thanh ghi PR2. Sau ta khi to duty cycle ca
xung pwm bng cch cu hnh thanh ghi CCPR1L.
10.2 Chng trnh mu

list
#include
p=18f4520
"p18f4520.inc"
org
bra
0x000000
start
udata
;------- Bien cho PWM ---------;
decode_var
res
PWM_var
res
start
call
call
movff
swapf
call
call
movff
call
call
goto
B mn K Thut My Tnh
; reset vector
1
1
init_lcd
init_pwm
PWM_var,decode_var
decode_var
decode_ascii
lcd_print_char
PWM_var,decode_var
decode_ascii
lcd_print_char
$
89
; Khoi dong LCD

; Lay byte cao
; Xuat byte1 ra LCD
; Lay byte thap
; Xuat byte2 ra LCD
Thc hnh Vi x l
Khoa KH & KTMT
10.3 Cc bc hin thc LVD

LVDCON
VDC
ON
1: Power up and enable LVD

circuitry
0:
Disable LVD circuitry
LVDE
N
Internal reference voltage stable flag
IRVS
T
1: 1.2 V reference is ready

0: 1.2 V reference is not ready
Threshold selection (lower threshold)
LVD
Reserved
0 0 0 0
0 0 0 1
0 0 1 0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1 0
1 0
11
1 1
0
1
0
1
2.0 V 2.12 V
2.2V 2.33 V
2.4 V 2.54 V
2.5 V 2.65 V
2.7V 2.86 V
2.8V 2.97 V
3.0 V 3.18 V
3.3 V 3.50 V
3.5 V 3.71 V
3.6V 3.82 V
3.8 V 4.03 V
4.0 V 4.24 V
4.2V 4.45 V
4.5 V 4.77 V
External input on RA5/LVDIN pin
VDD
LVD circuitry
VDD
VMUX
RA
RA5/LVDIN
Resistor ladder and
External
. input
pin
analog multiplexer
Select
Analog comparator
Set LVDIF IF V MUX < VIR
Clear LVDIF in software
LVDCON
RB
1.2V
internal
reference
VIR
set
5
PIR2
High-priority
interrupt
IPE2
PIE
2
TRISA
X X
X X X X X
LVDI
F
Set (for input) to use
LVDIF
external input
Low-priority
interrupt
GIEH
INTCON
INTCO
N
GIEL
X X X X X X
B mn K Thut My Tnh
PIE2 X X X X X
X X
RCON 1 X X X X X X X
RCO
N
90
LVDIP
X
X
X
X X
IPR2
X X
Thc hnh Vi x l
Khoa KH & KTMT
Bc 1. Ni RA5 vi RA0 dng jumper trn mch th nghim.

Bc 2. Vit chng trnh khi ng LVD
init_LVD
movlw
movwf
bsf
bsf
bsf
bsf
bcf
movlw
movwf
bsf
bsf
return
B'11111001'
ADCON1
TRISA,RA0
TRISA,RA5
RCON,IPEN
IPR2,LVDIP
PIR2,LVDIF
B'0011111'
LVDCON
PIE2,LVDIE
INTCON,GIEH
; AN0, AN5 Analog

; Port analog
; RA0 input
; RA5 input
; Cho phep uu tien
; Muc uu tien cao
; Xoa ngat LVD
; 1.2V Ready, Enable LVD
; 0 1,2 V
; Cho phep LVD
; ngat toan cuc cao = 1
Bc 3. Thc hin chng trnh chnh.

code
0
goto
org
goto
start
08h
isr_high
udata
PRG
start
LVD_isr
`
isr_high
call
movlw
movwf
call
movlw
movwf
call
movlw
movwf
call
movlw
movwf
call
rcall
bra
code
init_lcd
'L'
char
lcd_print_char
'V'
char
lcd_print_char
'D'
char
lcd_print_char
':'
char
lcd_print_char
init_LVD
$
; Khoi dong LCD

; Thuc day
bcf
bcf
movlw
movwf
call
bcf
sleep
bra
PIR2,LVDIF
INTCON,GIEH
'R'
char
lcd_print_char
PIE2,LVDIE
; Xoa ngat LVD

; ngat toan cuc cao = 0
; Phat hien LVD
call
retfie
LVD_isr
; Xuat byte2 ra LCD

; Thuc day
; Xuat byte2 ra LCD
; Thuc day
; Xuat byte2 ra LCD
; Thuc day
; Xuat byte2 ra LCD
; Khoi dong LVD
; Xuat ra LCD
; Cm LVD
10.4 Bi tp
a) Vit chng trnh xut ra LED 256 mc sng, thay i sau 1 giy v xut gi tr mc
sng ln LCD.
b) Vit chng trnh s dng chc nng LVD a vi iu khin vo ch sleep khi
in p ngoi nh hn hay bng 1,2V.
c) Sa chng trnh thc hin ngt LVD khi in p ngun nh hn 2,7V.
B mn K Thut My Tnh
91
Thc hnh Vi x l
Khoa KH & KTMT

TNVXLVDK V3 20-02-2014

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TNVXLVDK V3 20-02-2014

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I HC QUC GIA TP.

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Gii thiu MPLAB IDE v KIT PIC

Kit th nghim PICDEM 2 Plus c cc c im nh hnh sau :

cm DIP 18, 28 v 40 chn (c th cm 3 linh kin nhng ch dng 1 mi ln).

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

10. B dao ng (OSC) 4 MHz.

Chn Next ca s Welcome

Bc 3. Chn s hiu PIC cn s dng (PIC18F4520) ri bm Next:

Bc 4. Chn tool Microchip MPASM Toolsuite ti Active Toolsuite.

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Chn MPASM Assembler (mpasmwin.exe) ti Tollsuite Contents.

Click Next qua ca s k.

Chn th vin thng qua file .INC v .LKR thm vo project

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

C:\Program Files\Microchip\MPASM Suite\LKR\18f4520.lkr

Click Next s thy nh sau :

Click Finish. Ta s c mt project nh hnh sau:

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Bc 6. Thm file vo d n theo cc bc sau :

Chn header file ph hp vi PIC

Thc hin Save, t tn vi

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

;vung dinh nghia du lieu

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Nu thnh cng, ta s thy hnh sau:

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Mt thao tc cn lm gip ta c th dch chng trnh, np v chy t ng l vo

By gi ta c th dch, np v chy d n vi thao tc menu Project_|Build All (hoc

Nu thnh cng th chng trnh s c dch, np ra card PICDEM v chy ngay.

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Nu tht bi, xem thng tin bo li trong ca s Output khc phc v lm li t

T y ta c th m phng c chng trnh ca mnh mt cch d dng.

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

Bc 3. Khi debug th ta cng cn phi bit gi tr ca cc thanh ghi cng nh b nh

xem c gi tr ca cc thanh ghi SFR th ta chn View_|Special Function

Hay xem mt v thanh ghi m ta quan tm th c th dng Watch xem bng

Thc hnh Vi x l Vi iu khin

Trng H. Bch Khoa TP.HCM

Khoa KH & KTMT

1.5 Debug onchip dng Mplab ICD2.