library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multiplexor is
port (
a:
in std_logic_vector (3 downto 0);
seleccion: in std_logic_vector (1 downto 0);
salida:
out std_logic
);
end entity multiplexor;
architecture mux of multiplexor is
begin
process(a,seleccion)
begin
case seleccion is
when "00" =>
salida <=a(0);
when "01" =>
salida <=a(1);
when "10" =>
salida <=a(2);
when others =>
salida <=a(3);
end case;
end process;
end architecture mux;
--sergio ivan medina martinez