TABLE OF CONTENTS

Page No
List of Figures/Tables

Nomenclature

ABSTRACT

Chapter 1
1.1

Introduction

1.2

Objective of project

1.3

Organization of thesis

Chapter 2
2.1

Standard cell library development

2.2

Flow Diagram

2.3

Static CMOS logic

2.4

Topology Selection

2.4

CMOS Process at Glance

Chapter 3
3.1

Schematic

11

3.2

Layout Design

19

3.3

Layout Parasitic Extraction

25

Chapter 4
4.1

Process Corners

28

4.2

Timing Parameters

29

4.3

Power Characterization

31

Chapter 5
5.1

Script for Back Annotation

34

5.2

Script for Rise & Fall Capacitance

34

5.3

Script for Leakage Power

35

5.4

Script for Rise & Fall Power

35

5.5

Script for Timing

38

Chapter 6
6.1

Library Report Generation

43

6.2

Verifying the library

43

6.3

Modelling

44

CONCLUSION

45

FUTURE SCOPE

46

REFERENCES

47

APPENDIX

48