Low-Pass Sigma-Delta Modulators - Principles and Architectures

Low-Pass Sigma-Delta Modulators:
Principles and Architectures

Angel Rodrguez-Vzquez and Fernando Medeiro
IMSE
Instituto de Microelectrnica de Sevilla
(IMSE-CNM-CSIC)
Avda. Reina Mercedes s/n,
41012-Sevilla, SPAIN
Phone: +34 95 505 6666/6669
FAX: +34 95 505 6686
Escuela Superior de Ingenieros

Dpto. Electrnica y Electromagnetismo
Universidad de Sevilla
Camino de los Descubrimientos s/n,
41092-Sevilla, SPAIN
Phone: +34 954487377
email: angel@imse.cnm.es
Design of Embeddable Data Converters: Sigma-Delta Converters
Slide CoA 0
IMSE-
Design Group
Introduction
x
What is an Analog-to-Digital Converter?
Analog Signal
x
ADC
clock @
TS
xD
fS
Spatial Vector of Parallel Digital Signals

xD
Analog Voltage or Current x by a Dig-
ital Code x D Composed of N -Bits,
Electronic Circuit used to Represent an
b 1, b 2, b N .
TS
Signals are sampled prior to its digital

codification
xD
Temporal Vector of a Serial Digital Signal

0
0 1
TS
Slide CoA 1
t
IMSE-
Design Group
Introduction
Mixed-Signal Systems
Common substrate
System-on-Boards
PCB
Most Today Electronics Systems

are Mixed-Signal
System-on-Chip
(ASICs)
Monolithic circuit
Multi-Chip Module
Analog inputs
Speech
Images
Radiation
Sensor signals
............................
Analog outputs
Analog Part
parameters
calibration
programming
coded signals
timing
Audio
Video
Actuators
............................
Digital outputs
Digital inputs
Digital Part
Slide CoA 2
IMSE-
Design Group
Introduction
Why Monolithic Mixed-Signal Systems ?

Total System Production Cost is Reduced
High-Volume Production Cost of ICs is Smaller than that of PCBs
System Size is Reduced
Portable Systems
System Reliability is Enhanced

Quite Often Faults are Associated to the Interconnections
among PCB Components
Performance can be Enhanced

Analog Accuracy can be Enhanced through Digitally-Controlled Error Correction
Operation Speed can be Enhanced because Interconnection Parasitic Capacitances are Smaller
Power Consumption can be Reduced because Large Parasitic
Capacitances must not be Driven
Analog and Digital Subsystem Partitioning can be Optimized

Designs are Better Protected Against Copies and Reverse
Engineering
Slide CoA 3
IMSE-
Design Group
Introduction
Some Challenges in the Mixed-Signal ASIC Scenario
MICROELECTRONIC EVOLUTION BASICALLY DRIVEN BY DIGITAL

Reduced Sizes
Reduced Supply
Analog circuits should be designed in digital technologies

Reduced supply voltage, with large threshold voltages in MOS transistors
0.5m @ 3.3V @ V T 0.65V ; 0.25m @ 2.7V @ V T 0.65V

Reduced element set
Need to exploit all the functional features of the MOS Transistor

Poor matching and linearity for the critical analog components
Self-correction and calibration advisable

Poor characterization and modelling for the primitive components
Large substrate noise due to the proximity of noisy digital circuits

Lack of mature analog and mixed-mode design&test methodologies
Larger performance needed for new application fields
New converter architectures for increased speed and resolution
Architectures and circuits optimized for reduced power consumption
Slide CoA 4
IMSE-
Design Group
Introduction
y
Basic Implications of Analog-to-Digital Conversion

Sampling
Quantization
x
TS
Quantization Sets Accuracy
Sampling Sets Bandwidth
Basic Converter Specifications:

Resolution (Measured in Bits)
Speed (Measured in Hz)
There is a Trade-off between Resolution and Speed.

Slide CoA 5
IMSE-
Design Group
Introduction
Resolution-vs-Speed Trade-off in CMOS ADCs
Effective resolution (bits)
22
20
18
16
14
12
10
8
6
4
102
103
104
105
106
107
108
109
Digital output-rate (Sample/s)
(Low-Voltage)
(current mode)
Nyquist
Nyquist (Low-Voltage)
Resolution at Given Frequency

Improves 0.3 bits per year.
Slide CoA 6
IMSE-
Design Group
Introduction
Power/Resolution-vs-Speed Trade-off in CMOS ADCs

10-1
Power (W) / 2bit
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9 2
10
103
104
105
106
107
108
109
(Low-Voltage)
(current mode)
Nyquist
Nyquist (Low-Voltage)
Power ( W )
FOM = ------------------------------------------------------------------------- 1012
2 resolution ( bit ) DOR(S/s)
[Good96]
Slide CoA 7
IMSE-
Design Group
Introduction
Why are Sigma-Delta Converters Interesting?
They cover a wide region of the

resolution-frequency plane
They are well suited for mainstream CMOS VLSI technologies
because:
at the expense of more complicated digital circuitry.
They have good tolerances to

matching and other secondorder phenomena.
They simplify the requirements
placed on the anti-aliasing filters.
Sample-hold is not required.
.........
Effective resolution (bits)
they require relaxed analog circuitry performance,
22
(LV)
(CM)
Nyquist
Nyquist (LV)
20
18
16
14
12
10
8
6
4
102
103
104
105
106
107
108
109

Slide CoA 8
IMSE-
Design Group
Basic Concepts
Uniform Quantization
y
Quantizer Resolution:
Quantizer
Resolution:
B
B =
= log
log22 (( #
# Levels
Levels ))
Separation
SeparationBetween
BetweenInput
InputLevels:
Levels:
X
X FS
FS=
--------XXLSB
=
--------------LSB
BB
2 2 1
Separation
SeparationBetween
BetweenOutput
OutputLevels:
Levels:
Y
Y
=
-------------- = --------------B
22 B 11
X LSB
Quantizer
QuantizerGain
Gain:
X FS
Memoryless, Time-Invariant, Nonlinear Operation Consisting on Mapping

an Analog Input Signal onto a Set of
Discrete Output Values
Y 2B
G = -------------- = ---------- --------------X FS 2 B 1

X LSB
MidRise Quantizer: Output Transition at
Middle ofQuantizer:
Input Range
MidRise
Output Transition
at
Middle of
Input Range
MidTread
Quantizer:
Output Constant at
Middle of Input
Range Output Constant
MidTread
Quantizer:
at Middle of Input Range
Slide CoA 9
IMSE-
Design Group
Basic Concepts
Quantization Error and Overloading

1-bit Quantizer
y
+
eq
eq
3-bit Quantizer
eq
Overloading of Quantizer
eq
x
Overload
Overload
eq
X FS
Slide CoA 10
IMSE-
Design Group
Basic Concepts
Quantization Error Analysis

y = x + eq ( x )
The Quantization Error is Entirely
Dependent on the Input Signal
+
eq
[W. Bennett, 1948]

[B. Widrow, 1956]
[M. R. Gray, 1990], . . . . . . . . . . . . . . . .
Showed that
Errors Caused by Quantization
Produces Similar Effect as an
Independent Noise Source
When Many Quantization Levels
are Used
psd of the quantization error for a narrow

Eq ( )
band input signal
2
3
1
3
E q ( ) ----------------------- ----------- exp ----------------

3 B 1 2
3
8n 2 2
2
4
n = 1n
= f fB
[Engel99]
Slide CoA 11
= x rms
IMSE-
Design Group
Basic Concepts
Illustrating Quantization Errors I

eq
1/8Hz@0.5V Sine Signal with 3-bit Quantizer

e qLP
eq
Unfiltered

eq
eq
Low-Pass Filtered@1Hz
e qLP
e qLP
Unfiltered
Slide CoA 12
IMSE-
Design Group
Basic Concepts
Illustrating Quantization Errors II

eq
0.5V Uniform Random Signal@8Hz with 3-bit Quantizer

e qLP
eq
Unfiltered
0.5V Uniform Random Signal@8Hz with 1-bit Quantizer

eq
eq
e qLP
e qLP
Unfiltered
Slide CoA 13
IMSE-
Design Group
Basic Concepts
Quantization Error as an Additive Noise
Input Signal:
Non-overloading
y = x + eq( x )
Random
Band-Limited Characteristic Function
p ( eq )
eq
t
2
( eq ) =
2
2
( e q p ( e q ) ) de q = -----12
2
Quantization Error Signal:

White Noise (Random) Signal,
eq
Independendent of the Input

Signal
+
x
2
2
( e q ) = -----12
Uniformly Distributed in the

Interval [ 2, 2 ]
Slide CoA 14
IMSE-
Design Group
Basic Concepts
Non-Ideal Quantization: ADC Errors

YD
YD
Offset + Gain Error

DNL2
X LSB
5
X LSB
4
3
Offset
INL4
2
1
0
X FS
Offset and Gain Errors:

Deviation of the First Transition (Offset)
Deviation of the Last Transition (Gain)
X FS
Nonlinearity Errors:
Correct Offset and Gain Errors
Separation of Adjacent Transitions (DNL)
Deviations from Ideal Transitions (INL)
Slide CoA 15
IMSE-
Design Group
Basic Concepts
Non-Ideal Quantization: DAC Errors

x
Offset + Gain Error
INL4
yD
yD
DNLk
Offset
Offset and Gain Errors:
Nonlinearity Errors:
Deviation of the First Level (Offset)
Correct Offset and Gain Errors
Deviation of the Last Level (Gain)
Separation of Adjacent Levels (DNL)

Deviations from Ideal Levels (INL)
Slide CoA 16
IMSE-
Design Group
Basic Concepts
Non-ideal
Quantizer
Modelling and Effects of Non-Ideal Quantization

+
e qNI
Non Ideal Quantization Produces Extra Error
G ADC
y
G DAC
E osDAC
E osADC
ADC Errors
DAC Errors
Ideal Quantizer
eq
y = x + e q + e ADC + e DAC
e ADC
e DAC
+
YD
Slide CoA 17
IMSE-
Design Group
Basic Concepts
Sampling of Quantization Noise

S *q 2
Assuming that the quantization error is white noise

1 2
S *q = ------------- -----BW n 12
,f [ 0, BW n ]
f S 2f S 3f S 4f S BW n
n = 9
n = 1
The sampling process

makes the noise replicas n = 8
to fold and aliase into the
frequency band
n = 7
Sq
n = 2
n = 3
S *q [ f ( n f S ) ]
n =
Yielding the Power Spec- n = 1

tral Density of sampled
quantization noise
n = 9
Sq
2
1
S q = ------ -----f S 12
fS 2
fS 2
Slide CoA 18
IMSE-
Design Group
Basic Concepts
Sampling of Quantized Sinusoidal Signals
fS
( n 1 )T SnT S ( n + 1 )T S
The Spectrum of the Quantization Noise is Not Limited. Aliasing Appears
fB
fS
1Hz@0.5V Sine Signal with 2-bit Quantizer

eq
eq
All Error Power is Aliased into

f
S S
-, ----the band ------2 2
Whitening Increases as the

Sampling Frequency Increases
as Compared to the Signal Frequency
f S f B = 16
f S f B = 256
Slide CoA 19
IMSE-
Design Group
Basic Concepts
X
Illustrating Validity of Noise Power Calculation I

+
e qLP
Power
Estimation
e qLP
fB
eq

e qLP
2
e qLP
meas
e qLP
ideal
= 120
W
= 212
W
f S fB = 256
Power
Estimation
e qLP
f S f B = 16
eq
e qLP
2
e qLP
meas
e qLP
ideal
= 55
W
f S f B = 1024
meas
= 13
W
e qLP
e qLP
Slide CoA 20
ideal
= 55
W
= 3
W
IMSE-
Design Group
Basic Concepts
Illustrating Validity of Noise Power Calculation II

+
e qLP
eq
0.5V Uniform Random Signal with 1-bit Quantizer

e qLP
f S = 16Hz
e qLP
2
e qLP
f S = 256Hz
= 11mW
meas
e qLP
= 11mW
ideal
Power
Estimation
e qLP
Power
Estimation
eq
e qLP
2
e qLP
meas
e qLP
ideal
= 640
W
f S = 1024Hz
meas
= 650
W
e qLP
e qLP
Slide CoA 21
ideal
= 160
W
= 164
W
IMSE-
Design Group
Basic Concepts
X
SNR of Sampled, Quantized Signals

2 f
3
X
S
SNR = 10log 10 --- ------ -------2 2 2fB
Sampling
dB
clock @ f S
fB
2
fS B
X FS f S
3
3
SNR max = 10log 10 --- ---------- --------- = 10log 10 --- --------- ( 2 1 )
2 2f B
2 2 2f B
dB
SNR dB
1
fB
fS
-------2f B
SNRmax
Signal Power X
------
In-Band Noise Power
Pq =
2 2f B
S q ( f ) df =
------ -------12 f S
fB
fB
SNR 0dB
X mim
DR
Slide CoA 22
X
X FS
dBv
IMSE-
Design Group
Basic Concepts
Concept of Equivalent Number of Bits
N-bit Quantizer at Nyquist Rate

f S1 = 2f B f N
f B = fS1 2
B-bit Quantizer at Larger Rate

f S2 > f N
f S2 2
fB = f S1 2
using the N-bit Quantizer

2
3 N
SNR max = 10log 10 --- ( 2 1 )
2
dB
2
X FS
f S1
er P =
w
o
p
----=
-----------------------------------i se
q
o
2
n
12
f
B
d
n
12 ( 2 1 ) S2
in-ba
e power
is
o
n
.
t
n
a
qu
fB
Sine Signal Sampled at Nyquist Rate
X FS
r
e
w
P q = ------ = ----------------------------se p o
2
i
12
o
N
n
d
n
a
12
(
2
1
)
b
in2
f S2 2
fB
Sine Signal Sampled at Larger Rate

using a B-bit Quantizer
2
f S2 B
SNR max = 10log 10 3--- -------(2 1)
2 f S1
dB
SNRmax Measured and Univocal

SNR max 1.76
f S2
B
1
N ------------------------------------------- log 2 1 + --- log ------ 2
2
2 f S1
6.02
Slide CoA 23
valid only for

N large!!
IMSE-
Design Group
Basic Concepts
Performance Definitions: SNR and DR

0
Measure SNR
Ideally the range of x ends at
XFS
In practice its ends at lower
value of x, namely Overload
Input, XOL
In-band error power (dB)
Represent SNR as function of x
PSD x frequency bin (dB)
Filter
-25
-50
-80dB in-band
error power
-75
-100
-125
Overloading
SNRmax
-150
SNRpeak
SNR(dB)
Equivalent Number of Bits

N
SNR 0dB
X min
DR
N
X OL
SNR max 1.76
ideal
-------------------------------------------
6.02
SNR peak 1.76
actual
---------------------------------------------
6.02
X FS
Slide CoA 24
IMSE-
Design Group
Basic Concepts
Performance Definitions: Nonlinearities
Nonlinear Distortion increases the inband power error
Using a sine input

Ratio of signal power to the power of
noise plus harmonics
Amplitude (dBV)
-25
SNDR and SFDNR:
SFDR
-50
2nd har.
-75
3rd har.
-100
X 8
SNDR dB = 20log10 ------------------------------------------------------
noise + harmonics
-125
SFDNR (Spurious-Free Dynamic Range):
-150 0
Ratio between signal component and the

maximum distortion component
(IM)
and
Using two sine inputs at f1 and f2
IM3: Ratio between the carrier input power

and the power of distortion at 2f1f2 or
2f2f1
IP3:
IP 3 P x IM 3 2
dB
4e+05 6e+05 8e+05

Frequency (Hz)
1e+06
0
-20
Magnitude (dB)
Intermodulation Products
Intercept Points (IP):
2e+05
IM3 =-43 dB
-40
IM3 =-54 dB
-60
-80
-100
0.22
0.23
0.24
0.25
0.26
0.27
0.28
Frequency/Sampling Frequency
Slide CoA 25
IMSE-
Design Group
Noise Shaping
Ingredients of SDCs: Oversampling

Oversamplig means using a sampling frequency
larger than the Nyquist frequency
Oversampling Ratio
fS
M = -------2f B
Oversamplig reduces the Power of noise, and increases the SNR

2 1
Pq =
S q ( f ) df = ------ ----12 M
fB
2
B
SNR max = 10log 10 3--- M ( 2 1 )
2
fB
f S2 2
f S1 2
f B
f S1 2
fB
dB
f S2 2
Oversampling simplifies the design of the anti-aliasing filter
fB
f S1
f S2
Slide CoA 26
IMSE-
Design Group
Noise Shaping
What do you Gain by Oversampling?
SNR max = 1.76 + 20 log
10
(2
1 ) + 10 log
Quantizer
eq
eq
M = 8
2
e qLP
10
(M)
Oversamplig
eq
M = 128
= 11mW
2
e qLP
= 650
W
12dB
M = 512
e qLP = 164
W
18dB
Plain Oversampling Yields 3.01dB Everytime M is Doubled

M=65,536 is needed to Increase Resolution in around 8-bits
To obtain 12bit@10KHz by oversampling a 1-bit Quantizer, Samplig
Frequency must be around 340MHz !!
Slide CoA 27
IMSE-
Design Group
Noise Shaping
Ingredients of SDCs: Error Processing
Basic Idea
e qHP ( n ) = e q ( n ) e q ( n 1 )
To combine delayed (differentiated)

versions of the quantization error
At Low-Frequency (in-band) these
delayed versions practically coincide
By substracting then, low-frequency
error is cancelled
e qHP ( n ) = e q ( n ) + e q ( n 2 ) 2e q ( n 1 )
e qHP ( n ) = e q ( n ) + 3e q ( n 2 ) 3e q ( n 1 ) e q ( n 3 )
eq
N TF ( z ) =

eq
eq
L = 0
e qHP
eq
L = 1
1 L
(1 z )
L = 2
= 11mW f S = 16Hz e qHP

= 0.6mW
f S = 16Hz e qHP
meas
meas
= 65
W
f S = 16Hz e qHP
meas
Slide CoA 28
IMSE-
Design Group
Noise Shaping
Noise Shaping Concept I
In Frequency Domain, Error Correction Produces High-Pass Filtering of the Quantization

Noise
1 L
E qHP ( z ) = N TF ( z ) E q ( z ) = ( 1 z ) E q ( z )
z = e
f
j2
----fS
= e
1 f
j
----- ----M fB
max = ---The zeroes of N TF ( z ) at DC ( z = 1 = 0 ) proM
duce Attenuation of the error at Low-Frequencies

for .
max = ---M
Real ( z )
N TF ( )
On the other hand, at High-Frequencies, for

B < , the errors are Amplified.
The psd of this Shaped Noise is,
j
2L
2L
1 2
1 2 2L
S qHP ( ) = ----- ------ 1 e
= ----- ------ 2 sin ----
f S 12
f S 12
2
The In-Band Power of Quantization Noise is,

fB
2
2L
Pq =
S
( f ) df ------ ------------------------------------------ f B qHP
12 ( 2L + 1 )M 2L + 1
Slide CoA 29
IMSE-
Design Group
Noise Shaping
SNR
max
What do you Gain by Oversampling plus Noise Shaping?
= 1.76 + 20 log
2L + 1
2 B 1 + 10 log ( M ) + 20 L log ( M ) + 20 log -------------------
10
10
10
10
L
Quantizer
Plain Oversamplig
Noise Shaping
Plain Oversampling
Oversampling
Noise-Shaping
plus
SNR max
Add 3.01dB
per octave of M
M = 128
M = 64
M = 32
Add 3.01+6.02dB
per octave of M for L = 1
Offset = - 5.17dB
M = 16
M = 8
Add 3.01+12.04dB
Offset = - 12.89dB
M = 4
Add 3.01+18.06dB
Offset = - 21.37dB
L
Slide CoA 30
IMSE-
Design Group
Noise Shaping Implementation Through Error Feedback
Noise Shaping
Error must be shaped while the signal is transmitted

clock @ f S
eq
H(z)
[Cuttler, 1954]
YD
fB
DAC
y
Y ( z) = Eq ( z ) + U ( z ) = X ( z ) + [ 1 H ( z ) ] E q ( z )
S TF ( z ) = 1
Order of the filter is limited due to

Stability Problems. The system is
strongly nonlinear and dynamic
Transfer function for

Error
N TF ( z ) = 1 H ( z )
Errors of the Analog Substractors significantly degrades performance

Transfer function for

Signal
Slide CoA 31
IMSE-
Design Group
Noise Shaping
Oversampled Feedback Modulators

eq
clock @ fS
T( z)
e DAC
e ADC
+
u
YD
YD
Linear
Modeling
Quantizer
F( z)
DAC
y
of
Modeling Other Quantizer non-idealities as

additional errors
G T( z)
1
G T( z ) F( z) E
Y ( z ) = ----------------------------------------------X
( z ) + ---------------------------------------------( E q ( z ) + E ADC ( z ) ) ---------------------------------------------(z)
1 + G T (z ) F(z )
1 + G T (z ) F (z )
1 + G T ( z ) F ( z ) DAC
Delta Modulators
Interpolative Modulators
Sigma-Delta Modulators
G T ( z ) 1 in baseband
T ( z ) with large baseband gain
T ( z ) with large baseband gain
F ( z ) with large baseband gain
F ( z ) with large baseband gain
F ( z ) to unity
DAC Errors are amplified
DAC errors are amplified
DAC errors not amplified
Small quantizer input
Small quantizer input
Slide CoA 32
IMSE-
Design Group
Noise Shaping
Low-Pass and Band-Pass Modulators

clock @
fS
YD
T(z)
Combine Oversampling and Noise Shaping

improve the SNR by pushing the quantization noise outside the signal band,
The filtering can be either Continuous-Time
or Discrete-Time
F(z)
It is either Low-Pass or Band-Pass for the

input
DAC
It is either High-Pass or Band-Stop for the

quantization noise.
S TF ( z )
G T ( z ) = -----------------N TF ( z )
1 N TF ( z )
F ( z ) = --------------------------S TF ( z )
BandPass M
LowPass M
fS 2
f B
fB
Low-Pass to Band-Pass
Transformation, Among
Others
fS 2
fS 2
2f B
Slide CoA 33
fS 2
IMSE-
Design Group
Architectures
A/D Conversion Using Oversampled Modulators
Antialiasing filter
Modulator
Rough quantization
x sh
fS 2
Decimator
xa
H(z )
S/H
y
n
fN 2
Noise-shaping
Oversampling
D/A
yf( n )
fB fS 2
fS
yN ( n )
...
n
spurious
Digital processing
y(n)
...
X ( f ) antialiasing filter
Downsampling
Digital filter
x a ( t ), x sh ( t )
yN
yf
...
n
...
n
quantization error
with noise-shaping
Y(f)
Yf( f )
YN( f )
digital filter
X sh ( f )
...
fB fS 2
fS
f B fS 2
fS
fB fS 2
fS
Slide CoA 34
fB f N
fS
IMSE-
Design Group
Architectures
Getting Insight on Modulator Operation I

clock @
For Bounded Integrator Output,

YD
fS
The Averaged Integrator Input Must Be Null

1 T
u = lim --- ( g x g y ) dt = 0
T T 0
DAC
g
y = ------ x
g
[Inose, Tran. S. Elect. & Tel.1962]
Exemplary Waveforms
Zero Input
Positive Input
0
Negative Input
+ + + +
+ + + +
+
+ + + +
+
Caution!!! : Periodicity is a non-desirable feature happening for some inputs and some architectures
Slide CoA 35
IMSE-
Design Group
Architectures
Getting Insight on Modulator Operation II
Input Ramp with 128 samples per unit time

The output bounces
between adjacent levels
Local average tracks the
input
Differences are accumulated and self-corrected
clock @
YD
fS
DAC
Input Ramp with 32 samples per unit time

Same Observation as
Before
Slide CoA 36
IMSE-
Design Group
The 1st-Order 1-bit Modulator: Linear View
Architectures
eq
clock @
fS
u
Gain of the 1-bit Linear Quantizer Model

is an Arbitray Parameter
The 1-b quantizer is sensitive only to
the input sign
DAC
y
The Gain Value which yields unity gain of the

outermost loop is commonly used
1
Ggz
1z
Y ( z ) = X ( z ) ------------------------------------------ + E q ( z ) -----------------------------------------1
, 1
1
, 1
1 z + Gg z
1 z + Gg z
,
For Gg = 1 ,
g-z 1
S TF = ---,
g
YD
The value of G influences the calculation of in-band noise,

max
Pq = 2
min
2 2
1
---------------------------------------------------------- --------- d
j
j
24
1 + G T(e ) F(e )
The value can be estimated from,
N TF = 1 z
2
2 2
1
Ps +
---------------------------------------------------------- --------- d = -----
4
j
j
24
1 + G T ( e ) F ( e )
for P s = 0 .
Slide CoA 37
IMSE-
Design Group
The 2nd-Order 1-bit M: Genesis
Architectures
tio
ns
Starting from the Feedback Modulator Architecture

2
N TF ( z ) = ( 1 z 1 )
F ( z ) = 2z 1
clock @ f S
Af
te
rs
om
e
S TF ( z ) = z 2
ma
G T (z )
1
Y ( z ) = ----------------------------------------------X
( z ) + ----------------------------------------------E
(z)
1 + G T(z) F(z)
1 + G T( z ) F( z) q
nip
ula
z
G T ( z ) = -----------------------1 2
(1 z )
YD
y
DAC
G = 1
This structure requires large swing at the integrator output
Slide CoA 38
IMSE-
Design Group
Architectures
Illustrating the Problem of Stability

1st-order 1-bit SDM with g = g = 1
Stability Problems
u(n)
u(n)
Modulator States (Integrator

Ouputs)
are
large
or
unbounded
Overloading. If the quantizer
input u ( n ) is
X FS 2 B
u ( n ) > ---------- --------------- e q ( n ) > --2 2B 1

2
sine-input@X = X FS 2
sine-input@X = 5X FS 4
model not valid
2nd-order 1-bit Error-Feedback Modulator

Integrator Output Swing. If
y(n )
internal states are too large, y ( n )
integrator OS can be unfeasible.
Low-frequency,
large-amplitude oscillations are observed
sine-input@X = X FS
sine-input@X = 2X FS
Slide CoA 39
IMSE-
Design Group
The 2nd-Order 1-bit M: Scaled Version
Architectures
The Integrator Swing Problem is Alleviated through Signal Scaling

clock @ f S
g2
g1
x
g 1'
g 2'
YD
y
DAC
Using the quantizer gain value which

yields unity gain of the outermost
loop
1 G = ----------------g 1' g 2
The integrator gains must fulfill the

following condition to obtain the
ideal transfer functions,
g 2'
----------------- = 2
g 1' g 2
The input signal is scaled by g1 g 1'

g 1 2
S TF ( z ) = ------- z
g 1'
usually g 1 = g 1'
There are two degrees of freedom to control the output swing of the integrators
Overloading typically occurs at
X OL 0.8 X FS
Slide CoA 40
IMSE-
Design Group
Nonlinear Phenomenology: Generation of Patterns
Architectures
clock @
fS
P+ P y = ------------------E = x
P + + P- r
y
With DC excitations the output bounces

between two quantization levels keepins its
mean value equal to the input,
P + = number of positive pulses
DAC
P - = number of negative pulses
u(n) = u(n 1) + g (x y(n 1))
Take into account that u ( n ) y ( n ) = e q ( n ) and that

Assume E ref = 1, g = 1 , and take
y ( n ) = E r sgn ( u ( n ) )
e q ( 1 ) = 0
x=0
x = 1/3
x = 1/2
u(n)
y(n)
eq(n)
u(n)
y(n)
eq(n)
u(n)
y(n)
eq(n)
1/3
2/3
1/2
1/2
-1
-1
-1/3
-1
-2/3
-1/2
-1
-1/2
1/3
2/3
1/2
1/2
3
4
Slide CoA 41
IMSE-
Design Group
Noise Pattern: First Order 1-bit Modulator

Architectures
If the input x is a rational number such that x 1 , the output is periodic; and vice-versa,
P+ P y = ------------------- = Integer
------------------ = x
P + + PInteger
The period of the oscillatory movement depends on the input value.

For small inputs, the period is very large
The quantization error is also periodic, and hence it is not white noise.
The quantization error spectrum contains tones at sub-harmonics of the sampling frequency.
When the repetition frequency lies in the signal band the modulation is noisy.
If the input x
In-band quantization error
power (dB)
is an irrational number such that x 1 , the output is not periodic. However its
spectrum is discrete.
Some Properties of Pattern Noise
-40
Height and Width of each peak inversely proportional to M .
-45
Power in each peak inversely proportional to M .

Height and Width of each peak inversely proportional to the
3
-50
denominator of the fraction that describes the position of

the input within the corresponding quantization interval.
-55
-60
-65
2 2
------ ----------The average noise is given by P Q =
-70
About half of the total power is in the end peaks and 1 16 in
12 3M 3
-1 -0.8 -0.6 -0.4 -0.2
0.2 0.4 0.6 0.8
DC input level referred to /2
the center ones.
Slide CoA 42
IMSE-
Design Group
Architectures
Noise Pattern: 1st versus 2nd Order 1-bit Modulator
2nd Order M
In-band quantization noise power
(dB)
In-band quantization error

power (dB)
1st Order M
-40
-45
-50
-55
-60
-65
-70
-30
-40
-50
-60
-70
-80
-90
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

Slide CoA 43
IMSE-
Design Group
Illustrating Coefficient Selection for 2nd-Order 1-bit M
Architectures
They are selected by considering

different issues:
g1
Constraints on the Coefficients
g2
g 1'
g 2'
+E r
Maximum SNR peak:
D/A
Er
Available integrator output swing

SNR(dB)
Required integrator dynamic

Implementation considerations:
size and number of capacitors,
etc.
...
YD
SNRpeak
Overloading
X OL 0.8 X FS
for 2nd-Order SDM
SNR0dB
X min
DR
X OL X FS
Weight
[Bose,88]
[Yin,94]
[Marques, 97]
[Medeiro, 98]
g 1 , g 1'
0.5
0.25
1/3
0.25
g2
0.5
0.5
0.6
g 2'
0.5
0.25
0.4
0.5
Total int. OS / Er
3.5
2.4
# unitary caps.
10
12
Slide CoA 44
IMSE-
Design Group
High-Order Single-Loop Ms
Architectures
S TF ( z ) = z L
N TF ( z ) = ( 1
T(z )
2
2L
P q ------ ------------------------------------------12 ( 2L + 1 )M 2L + 1
Very large noise transfer function at highfrequencies
YD
F( z)
N TF = 2
DAC
Induces overloading and unstabilities

Forces reduction of amplitude
U ( z ) = S TF ( z ) X ( z ) + [ N TF ( z ) 1 ] E q ( z )
Tradeoff Stability-SNR
Analytical techniques are not available
for evaluation of the optimum noise
transfer function.
Describing function method
Root-locus using variable gain for

the quantizer (1-bit)
Forces modification of the noise transfer

function
N TF ( e )
clock @
L
z1 )
Very Strong Noise Shaping
fS
1 z1 )
N TF ( z ) = (-----------------------D( z)
Maximum Input
Rule of Thumb
j
N TF ( e ) < 1.5 or 2
Basically, simulations are employed

Simpler tradeoff as B increases
Relationship Between
N TF
Slide CoA 45
1 S q ( ) -----------------2
D( )
IMSE-
Design Group
Architectures
Distributed Feedback Topologies

clock @
z
---------------1
1z
g1
z
---------------1
1z
g2
g 1'
fS
z
---------------1
1z
g3
YD
g L'
g 2'
DAC
1 S TF ( z ) = ----------D( z)
( 1 z 1 ) N TF ( z ) = -----------------------D(z )
Butterworth approximation
Assuming g k = g k' , and 1-bit quantizer, g k' G = 2 for good fitting to the simulated psd
Increasing
k = 1, L
G gk' worsens the stability of the loop
Decreasing it worsens the SNR

Compromise value
k = 1, L
Difficult to stabilize
Significant SNR lost
Large power consumption
G g k' = 1, , 1 5, 1 25 . g k' increasing from the 1st to the last
[OptEynde, 1990] [Marques, 1998]
Some Experimental Prototypes

BW
FOM@Power
8KHz
100KHz
12
14
5@0.34mW(2V)
195@160mW(5V)
Third-Order
Third-Order
Slide CoA 46
[Au, 97]
[OptEynde, 91]
IMSE-
Design Group
Architectures
Alternative Single-Loop High-Order Topologies I
g1
clock @
g2
g 1'
fS
g1
g 2'
YD
g1
g 1'
g 1'
DAC
L2
( 1 z1 )
[ 1 ( 2 )z 1 + z 2 ]
N TF ( z ) = -------------------------------------------------------------------------------------------D(z)
Zeros at DC
Other zeros on the unity circle
Also feedforward inputs to integrators
clock @
g2
g2
g2
g2
fS
YD
DAC
Slide CoA 47
IMSE-
Design Group
Architectures
Interpolative Modulator Topologies

BL
..
.
B2
B1
AL
..
.
eq
A2
+
YD
A1
A0
D/A
[Lee & Sodini]
N TF
( z 1 )L Bi ( z 1 )L i
Ai ( z 1 )N i
i=1
i=0
= --------------------------------------------------------------------------------------------------------------------------- S TF = --------------------------------------------------------------------------------------------------------------------------L
L
L
L
z ( z 1 )L Bi ( z 1 )L i + Ai ( z 1 )L i
z ( z 1 ) L B i ( z 1 )L i + Ai ( z 1 )L i
i=1
i=0
i=1
Slide CoA 48
i=0
IMSE-
Design Group
Architectures
MultiBit Sigma Delta
Pros of MultiBit
Much smaller for same XFS

2
X FS 1
---------- ----12 f S
1-bit
2
X FS
Pq =
------ = --------12
12
B-bits
X FS
P q = ------ = ----------------------------2
12
B
12 ( 2 1 )
X FS
1
-------------------------- ----B
12 ( 2 1 ) fS
SNR improves 6.02 x B

Better stability, i.e., smaller SNR
degradation
Better fitting to the white noise
error model
Counters of MultiBit
DAC errors appear at the modulator input
Produces extra noise and distortion
e ADC
eq
x
G (z )
u
G
YD
e DAC
DAC must have the same accuracy as the overall modulator
2
2 2
e DAC 1--- ( INL
)
LSB
2
Slide CoA 49
IMSE-
Design Group
Architectures
Common Quantizer Architecture

B
2 Unity Elements
Parallel Bank of
Comparators
Unit Elements
Thermometer
Unit Elements
type
decoder
Digital
Input
Unit Elements
Unit Elements
ADC
DAC
Unit Elements
Equal-valued resistors, capacitors or transistor current sources
Mismatching of elements determines the DAC nonlinearity
U
y
1
------- = -------------- ----------e-
y
U
B
2 2 e
U
----------e- unit element error
Ue
Error Correction Needed

Trimming
Calibration
Others
Slide CoA 50
IMSE-
Design Group
Architectures
Dynamic Element Matching (DEM)
Convert the Static DAC Error into Wideband Noise

B
2 Unity Elements
Unit Elements
Thermometer
type
Shuffler
Unit Elements
decoder
Digital
Input
Unit Elements
Unit Elements
For each input code, select different unit elements at different times
Random Selection:
Convert the mismatch error into unshaped white noise
Conceptually simple implementation
Algorithmic Selection:
Reduce the in-band power of mismatch error
Different Algorithms: CLA, ILA, DWA, . . .
Noise-Shaping DEM:
Second-order LowPass or BandPass shaping of mismatch error
Slide CoA 51
IMSE-
Design Group
Architectures
Dynamic Element Matching (DEM)
Dynamic Element Rotation Barrel Shifter (CLA) [Leung, 92]:

The shuffler consists of a register and a counter
Makes the mismatch error a periodic signal. Frequencies around: f s 2 k f in
B
Condition to avoid baseband tones: M > ( 1 + 2 )2
B1
Individual Level Averaging (ILA) [Chen, 95]:

Guarantees that each element is used with equal probability per digital code
Makes a first-order noise shaping of the mismatch error
Data Weighted Averaging Techniques (DWA) [Henderson, 96]:
Similar to previous one
Makes a first-order noise shaping of the mismatch error
General Mismatch-Shaping DAC [Schreier, 95]:
Incorporates a filter into the element selection logic: high-order shaping
Suitable for low-pass and bandpass
Very complicated hardware. Can be simplified using tree-structures
(TNSDEM) [Yasuda, 97]
Slide CoA 52
IMSE-
Design Group
Architectures
Digital Correction Techniques
Makes a a posteriori Correction of the Output in Digital Domain
output
Multibit
Digital
Correction
(RAM)
M
M
Decimation
Filter
Data Stored in RAM:

Accurate digital equivalents of actual DAC outputs
Resolution of the RAM equal to overall resolution of the sigma-delta
Calibration needed
N bit
DAC
RAM
Data in
G(z)
Address
Up/Down
Counter
N-bit counter
Slide CoA 53
IMSE-
Design Group
Architectures
Cascade Topologies: The Concept

clock @
G1 T1 ( z )
Y ( z ) = --------------------------------------------- X( z) +
1 + G 1 T 1 ( z )F 1 ( z )
fS
Y 1D
T1( z )
y1
F1( z )
H ( z )G 2 T 2 ( z )
---------------------------------------------E (z ) +
1 + G 2 T 2 ( z )F 2 ( z ) q1
H(z )
---------------------------------------------- E q2 ( z )
1 + G 2 T 2 ( z )F 2 ( z )
DAC
The Terms in Eq2 Cancel out if,

H(z )
clock @
G 1 T1 ( z )
S TF ( z ) = --------------------------------------------1 + G 1 T 1 ( z )F 1 ( z )
fS
Y 2D
T2( z )
H ( z )G 2 T 2 ( z )
1
--------------------------------------------- = --------------------------------------------1 + G 1 T 1 ( z )F 1 ( z )
1 + G 2 T 2 ( z )F 2 ( z )
Then:
e q1
YD
1
+ ---------------------------------------------E (z ) +
1 + G 1 T 1 ( z )F 1 ( z ) q1
H(z)
N TF ( z ) = ---------------------------------------------1 + G 2 T 2 ( z )F 2 ( z )
For First Order,
H(z ) = 1 z
F2 ( z )
y2
DAC
N TF ( z ) = ( 1 z 1 )
by adding a delay to
Slide CoA 54
Y 1D
IMSE-
Design Group
Architectures
Dual Quantization
clock @
G(z)
fS
YD
1-bit
ADC
1b
H1( z )
YD
1-bit
DAC
clock @
fS
YD
B-bit
ADC
YD
YD
Bb
1b
Bb
H2( z )
= S TF X + N TF E q1
Y D = S TF ( H 1 + H 2 ) x + ( H 1 N TF + H 2 N TF H 2 ) E q1 + H 2 E qB
= U + E qB = Y D
E q1 + E qB
1b
H 1 = 1 N TF
[Leslie, 92]
H2 = N TF
Y D = S TF x + N TF E qB
Slide CoA 55
IMSE-
Design Group
Architectures
L
x
Modulator Topology:
q1
1-bit
1D
Eq2
2
L
1-bit
2D
X3
. .
.
E qN
B-bit Y N D
Q
LN
CANCELLATION LOGIC
Cascade Topologies
Li
YD
-------------B
2 1
L = L 1 + L2 + + LN
1st- and 2nd-order Ms

to ensure stability
single-bit quantizers
in all but last stage
multi-bit quantizer
only in last stage
multi-bit DAC non-linearity

attenuated by previous stages
After Cancellation Logic:

Y(z ) = z
( L LN )
1 L
1
X ( z ) + d ( 1 z ) E qN ( z ) d ( 1 z )
ED ( z )
Signal
Lth-order shaping in
last-stage quantization error
(L-LN)th-order shaping in
last-stage DAC error
Slide CoA 56
IMSE-
Design Group
Architectures
Cascade Topologies: 2-12mb

Cancellation Constraints
g1
g '
1
Eq1
g2
g '
2
Y1D
H1(z)
Analog
Digital/Analog
Digital
g 1' = g 1
g3'
d 0 = 1 -------------------g1 g2 g3
H1 ( z ) = z 1
g 2' = 2g 1'g 2
g 3''
d 1 = -------------------g1 g2 g3
H2 ( z ) = ( 1 z 1 ) 2
g 4' = g 3''g 4
d2 = 0
H 3 ( z ) = z 1
g 4''
d 3 = --------------------------g1 g2 g3 g4
H4 ( z ) = ( 1 z 1 ) 3
DAC
Eq2
g3
g '
3
d0
Y2D
g 3''
d1
H2(z)
DAC
g '
4
g ''
4
H3(z)
Eq3
g4
ED
d2
B-bit
ADC
B-bit
DAC
Y3D
B
d3
H4(z)
+
YD
Cancellation Logic
Y ( z ) = z 4 X ( z ) + d 3 ( 1 z 1 ) 4 E q3 ( z ) d 3 ( 1 z 1 ) 3 E D ( z )
1 2
q = ------ -----------------
12 B
2 1
2
2
1 2 INL 2
D = --- ----------
2
100
4-th Filtering of Quantization Noise

3-th Filtering of Nonlinearity
Error
Sensitive to Mismatch
8
6
2 2
2
P q = d 3 q ----------- + D -----------
9
7
9M
7M
Slide CoA 57
IMSE-
Design Group
Architectures
x
g1
g '
1
g2
Cascade Topologies: 2-13mb

Eq1
g '
2
Cancellation Constraints
Y1
H1(z)
Analog
Digital/Analog
Digital
g 1' = g 1
g 3'
d 0 = 1 -------------------g1 g2 g3
H1 ( z ) = z 1
g 2' = 2g 1'g 2
g 3''
d 1 = -------------------g1 g2 g 3
H2 ( z ) = ( 1 z 1 ) 2
g 4' = g 3''g 4
d2 = 0
H 3 ( z ) = z 1
g 5' = g 4''g 5
g 4''
d 3 = --------------------------g1 g2 g 3 g 4
H4 ( z ) = ( 1 z 1 ) 3
d4 = 0
H5 ( z ) = z 1
DAC
g3
g '
3
g ''
Eq2
d0
Y2
d1
+ H2(z) +
DAC
g4
g '
4
g ''
Eq3
d2
Y3
DAC
g5
g '
5
g ''
5
+ H4(z)
g 5''
d 5 = ---------------------------------- H6 ( z ) = ( 1 z 1 ) 4
g 1 g2 g3 g 4 g 5
H5(z)
Eq4
B-bit
ADC
ED
B-bit
DAC
d3
H3(z)
d4
Y4
B
d5 + H6(z)
Cancellation Logic
Y ( z ) = z 5 X ( z ) + d 5 ( 1 z 1 ) 5 E q4 ( z ) d 5 ( 1 z 1 ) 4 E D ( z )
2
1 2
q = ------ -----------------
12 B
2 1
2
2
1 2
D = --- INL
--------2 100
4-th Filtering of Quantization Noise

3-th Filtering of Nonlinearity
Error
Sensitive to Mismatch
8
8
2 2
2
P q = d 5 q ----------------- + D -----------
9
11M 11
9M
Slide CoA 58
IMSE-
Design Group
Architectures
Cascade Topologies: Integrator Weight Optimization
They are selected by considering

Cancellation constraints
Minimum SNR degradation:
Transferred signal must be scaled to avoid overloading.
Digital coefficients amplifying the last-stage quantization error must be minimized.
P
2
2 1 mb
8
6
2 2
2
= d 3 q ----------- + D -----------
9
7
9M
7M
2 2
2
= d 5 q ---------------- + D ----------
11
9
10
2 1 mb
11M
9M
Other Practical Considerations:

Integrator output swing must be achievable.
Digital coefficients should be 0, 1 or multiple of 2.
Multi-bit quantizer gain should be not too large.
The number of integrator branches and unitary capacitors must be minimum
2-12mb M
2-13mb M
g1
0.25
g3
g4
d0
-1
g1 0.25 g3
g1 0.25 g3
g1
0.25
g3
0.5
g4
d1
g2
g2
g3
0.5
g4
d2
g2 0.5
g2
0.5
d3
g3
g4
g5
d0
-1
g4 0.5 g5
d1
g4 0.5 g5
d2
d3
d4
d5
Slide CoA 59
0.5
IMSE-
Design Group
Other Cascade-Like Topologies: -Pipeline
Architectures
V in +
16
5b
DAC
5b
DAC
5b
DAC
3b
3b
DAC DAC
3b
3b
DAC DAC
5b
DAC
4b
DAC
PIPELINE CORRECTION LOGIC
SHUFFLE
M out
8 LSBs
LSB
Differentiator
C out
[Brook, 97]
Slide CoA 60
IMSE-
Design Group
Architectures
Examples of Experimental CMOS Prototypes I
High-Order, Single-Loop
BW
Power
Type
[Kasha 98]
400Hz
20bit
16mW (5V)
4th order FF + 1 resonator
[Rito, 91]
24kHz
16
200mW (5V)
[Welland, 89]
24kHz
16
450mW (10V)
[Adams, 91]
24kHz
18
1100 mW (10V)
5th order FF + 2 resonators
[Sau, 95]
24kHz
15
1mW (2.6V)
FB + FF input + 1 resonator
Slide CoA 61
IMSE-
Design Group
Architectures
Examples of Experimental CMOS Prototypes II
Multi-Bit
BW
N, bits
Power
DAC Non-Linearity Correction

Technique
[Nys, 96]
400Hz
19
2.7mW (5V)
DWA
2nd / 3b
[Yasuda, 98]
100kHz
12.8
14.8 mW (2.7V)
TNSDEM
3rd / 3b
[Sarhang, 93]
20.5kHz
16
Digital Correction
2nd / 4b
[Baird, 96]
500kHz
14
58 mW (5V)
Digital Calibration
4th / 4b
2nd / 3b
Order /
Number of bit
[Fattaruso, 93]
24kHz
15
100mW (5V)
Self-calibration &
random dynamic
matching
[Chen, 95]
20kHz
16
67.5mW (5V)
ILA
2nd / 3b
[Fongleman, 00]
24kHz
16
66mW (5V)
Mismatching Shaping Digital Encoder
2nd / 33 levels
[Vink, 98]
5MHz
1MHz
6.8
10
60mW (5V)
No Calibration
2nd / 5b
[Fuji, 00]
2.5MHz
15
270mW (5V)
Bi-directional DWA
2-1-1 / 4b
[Geert, 00]
2.5MHz
16
295mW (5V)
Speed-optimized
DWA
3rd / 4b
Slide CoA 62
IMSE-
Design Group
Architectures
Examples of Experimental CMOS Prototypes III
Cascade
N, bits
DOR (MS/s)
Process / Supply
Power (mW)
Topology
[Geerts00]
15.8
2.5
0.65m DP (5V)
295
3rd-order single-loop M
[Fujimori00]
15.0
2.5
0.5m DP (5V)
105
2-1-1 multi-bit cascade M
[Paul99]
12.0
18.0
1.2m DP (5V)
324
pipeline / oversampling
[Paul99]
10.7
30.0
0.6m DP (5V)
230
[Geerts99]
15.0
2.2
0.5m DP (3.3V)
200
2-1-1 cascade M
[Medeiro99]
13.0
2.2
0.7m P-diff. caps (5V)
55
2-1-1 multi-bit cascade M
[Feldman98]
13.0
1.4
0.7m DP (3.3V)
81
2-2-2 cascade M
[Marques98]
14.8
2.0
1m DP (5V)
230
2-1-1 cascade M
[Brooks97]
14.5
2.5
0.6m DP (5V)
550*
Slide CoA 63
IMSE-
Design Group

Low-Pass Sigma-Delta Modulators - Principles and Architectures

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Low-Pass Sigma-Delta Modulators - Principles and Architectures

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Low-Pass Sigma-Delta Modulators:

Principles and Architectures

Escuela Superior de Ingenieros

Design of Embeddable Data Converters: Sigma-Delta Converters

What is an Analog-to-Digital Converter?

Spatial Vector of Parallel Digital Signals

Analog Voltage or Current x by a Dig-

ital Code x D Composed of N -Bits,

Electronic Circuit used to Represent an

Signals are sampled prior to its digital

Temporal Vector of a Serial Digital Signal

Most Today Electronics Systems

Why Monolithic Mixed-Signal Systems ?

System Size is Reduced

System Reliability is Enhanced

Performance can be Enhanced

Analog and Digital Subsystem Partitioning can be Optimized

Some Challenges in the Mixed-Signal ASIC Scenario

MICROELECTRONIC EVOLUTION BASICALLY DRIVEN BY DIGITAL

Analog circuits should be designed in digital technologies

0.5m @ 3.3V @ V T 0.65V ; 0.25m @ 2.7V @ V T 0.65V

Need to exploit all the functional features of the MOS Transistor

Self-correction and calibration advisable

Large substrate noise due to the proximity of noisy digital circuits

Basic Implications of Analog-to-Digital Conversion

Quantization Sets Accuracy

Sampling Sets Bandwidth

Basic Converter Specifications:

There is a Trade-off between Resolution and Speed.

Resolution-vs-Speed Trade-off in CMOS ADCs

Effective resolution (bits)

Digital output-rate (Sample/s)

Design of Embeddable Data Converters: Sigma-Delta Converters

Resolution at Given Frequency

Power/Resolution-vs-Speed Trade-off in CMOS ADCs

Power (W) / 2bit

Digital output-rate (Sample/s)

Design of Embeddable Data Converters: Sigma-Delta Converters

Why are Sigma-Delta Converters Interesting?

They cover a wide region of the

at the expense of more complicated digital circuitry.

They have good tolerances to

Effective resolution (bits)

they require relaxed analog circuitry performance,

Digital output-rate (Sample/s)

Memoryless, Time-Invariant, Nonlinear Operation Consisting on Mapping

G = -------------- = ---------- --------------X FS 2 B 1

Quantization Error and Overloading

Design of Embeddable Data Converters: Sigma-Delta Converters

Quantization Error Analysis

The Quantization Error is Entirely

Dependent on the Input Signal

[W. Bennett, 1948]

psd of the quantization error for a narrow

band input signal

E q ( ) ----------------------- ----------- exp ----------------

Illustrating Quantization Errors I

1/8Hz@0.5V Sine Signal with 3-bit Quantizer

1/8Hz@0.5V Sine Signal with 1-bit Quantizer

Illustrating Quantization Errors II

0.5V Uniform Random Signal@8Hz with 3-bit Quantizer

0.5V Uniform Random Signal@8Hz with 1-bit Quantizer

Quantization Error as an Additive Noise