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    Instruction Set Summary

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    9 views5 pages

    Instruction Set Summary

    Uploaded by

    Vishal Gudla Nagraj
    Instruction Set Summary

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 5
    Amet Complete Instruction Set Summary Notes: 1 2 Not all instructions are available in all devices, Refer to the device specific instruction summary. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. For LD, ST, LDS, STS, PUSH, POP. add one cycle plus one cycle for each wait state. For CALL, ICALL, EICALL, RCALL, RET, RET in devices with 16 bit PC, add three cycles plus two cycles for each wait state. For CALL, ICAL, EICALL, RCALL, RET, RETI in devices with 22 bit PC, add five cycles plus three cycles for each walt state, Instruction Set Summary Mnemonics | Operands | Description Operation Flags #Glock Note ‘Arithmetic and Logie Instructions ‘ADD Ra, Rr__| Add without Carry Rd < Rd+ Rr ZCNNSH | 1 ‘ADC Ra, Rr__| Add with Carry Rd Rd+Rr+O Z.CNNSH | 1 ADIW Rd, K___| Add Immediate to Word Rae tiRd < RavtRa + K ZoNvSs | 2 SUB Ra, Rr__[ Subtract without Carry Rd © Rd- Rr ZCNNSH | 1 sus! Ra, K Subtract Immediate Rd Rd-K ZONNSH | 1 SBC Ra, Rr__| Subtract with Carry Rd © Rd-Rr-C Z.CNNSH | 1 scl Ra, K | Subtract Immediate with Carry | Rd Rd-K-C Z.CNVSH | 1 saw Ra. K | Subtract Immediate from Word | Rds t:Rd< Ravt:Rd- ZoNvs | 2 ‘AND Ra. Rr__| Logical AND Rd @ Ade Rr ZNvs [1 ‘ANDI Ra, K Logical AND with Immediate Rd RdeK 1 OR Ra Rr__| Logical OR Rd < Rdv Rr 1 ORI Ra K Logical OR with Immediate Rd RdvK 1 EOR’ Ra, Rr__| Exclusive OR Rd < Rd Rr 1 com Ra ‘One's Complement Rd $FF-Rd 1 NEG) Rd ‘Two's Complement Rd < $00- Ra ZCNVSH [1 SBR Rak ‘Set Bi(s) in Register Rd @ RdvK ZNVS [1 car Rak Clear Bit{s) in Register| Ra «Rd (SFFH- K) ZNvs [1 INC Ra Increment Rd R= ZNvs [1 DEC. Ra Decrement Rd Rd- znvs | t TST Ra Test for Zero or Minus Rd Ade Rd ZNvs [1 LR Rd Clear Register Rd Rds Ra ZNvs [1 SER Rd ‘Sot Register Rd c $F None 1 MUL. Rar | Muliply Unsigned RIsRO & Rad Rr (UU) Ze 2 MULS: Rar | Mutiply Signed RUsRO < Rx Rr (SS) Zc 2 MULSU [Rar | Multiply Signed with Unsigned | RYRO Rd Rr (SU) Ze 2 FMUL_ Ra\Ar___| Fractional Multiply Unsigned RU:RO @ (Rd x Rr)<

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