dce

2009

Thit k mch s dng HDL

Chng 3: Thit k mch lunl
tun t

Co
omputer Eng
ginee
ering
g 200
09

Ni dung chnh

Cc phn t lu tr
Fli Fl
Flip-Flop
g thi
Bus v cc thit b ba trng
Thit k my tun t
th bin i trng thi (State
(StateTransaction Graph)
B chuyn
h m
ni
i ti
tip cho
h vic
i truyn
t d
liu (Serial-line code converter)
Rt gn trng v cc trng thi tng
g
ng
Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Ni dung chnh

Cc phn t lu tr
Fli Fl
Flip-Flop
g thi
Bus v cc thit b ba trng
Thit k my tun t
th bin i trng thi (State
(StateTransaction Graph)
B chuyn
h m
ni
i ti
tip cho
h vic
i truyn
t d
liu (Serial-line code converter)
Rt gn trng v cc trng thi tng
g
ng
Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Mch tun t
Ng ra thi im t ph
thuc vo ng vo ti thi
im t v lch s ng
vo trc
Cn nhng phn t lu
tr li cc trng thi qu
kh ca mch
Mch tun t c th l
nh
n
h h
hay xc
sut,
t
ng b hay bt ng b
Cc phn mm tng hp
hin ch h tr ng b
(synchronous)
Advanced Digital Design with the Verilog HDL chapter 3

a
b
c

y1
1
Sequential

y2

Circuit

y3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Cc phn t b nh (Storage elements)

Lu tr thng tin di dng nh phn
Level sensitive
Latches
Ng ra ca mch thay i ngay khi mt hay
nhiu ng vo thay i (tn hiu enable tch
cc)

Edge
Ed sensitive
iti
Flip-Flop
Ng ra ca mch ch thay i khi c tn hiu
ng b
Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Latches

S1

R1

Qnext

Qnext

S2

R2

Qnext

Qnext

Hold

Not allowed

Reset

Set

Set

Reset

Not allowed

Hold

Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Latches trong sut (D-latch)

D liu ng ra ch thay i theo ng vo
khi llatch
t h c

php
h h
hott ng
(enable)
(
bl )
Clocked Latch

Enable = 0, Hold state

Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

D-latch

Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Ni dung chnh

Cc phn t lu tr
Fli Fl
Flip-Flop
g thi
Bus v cc thit b ba trng
Thit k my tun t
th bin i trng thi (State
(StateTransaction Graph)
B chuyn
h m
ni
i ti
tip cho
h vic
i truyn
t d
liu (Serial-line code converter)
Rt gn trng v cc trng thi tng
g
ng
Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

Co
omputer Eng
ginee
ering
g 200
09

Flip-Flop
Hot ng ng b vi cnh ln hoc
xung
ca
xung clock
l k

D FF
Master-slave FF
J-K FF
T FF

Advanced Digital Design with the Verilog HDL chapter 3

2009, Pham Quoc Cuong

10