@.0.0_0-8_0-0-6-0-0-0-0-0-0-0-8-0-0- 8 0-88 6 8 Oo '8 This chapter first discusses data jitter and clock jitter definitions and their roles in synchronized compiiter systems and asynchronized communication systems. “Then it discusses the definitions of various kinds of jiter, such as phase jiver, period fitter, and eycle-to-cycle jitter, as well as their interrelationships using the uniform nature of a clock signal waveform. Last, this chapter covers clock jitter and its relationship with phase noise, including the conversion from phase jitter to phase noise end vice versa. CLOCK JITTER Clock is widely used in modern electronics, from computers, to communications, to consumer electronics. 1n a computer systern, clock is used to provide timing or synchronization for the system. In a communication system, clock is used to specify when a data switch or bit transaction should be transmitted and received. Ina synchronized system, u central global clock is distributed to its subsystems. Tn acommunication system, particularly an asynchronized system, a clock can be either recovered or forwarded. Clearly, timing accuracy degradation in a clock 185186 Jitter, Noise, and Signal Integrity at High Speed affects the performance of the system it resides in. This chapter focuses on the single most imiportant degrader of clock performance: clock jitter. ‘We start with clock jitter definition and then move {o its impact on synchro- nized and aiyecluoaized systems in a quantitative manner. 7.14 Clock Jitter Definition From a sigrial or waveform point of view, clock signal or waveform is a special caée of a data signal, or waveform because the clock signal has a uniform transi- tion distribution and repeats at its minimam period. Assuming that the clock sig- nal ovet one period is represented by f(@), we have f= fexnTy Equation 7.4 where T is the period of the clock signal and n is an integer, Because clock signal is a special form of the general data signal, most of definitions of data jitter apply to clock jitter, such as DJ and RJ. However, some of the subcomponents of DJ for 2 data signal do not apply to clock jitter. The ISI does not apply to a clock signal because thore is no uneven transition for a clock of signal or waveform. The rest of the jitter components that wete introduced for a data signal in the previous chapters still apply to a clock signal. ‘The unique characteristic of uniform edge transition for a clock signal deter- tines its jitter root-canse mechanisms, as well as its measurement metrics. Figuer 7.1 shows clock jitter in reference to its ideal edge transitions. t ‘ i 1 2 3 Figure 7.4 A jittory clock signal with its reference voltage/power crossing times shown. 9 For a clock signal, an edge transition is expected to occur at every period. Tt petits a uniforin sampling for the clock jitter record, facilitating a direct Fourier ‘Transformation (FT) or Fast Fourier Transformation (FFT)! for jiter spectram analysis. There’s no need to “fill” the holes because of nonuniform sampling, as in tha case of data pattern signal, where edge transitions do not. occur evenly.FA Clock Jitter 187 In general, the jitter analysis method developed for a data signal can be applied to clock signal analysis equally well because it is a special case. But the opposite is not necessarily true. For example, FFT can be applied t9 clock jitter directly but cannot be applied to data jitter unless missing data holes have been filled (see Chapter 6, “Jitter and Noise Separation and Analysis in the Time and Frequeacy Domains”). Clock jitter analysis is subject to fewer sampling, con- straints compated to data signal jitter; therefore, more direct and vetsatiie meth- ods are possible for clock jitter analysis. in another example, clock jitter canbe measuied and analyzed by time-domain instruments such as time interval ana- lyzer (TIA) or sampling oscillascope (OS), and frequency-domain measurement instruments such as spectrum analyzer (SA).? However, in practice, data jitter has been measured and analyzed mostly by time-domain instruments, nol frequency- domain instruments such as SA, largely due to the difficulty of separating various jitter components with the SA data? 7.1.2 Impacts of Clock Jitter ‘When a clock experiences jitter, it affects the performance of the device or system thal uses it, We will discuss the impact of clock jitter on two distinct link systems; synchronized and asynchronized, 7.1.2.4 Synchronized System A synchronized system is commonty ased in computer applications. Figure 7.2 shows a typical synchronized link system in which a global clock is used t update and determine the logical bits for driver, sempler, or register. $ If the clock has jitter, it degrades the systems’ functionality and performance. A Clock 7m Figure 7.2 A synchronized system in which a global clock is used for both driving (deviee A) and. receiving (device 1B) devices. Propagation delays (PD) from clock (o data latch inputs (T_c_pda, *f. ¢- pdb) and data drive (device A) outpat to data receiver (device B) input (T_d_pd) are also shown Coco eee eee Foes ereS eos ereers se188 Jitter, Noise, and Signal integrity at High-Speed In this synchronized system, the initial clock pulse causes the driving device Ato latch the data from the inputand launch il into the transmission medium, The second clock causes device B to latch the incoming data. The time available for sending and receiving a date bit is ‘one clock period Ty. Figure 7.3 shows the rela- tionships between those critical timing paratneters. Figure 7.2 ‘The relative relationships between the various tming parameters shown: in Figure 7.2. Here Tsu is the setup time, T_su_mgis the setup time margin, T_td is the hold tine, T_hd_mg is the hold time margin, andT,, is the clock period. Figure 7.3 suggests the following relationships for those timing parameters: TY Top ® Fete Eire Tos Ea it Fonte 8 Equation 72 Zug oe Tt Fe ns ni 0 Faye * Type 70 Equation 7.3 These iwo equations can be rewritien in a different format: Bigiag = Bo Tia Eo ete Togas) Equation 7.4 e e e e e 6 e e e e e e e CJ e . e . . e 6 e e : e .7.4: Clock Jitter 188 Bane = Tana To jie Toa + Fe pte Tpit) Equation 7.5 Let us define Ty gee = Te pda — Te pay The minimum conditions are that both setup time and hold time margin should be larger than 0. This leads to the follow- ing inequalities for setup and hold time conditions: Ty eT gt Bate tT gc the Equation 7.6 Dra ST pat Estee Ei Equation 7.7 Equations 7.6 and 7.7 give the quantitative descriptions of how clock jitter and clock skew affect the performance of the synchronized system in which a com- mon or global clock for both driver and receiver is used. In the absence of clock jitter (Tig =), if Te guey > 0 the minimum clock period increases, degrading system performance. Under this condition, the maxi- mum hold time also increases, making the hold time condition easy to meet. On the other hand, if Tc_skew < 0, the minimum clock period decteases, improving system performance. Under such conditions, the maximum held time deceases, making the hold time condition harder to meet (a race condition). in the absence of skew (T, sjey = 0) if T, ja, > 0. Conger cycle), the mini- mam clock period increases, degrading system performance. Meanwhile, under this same condition, the maximum hold time decreases, making the hold time condition hard to meet. So positive jitter over one clock period makes both clock period and hold time hard to meet. Jf T, jq< 0 (a shorter cycle), the minirium clock period decreases, improving system performance. Under this condition, the maximum hold time increases, making the hold time condition easier to meet and eliminating race conditions. You can see that a longer cycle does more harm to system performance. ‘When both skew and jilter are present, system performance can be any-of the four scenarios just discussed. If skew is the dominant effect, the discussions of skew impact continue to hold. Similarly, if jitter is dominant over skew, the dis- cussions of jitter impact continue to hold, When jitter and skew are comparable, quantitative mumbers for both jitter and skew are needed to assess the net effect on system performance. OOO Oe 8 Oe oeeevueceve190 ditter, Noise, and Signal Integrity at High-Speed 7.12.2 Asynchronized System We have discussed both skew and jitter effects on system performance for a syn- chronized system. Using tink /O as an example, the skew for a synchronized sys- tem becomes hard to manage when the data cate increases, typically above 1 Gb/s, At multiple Gb/s data rates, ‘an asynchronized system is commonly used, as shown in Figure 7.4. tedium Figure 7.4 A block diagram of an asynchronized link system. Note that there is no global clock, as in the case of the syachronized system shown in Figure 7.2 Unlike a synchronized system, this asyachronized link system does not send. clock with data to the receiver. Instead, only data bit stream is sent. The clock is embedded in the data signal and gets recovered at the receiver through a unit called clock recovery (CR). Obviously, this. asynchronized link system has no clock skew, because clock at the receiver is not distributed or sent, but rather is. recovered. Phase-locked Joop (PLL) is typically used to recover the clock from the incoming data stream. Let us assume that the jitter for the transmitter clock and recovered clock are composed of DJs and RJs. Further assume that the DJ and RJ for the tansmitter clock after the high-pass filter of the clock recovery jitter transfer function® (see Chapters 9, 10, and 11) are D/,, , for its pk-pk and a, ,, for its Gaussian sigma or rns, respectively, Similarly, for the recovered clock, we assume that its DJ pk-pk and RI Gaussian sigma are DJ, , aod oy ,,. tespectively. Let us also assume that the jitter from the transmitter clock and jitter from the recovered clock are inde- pendent. Then the worst-case jilter at the receiver eye closure due to clock jitter is as follows: Dhue = Poy, p+ Pd, che — Pg + Se ee Equation 7.8 OO 8-9-0 © 6-0-8 6 © 6 8 8 ee 6-6 6 8+oe Ot Uc Equation 7.9 b 72 Definitions of and Math Modet for Various Jitter Types 191 e ‘The jitter from the transmitter clock and recovered clock both impact the receiver e eye closure according to equations 7.8 and.7.9. They both need to be minimized to achieve good overall system performance. Low-frequency jilter from the trans- s mitler clock can be tracked ot attenuated by the clock recovery function if it has a high-enough comer frequency. A low phase noise oscillator within a PLL clock recovery also provides smalier RF generations. These are. two odvious design guides for reducing jitter from both the transmitter clock and receiver recoveied clock if cost is not a constraint. Conventionally, jitter is defined as any, deviation of the edge Wausition timing from the ideal timing. This is a good mettic for most asynchronous systems, in which a PIL or phase interpolator (PI) is used to generate or recover a clock sig- nal. However, in many synchronous systems, the digital circuits don’t use clock edge timings disectly. Rather, what matters is poriad or the period variation froma one cycle to another. For example, in the global clock system, period variations (or changes) ace important because tonger period can cause hold time violation, resulting in logical failure. In another example, cycle-to-cycle jitter is a good pet- formance indicator for multiplication PLLs because il can capture the timing. dis- turbance caused by the dividing circuits, This section first gives the definitions and mathematical representations for cach type of jitter and poiats out their approptiate applications, Then it discusses their interrelationships. , 7.2 DEFINITIONS OF AND MATH MODEL FOR VARIOUS JITTER TYPES a 5 7.2.1 Phase Jitter ‘The basic phase jitter (also called accumulated jitter) concept is illustrated in Figure 7.5. It shows two waveforms: the ideal clock with zero jitter and the clock, with jitter, The phase jitter js then defined as the actual edge transition timing Geviati the 1 the corresponding ideal clock timing. Mathematically, this means “that phase jitter Al, is defined by the following equation: $ Fae = 4-74 Equation 7.10192 Jitter, Noise, and Signal Integrity at HighSpead where t, and T,, are timings for the nth edge transitions for jittery clock and ideal clock, respectively. If T, is the ideal clock period, we have the following: T-ByeMay- TT Ta hn ty Equation 7.14 and Lacgebte me T A, (At > Atle Equation 7.20 Equation 7.20 is very important because it gives the interrelationship between oycls-lo-cyele jitter, period jitter, and phase jitter! It says that cycle-to-cycle jitte ig the first difference of period jitter and the second difference of the phase jitter. | ‘We can also represent cycle-to-cycie jitter in terms of phase unit of radians: B=, -9,.=@, 8 )-G, Equation 7.21 1 Py2) where b, = 2x(At, /,). Equations 7.20 and 7.21 say that eycle-to-cycle jitter, period jitter, and phase jitter are related through the first and sccond difference functions. If you know the phase jitier, the period jitter and cycle-lo-cycle jitter can be uniquely estimated, Conversely, if-you know the cycle-to-cycle jitter, the period jitter and phase jitter can be estimated.through the first and sccond sum- ming or integration functions. if period jittcr is given, the first difference gives tise to cycle-to-cycle jitter, and the/first integration gives.rise (0 phase, jitter Tt is worth pointing out that the integration function may introduce a constant, so an Yinitial condition is, needed 10 ensure 4 upigque determination. Phase jitter, period jitter, and cycle-to-cycle jitter relationships are similar Jo position, speed, and acceleration relationships in Newtonian mechanics. [| Mathematically, you may define the third difference jitter or cycle-to-eycle jilterTCeeeocevoeeeseeeoveessvsovseneven ve ‘eevee 7.2. Definitions of and Math Model for Various Jitter Types: 195 difference, and so forth. However, those jitter defaitions with higher-order dif- ference functions have not found.mouch practical use yet. Clearly, the simple math model established here provides useful insights into the difference jitter definition and interrelationship. If you know one of them; others can be estimated. For more information on phase, period; and cycle-to-. cycle jitter, refer to 7 and 8. 7.2.4 interrelationships It is useful to show the interrelationships belween phase jitter, period jitter, and cycle-to-cycle jitter with some practical examples to give yori furthes insights, We ‘ill demonstrate their relationship in both time and frequency domains. 7241 Time Domain A.simple example to demonstrate the phase, period, and cycle-to-cycle jilter rela- tionship starts with a phase jitter that is a sinusoidal of the following: = te sinQaf,t,)=sin(a,t,)) 5 staa tae tte Equation 7.22 ‘We.assume that this smusoidal jitter has a zero initial phase and a unit-normalized magnitude. In addition, we define T,, as the period, with a corresponding fre- guency f,, and an angular frequency ©, Obviously we have f, =1/T,,, = 20f, = 2x /T,, This sinusoidal is sampled ot the carrier clock periad of Ty, Using the definition of sinusoidal jitter in equation 7.22-and the phase jitter to period jitter relationship in equation 7.15, we have the following: Mea = (Ene tr ~h 7 L 2 Ate Shed = 2sinia,, Peden, 0 Equation 7.23 2g,tn( t Comparing equations 7.22 and 7.23 suggests the following peak. magnitude we tionship between phase j Jiwer and period jitter (ty) oS phi oD | "Baiiation 7.24196 Jiter, Noise, and Signal Integrity at High-Speed ‘The peak magnitude satio between period jitter and phase jitter follows a sinu- soidaf having the same frequcncy as the sinusoidal phase jitter, When the petiod of the sinusoidal jitter T,, is much larger than the carrier clock period of T5— namely, low-frequency modulation—we have T, >>7,, and o,f,.<> 7,, and 0,7, << L. Equation 7.27 then can be simptified by using sin(x) =x when x << | as Ct), Te @, RY 0, equation 7.36 gives the definition for a phase noise power spec- trum density (PSD) S,(f). Because L(A) is a single-sideband PSD, itis half of the phase noise PSD S,(6): Up 387) Equation 7.37 0.0.0.0. 0 0669 0 6-6-8 where the approximation is because phase noise is defined in an average sense, and PSD is defined “per point” (phase noise power over an indefinitely small fre- quency range). L(®) and 8,(1) defined in equations 7.36 and 7.37 have a physical init of rad?/H. Phase noise is often detined in its decibel unit by taking the logarithmic of equation 7.36 > \ Up=004| FI > Equation 7.38 ‘The phase noise is defined in units of dBc/Hz. If you know the phase noise PSD S,(0), to get dBo/Bz, you must use the following equation: Phage vets “ fe ol? ha ne a) “s =4@leg,, (22 Equation 7.33a [Hore woe 4 Tat 7.3. Clock Jitter Versus Phase Noise . to Equations 7.38 and 7.39 give the formulas for calevlating the: phase noise in dBefHz, when phase noise power or PSD are given, respectively. For more infor. mation on phase noise and jitter relationship, particularly oscillator phase noise, refer to §, 9, and "!, Hore, our focus is on the-relaiionship between phase cise and phase jitter. 7.3.2 Phase Jitter to Phase Noise Conversion Obvidusly, phase jiwer and phase noise are two different metrics or manifestations for the same jitter or noise. process.. Therefore, they are related to each other. ‘Because phase jitter generally is measured in the time domain by instruments such as an SO or TIA, and phase noise generally is measured by frequenoy- domain instruments such as an SA, they are not always discussed in the same context. [Phase jiter to phase noise conversion is a relatively new topic because of _the wide use of high-speed data communication technologies. This section gives “the math theory for the conversions from phase jitter to phase noise, Suppose that the phase jitter is given and we denote it as @(t). Its correspon- ding autocorrelation function (see section 2.5.3 in ‘Chapter 2, “Statistical Signal and Linear Theory for Jitter, Noise, and Siznal Tegrity *) is as follows: R,@) oti ® onarteeai Equation 7.40/77 hase & where T is the time average period. Then the phase jitter PSD (seo section 2.5.4 ia Chapter 2) $(f) can be estimated by the following: 5,(@)= [Rome ar Equation 7.41 After the phase jitter PSD is obtained, the phase noise. PSD i in raft or apc cant be estimated by using equations 7.37 and 7.39, respectively. It will be interesting to sce how well the phasc noise estimated through using a frequency-domain SA agrees with that estimated by a time-domain insttu- mant such as a TIA. The results shown in Figure 7.10 indicate good agreement.204 Jitter, Noise, and Signal Integrity at High-Speed Phase Nolse (de/Hz) “100. 109 0! 1 Frequency (H2) Figure 7.10 Phase ncise measurement in dBe/Hz, The solid is measured from an SA—a frequency-domain instrument—and the dashed linc is from a TA—a time-domain instrument. “the phase information affects the overall 7.3.3 Phase Noise to Phase Jitter Conversion As jitter or phase jitter become a dominant metric in quantifying the performance of a communication link, there is a need to convert the phase noise measured in the frequency domain t phase jitter for devices’ PLLs, clocks, or oscillators used in the link. From the phase noise PSD L(), random jitier (RJ) can he identified as the fenvelopé and deter dont jitter (DJ) can be identified as Speciza floor (sec Figure 7.11). Here DI may include Dt BUJ. No ISI is associated with a clock signal as we had discussed earlier, Because nd pk-pk value, andthe phase - 8 “to determitie the overall DJ (considering all the spectral lines above the RJ back ground) PDF and pk-pk completely and accurately basod on the DJ part of L(f). However, we can still establish a useful upper limit for the DJ peak (or pk-pk), value given L(f),RJ rms estimation is relatively straightforward compared to: Di PDF and ppl determination. of On, Phase wriie- epee é e000 0 0 0 0 ne atl :esoveoesee ee Cree ne Coe 7.3 Glock Jitter Versus Phase Noise 205 80 86 Py Du 0 Lif} (4Bertiz} 105 a0 }- 4 a8 420 . 30 100 150 200 Frequency (Hz) Figure 7.11 RJ and DS signatures on a measured phase noise PSD L(D). If the phase noise PSD L(f) is in rag2/Hz, as defined by equation 7.36, the DS PSD composed of spectral lines above the RJ continuous spectral floor is given by the following: Se oAD= [Se.00-0, Equation 7,42 where{h,. represents the DI spectral line magnitudes at frequency f, in the L) Nijaef — fi is a Dirac delta function at frequénsy f,, Simi- addy, ihe RF PSD with DI’ spectral Lincs removed is given by the following: Sy p= 2A Sy y= afr $otn A- | a Equation 7.43206 vitter, Noise, and Signal integrity at High-Spocd Denote the DJ pk value as @py yy and the RU rms or signna vale a8 Py pyy- Then they can be readily estimated a3 %, Oy aS 2D bers Equation 7.44 Pye = Lf Sow ah ‘ Equation 7.45 and. where f, and f, ate the lower and bigher frequency limits for the RJ frequency hand. Obviously, equation 7.44 does not give an exact DY peak value solution, Instead, it gives an upper limit or worst-case DJ peak that is also very useful. However, if the phase noise PSD LD is in dBo/Hz, as defined by equation 7.39, phase jitter PSD in rad2/Hz can be represented in terms of L{f) as follows: ue) S,(f)- 2410" Equation 7.45 Let us denote the DF spectral line magnitudes in the S, domain as v at fre- quency f, and i= 1, 2, .. N. We have the following: y Se uf)= Bene Equation 7.47 Note that ®, > 0. Similarly, the RJ PSD with DJ power spectral lines removed is given by w Sy afb SQ Sy nD SPY, SGD at Equation 7.48e ° e * 3 74 Summary 207 As soon as the BI PSD and RJ PSD are determined, DI peak 55, Upper limit can be estimated as . 248%, Equation 7.49 and the RI-rms value ®,, ,,. can be estimated the same way as equation 7.45. ‘Thus, we have established a complete set of equations to estimate DI peak value (or pk-pk, assuming that pk-pk = 2pk) upper limits and RJ ams over certain frequency bands from the phase noise PSD measured in either rad?/Hz or dBo/Hz: Note that most of the phase noise to jitter conversion techniques existing in the literature (such as"? and 13, to name a couple) do not convert phase noise to ‘DJ pk-pk and RJ rms parameters that are widely used in quantifying time-domain Jitter in today’s high-speed device characterization and testing. Most of those techniques do not soparate DJ from RJ in the phase noise PSD and only give a mixed and broadband rms value that kas some serious fimitations itt the applica- tion. The new technique introduced in this section addresses this new emerging +need with better comprehension, accuracy, and math rigor, 74 SUMMARY This chapter focused on clock jitter to address the special and important roles it plays im synchronized and asynchronized link. systems. We started with the rea- sons and rationales for why we single oul clock jitter, Then we discussed the defi- nition of jitter along the same lines es the data jitter definition introduced in Previous chapters. The impacts of clock jitter on two distinct systems of synchro- nized and asynchronized systems were discussed, along with their performance relationships to clock jitter and clock skew. Section 7.2 focused on different types of jitter and metries for a clock signal due to ils even and uniform edge transition properly. Phase jitter, period jitter, and cycle-to-cycle jitter were introduced, along with their intezrelationships in (he time and frequency domains, We pointed out that those different jitter types are different manifestations of the same jitter mechanism and are uniquely related, 1f you know one of them, you can determine the other with appropriate conditioning, With the introduction of phase jitter, we discussed the important topic of the intertclationship between phase jitter and pitase noise in section 7.3. The mathematical representations of phase jitter and phase noise were derived, Detailed procedures nd math mapping equations for208 Jitter, Noise, and Signal Integrity at High-Speed phase jitter to phase noise conversion, as well as phase noise to phase jitter con- version, were given for both deterministic and rancom components in the respec- tive phase noise and jitter domains. This information can be very useful given the recent trend that clock performance is specified in tetms of phase jitter and/or phase noise. The interchange between them becomes common and necessary. ENDNOTES 1. A. V. Oppenheim, A. S. Willsky. and 5. H. Nawab, Signals & Systems, Prentice Hall, 1996. 2. D, Detickson, Fiber Optic Test and Mcasuretent, Prentice Hall, 1998. 3. National Committee for Information Technology Standardization (NCITS), working draft for “Fibre Channel_—Methodologies for Jitter Specitication- MISQ” Rev 14, 2005. 4. I.M. Rabaey, Digital Integrated Circuits: A Design Perspective, Englewood Chiifs, NJ: Prentice Hall, 1996, 5. W.J, Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998 6. M. Liand §. Wilstrup, “Paradigm Shift for Jitter and Noise in Design and Test > 1 Gb/s Communication Systems,” IEEE International Conference on Computer Design (CCD), 2003. 7. M. Li, A. Marwick, G. Talbot, and J. Wilstrop, “Transfer Functions for the Reference Clock Jitter in a Serial Link: Thearyand Applications,” IEEE International ‘Test Conference (TC), 2004. -.8. PCL Express Jitter white paper (1), 2004: hitp/ivww,pcisig.com/specifications! peiexpress/technical_library. 9. B. Razavi, “A Study of Phase Noise in CMOS Osciltators,” IEEE J. Solid- State Circuits, vol. 31, pp. 331-343, Mar. 1996. 10. JA. MeNeili, “Jitter in Ring Oscillators,” IEEE J, Solid-State Circeits, vol. 32, pp. 870-879, June 1997. li. TH. Lee and A. Hajimiri, “Oscillator Phase Noise: A Tutorial,” TEBE J. Solid-State Circuits, vol. 35, pp. 326-336, Mar. 2000. 12. Rutman, J., “Charecterization of Phase and Frequency Instabilities in Precision Frequency Souyces: Fifieen Years of Progress,” Proceedings of the IBEE, vol. 66, no. 9, Sept. 1978. 13. Boris Drakhlis, “Calculate Oscillator Jitter by Using Phase-Noise Analysis.” Microwaves & RE pp. 82-90, Jan. 2001