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CH) 04 (1
CH) 04 (1
Electronics - 04
: Transistors
More on Transistors
- Ebers - Moll model
1.
V C > VE
npn
IC
IB
C
B
IC
IB
VB VE + 0.6 V
VB = VE + VBE
4.
IC = hF E IB = IB
"
kT
1.38 1023 J/K (273.16 + 20)
=
25.3 mV
q
1.6 1019 C
note:
IC
Temperature: 27.0
1.0A
1.0mA
1.0uA
Note: y-axis
is log-scale
1.0nA
10pA
0.1V
Ic(Q1)
0.2V
0.3V
0.4V
0.5V
V_V1
Page 1
0.6V
0.7V
0.8V
0.9V
1.0V
Time: 20:19:00
VBE
From IC = IS exp
10 exp (
VBE /VT
VBE2
VBE1
)
VT
VT
"
IC2
exp
IC1
VBE2
VBE1
VT
VT
"
so, if IC2/IC1 ~ 10
VT lne 10 = VBE
1
From IC = IS exp
and re =
gives
VT
VT
dIC
re =
dVBE
VT VBE /VT
=
e
dIC
IS
"
!
"
VT ! VBE /VT
V
T
=
e
1 eVBE /VT =
1 eVBE /VT
IC
IC
3. Temperature dependence
re
VT
25.3 mV
25
=
IC
IC
IC
when IC is in mA
VBE = VCE
VBE slightly varies with changing VCE at constant IC
Electronics by Eunil Won, Korea University
0.0001
+VCC
IC = 1 mA
This has to be changed to
VB (fixed)
RE
re != 0
( IC = 1 mA, re = 25/IC )
RE
load
RS
re
VB (fixed)
IC = 1 mA
ex) RS = 1k
We learned
this before!
Zout
Zsource
=
hf e + 1
"
load
re = 25/IC = 25
Rout
Electronics by Eunil Won, Korea University
1k
= 25 +
35
101
G=
RC
RE
10 k 1(mA)
= 400
25 V
20 V
= 2 mA
10 k
IC = 0
IC =
G = 800
G=0
VCC
VCC
VIN
VOUT
time
time
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HIJ)>*<+,8$8?$('##$*?"(@)H";#'K$J
B.(M
03(M
0.(M
3(M
.=
MHN0-;J
0.(=
!"#$-)C$@#$(D$*)01E)B..2
B.(=
G.(=
)))))))))))
&'($
F">$)0
4.(=
3.(=
L.(=
&'($-).1-0G-43
Our spice simulation shows the clear nonlinear behavior discussed in the previous slide
What did I put in V4 to get this? Please play around with your spice program!
signal in
(dc coupled)
re is
hidden
here
3. Biasing
The grounded emitter amplifier is difficult to bias stably against the temperature change
Previously, we said :
IC
VBE
The grounded emitter amplifier is difficult to bias stably against the temperature change
Previously, we said :
spice simulation:
* D:\hardware\electronics\electronics\shematics\transistor_thermal.sch
Date/Time run: 09/18/07 08:36:36
Temperature: 10.0, 12.0, 14.0, 16.0, 18.0,...
(A) transistor_thermal (active)
oC
10
680mV
VBE
640mV
V 70 mV
600mV
50 oC
560mV
4V
6V
8V
10V
... V(Q1:b,Q1:e)
V
70 mV
o
1.8
mV/
C
T
40 o C
Electronics by Eunil Won, Korea University
14V
16V
V_V2
Page 1
18V
20V
VC
Time: 08:39:56
82k
7.5k
signal in
1.0 V
0.1 uF
10k
Note:
7.5 V
1.6 V
RE 0.1RC
(1.0k)
(7.5k)
10 k
15 V 1.6 V
10 k + 82 k
VE = VB 0.6 V = 1.0 V
IE =
10 uF
1.0k
signal out
VB =
1.0 V
= 1.0 mA
1.0 k
IE IC = 1.0 mA
VE
If not, (if RE was too small), then IE =
RE
big
change of
IE
Note: the emitter bypass capacitor is chosen by making its impedance small compared with re (not RE) at the
lowest frequency of interest
1
1
25
Z
=
=
at 650 Hz, the impedance of the capacitor becomes
2f C
2 650 10 106
at signal frequency, input coupling capacitor sees an impedance of
10 k || hf e 25 10 k || 2.5 k = 2 k
10k
ac
dc
1.0k
+20V
20 k
10 k
10 k
10 k
C
Q2
signal out
Q1
signal in
+20V
i1
20 k i3
10 k
i2
0.6V
1.0 mA
10 k
0.6V
Q1
10 k
Q2
VC
0.6 V
full analysis
VBE
20 V VC
20 k
VC = VCC IC RC = 20 V 1.0 mA 20 k 0 V
IC
i2 =
VC 0.6 V
10 k
i3 =
VC 0.6 V
10 k
1 mA = i1 i2 i3
20 V VC
VC 0.6 V VC 0.6 V
20 k
10 k
10 k
VC < VB
11
+20V
i1
20 k i3
10 k
10 k
10 k
0.6V
Q1
Q2
VC
IC (Q1 ) = 1 mA
i2
0.6V
modified analysis
20 k
(1) IC (Q2 ) = 1 mA
(2) VB (Q2 ) = 0.6 V
1
1
(3) IB (Q2 ) =
IC (Q2 ) =
1 mA = 10 A
hf e
100
(4) VC (Q1 ) = 10 k 10 A + 0.6 V = 700 mV
20 V 700 mV
(5) I(20 k) =
0.965 mA
20 k
IC (Q1 ) = 0.965 mA 2 10 A = 0.945 mA
Now is it closer to SPICE simulation?
Electronics by Eunil Won, Korea University
12
: spice simulation
(quiescent point)
13
I=0
+15V
RC
8.2k
R1
68k
Since R1 : R2 = 10 : 1,
signal out
signal in
VC = 11VBE = 11 0.6 V 7 V
IC =
(15 7) V
1 mA
8.2 k
R2
6.8k
!
"
IC = IS expVBE /VT 1
1) now if for some reason VBE is increased, then IC will be increased due to Ebers-Moll model
2) If IC is increased then there will be larger voltage drop across RC
3) If there is larger voltage drop across RC, then VB tens to be decreased
4) If VB is decreased, then VBE is decreased
1.0 mA
IC
this is the idea of negative feedback that allows a stable biasing of the circuit
Electronics by Eunil Won, Korea University
0.6 V
VBE
14
I=0
+15V
RC
8.2k
IC = 1 mA
VC = 7 V
R1
68k
7.5k
signal out
spice simulation
signal in
R2
6.8k
VB =
0.6 V
15
Current Mirrors
It is possible to make a circuit that gives a stable current source: let us consider the following circuit
+15V
Q1
14.4k
Q2
load
IC (Q1 ) = IC (Q2 ) = 1 mA
3) From 1),
(mirroring of the current is occurred, regardless of the value of the load)
For a more realistic case:
since the collector current is IC,
IC / IC /
Q1
Q2
IC
IR
2IC /
IB = IC /
and then
IR = IC + 2IC / = IC
2
1+
"
IC (Q2 )
I
! C " and is reduced to 1 if ! 1
=
IR
IC 1 + 2
16