Name:

Homework 7
Due Date: 11/07/2012 in class
1. Assume that the following sequence of instructions is executed on a 5-stage pipelined
datapath:
1
2
3
4
5

ADD R5,R2,R1
LW R3,4(R5)
LW R2,0(R2)
OR R3,R5,R3
SW R3,0(R5)

a) If there is no forwarding or hazard detection, insert NOPs to ensure correct

execution.
1
2
3
4
5

D
F

1 ADD R5,R2,R1
2 LW R3,4(R5)

E
D
F

#
#
#
#
#
#
#
#

3 LW R2,0(R2)
4 OR R3,R5,R3
5 SW R3,0(R5)

R5
R5
R3
No
R3
R3
R3
R5

M
NOP
NOP

W
NOP
NOP

E
D
F

M
E
D
F

W
M
NOP
NOP

W
E
D

M
NOP

W
NOP

is destination, written in WB stage

is source, not available until after WB of 1
is destination, written in WB stage (inst 4)
dependencies, no hazard
is source, not available until after WB of 2
is destination, written in WB stage (inst 5)
is source, not available until after WB of 4
is source but has already been updated

ADD R5,R2,R1
NOP
NOP
LW R3,4(R5)
LW R2,0(R2)
NOP
OR R3,R5,R3
NOP
NOP
SW R3,0(R5)

b) If there are forwarding and hazard detection units implemented, indicate the
instructions where forwarding is required to eliminate NOPs.
1
2
3
4
5

ADD R5,R2,R1
LW R3,4(R5)
LW R2,0(R2)
OR R3,R5,R3
SW R3,0(R5)

D
F

E
D
F

M
E
D
F

W
M
E
D
F

W
M
E
D

W
M
E

W
M

# R5 is destination, available after Ex stage (inst 2)

# R5 is source, forwarded from EX/Mem reg
# R3 is destination, forwarded from Mem/WB reg
# R3 is source, forwarded from Mem/WB reg

Name:

2. Consider the following instructions being executed in pipelined MIPS processor and treat
them separately:
i.
ii.

SW R16, -100(R6)
OR R2, R1, R0

a) As the instruction executes, what is kept in the pipeline registers in each stage?
b) Which registers are read?
c) What does the instruction do in each stage of the pipeline?