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Thit k kin trc h thng

Vit code RTL v m phng
Cng on tng hp netlist

Functional specification :
L m t yu cu t pha ngi
dng nh 1 bn cc chc nng
yu cu tn hieu input v output
ca 1 h thng hay l datasheet .
Cn phi hiu r nguyn l hot
ng ca ton b h thng, cc
c im v cng ngh, tc x
l, mc tiu th nng lng, cch
b tr cc Pins, cc lc khi,
cc iu kin vt l nh kch
thc, nhit , in p...
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Define Architecture :

M t chi tit chc nng tng khi

La chn thut ton x l
Xy dng v tr tng khi
S dng ngun IP hay t pht trin
Chn la tool v ngn ng.

Coding RTL :

S dng ngn ng thit k phn cng

(Verilog-HDL,VHDL, System-C...)
hin thc cc chc nng logic ca thit
k. Lc ny ta khng cn quan tm n
cu to chi tit ca mch m ch ch
trng vo chc nng ca mch da trn
kt qu tnh ton cng nh s lun
chuyn d liu gia cc thanh ghi .

RTL Verification :
Kim tra thit k logic
Loi tr li t VHDL code
M phng simulation bi tool chuyn dng

Synthesis :
Sau khi kim tra v m bo h thng chy ng chc nng,
RTL code c dng tng hp to netlist .
c h tr ca cc cng c chuyn dng nh Design
Compiler (Synopsys), Synplify (Synplicity)
H thng t ch c m t bng RTL s c chuyn sang
mc cng, m t di dng text v c gi l netlist .

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L giai on phn tch v mt thi gian ca thit k sau khi

Synthesis, phn mm s dng l PrimeTime cho php phn
tch tr hon qua cc ng truyn tn hiu trong thit k.
Kt qu phn tch s l cc bo co, ngi thit k da vo
cc bng bo co ny xem tc hot ng ca thit k
c t yu cu hay khng. Trong thc t qu trnh STA c
lp i lp li nhiu ln vi Synthesis cho n khi cc yu
cu v thi gian ca thit k c p ng.
STA gm hai giai on: pre-layout STA v post-layout STA.
Giai on pre-layout STA m bo thit k tha mn cc
yu cu v thi gian sau qu trnh Synthesis.
Giai on post-layout STA m bo thit k vn tha v
thi gian sau khi Back End thit t cc gi tr thc v R,
C ca cc Cell v cc dy ni.

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C u vo l file netlist t
Front End
Kt thc s to ra file *.gds
hay *.gds2

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Chc nng :
To hnh cho linh kin transistor, in tr, t in, cun cm ,
dy dn
Tun theo cc qui lut (design rules) m cng ngh ang s
dng .

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Floorplanning

Back
End

Place v Routing
Tape-out

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Cng c nhn cc file th vin vt l, th

vin logic v file netlist lm c s
to layout
Floorplanning l qu trnh sp xp cc
khi trong vng die hay bn trong cc khi
khc v gia chng phi c nh ngha cc
vng dng i dy.
Qu trnh Floorplanning c nh hng rt
ln n hiu sut v nh thi ca mch
Cht lng Floorplanning nh hng ng
k n cht lng thit k ca chng ta.

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Qu trnh t cc Cell v kt ni dy da trn kt ni

v mt Logic gia cc Cell trong Gate-level Netlist.
Tip theo l kt ni dy s tin hnh giai on postlayout STA v post-layout simulation m bo
Netlist vi cc gi tr thc v R, C ca cc Cell v dy
ni vn tha chc nng v thi gian. Nu khng c li,
xut d liu ra di dng file gds2. Nu c li, kim
tra li vic t cc Cell v kt ni dy.

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Kim tra li tt c cc bo co sau qu

trnh Place and Route trc khi a i sn
xut.

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Kim tra ,so snh gia schematic v layout c v c

ph hp cha ?

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Mask l ci khun c vi mch ln tm Silicon.

Cc b Mask s c to ra di dng data c bit. Mask
data s c gi ti cc nh sn xut Mask nhn v mt b
Mask kim loi phc v cho cng vic sn xut tip theo

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Cng ngh sn xut Mask hin i

dng tia in t (EB - Electron
Beam). Cc in t vi nng lng
ln (vi chc keV) s c vut
thnh chm v c chiu vo lp
film Crom trn b mt tm thy
tinh. Phn Cr khng b che bi
Mask (artwork) s b ph hy, kt
qu l phn Cr khng b chm
electron chiu vo s tr thnh
mask thc s.
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1.

Chun b wafer

2.

Cc quy trnh x l

3.

Kim tra ng gi-xut xng

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y l bc tinh ch ct(SiO2) thnh Silic

nguyn cht .

Silic nguyn cht s c pha thm tp

cht l cc nguyn t nhm 3 hoc nhm 5.

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Sau khi c c c ta c mt khi silicon

n tinh th.

Cn c gi l thi silicon(silicon Ingot) v

c cc tnh cht c th sn xut
transistor.

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Cng on ny c gi l ingot slicing

Sau khi c ct lt chng ta co nhng

wafer dng th.

V chng s c nh bng cho n khi

mt thng khng nhn thy nhng t vt
na. Trc khi i in litho.

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y l bc chun b to ra cc
transistor.

Tm wafer c bi du cc dung dch lng

Dch ny dng chn quang(photo resist)

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Sau khi hnh thnh gia cc lp chn quang

wafer s c phi sng trc cc tia t
ngoi(UV).
Trc khi chm vo b mt wafer cc tia t
ngoi s phi lt qua cc khe c c
sn trn tm mt n.

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T trn xung: UV -> mask -> len -> wafer

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Lp chn quang b chuyn sang dng ha

tan v s c ty sch bng mt dng
dung mi ph hp.

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Mu xm l phn silicon nn

Mu hng tm l lp vt liu cch in

Mu lc l phn silicon tinh th to ra

ngun mng v knh

Mu vng l lp in mi (lp ny kh
quan trng, ti s k vo dp khc)

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Mu lam nht l cc cng

Mu lam m nh lc trc l lp chn

quang quen thuc.

Mc ch ca vic cy ion l to ra cc
ngun v cc mng.

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Tm wafer c ngm vo dung dch

CuSO4.

Phn cn li ca wafer ni vo cc m (-)

ca ngun in. Cc dng (+) l mt
ming ng c ngm chm vo dung dch
mui.

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kim tra hiu nng chip trc khi tung ra th

trng.

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FPGA Design Advantages

ASIC Design Advantages

Faster time-to-market: no layout,

masks or other manufacturing steps
are needed.
No upfront NRE (non recurring
expenses):costs typically associated
with an ASIC design.
Simpler design cycle: due to software
that handles much of routing,
placement, and timing.
Field reprogramability: a new
bitstream can be upload remotely

Full custom capability: for design

since device is manufactured to
design specs.
Lower unit costs: for very high
volume designs.
Smaller form factor: since device is
manufactured to design specs.
Higher raw internal clock speeds.

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Truyn thng: in thoi s, mng .

My tnh: PC/Workstation, Chipset.
Hng tiu dng: Game box, Camera s ,
TV .

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OMAP 4
- Sn xut theo cng ngh 45n
- Kch thc 12mm x 12mm x 0.4mm
- Li ha POWER VR SGX540, h tr
giao din 3D.
- H tr mn hnh phn gii WSXGA.
- Ng video HDMI.
- Chy video 1080p HD hn 10h.
- Ghi video 1080p HD hn 4h.
- Nghe nhc cht lng CD 140h.
- Tch hp cc cng ngh wireless tin
tin nh WiLink, Wi-Fi, NaviLink GPS
v BlueLink Bluetooth.
- H tr chip qun l nng lng.
- H tr my chiu siu nh.

H tr my chiu siu nh

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NVIDIA Tegra 2
- Sn xut theo cng ngh 40nm.
- Tng thch cc HH: Windows CE,
WinMo, Android, Chrome OS cho nn h
tr tt cho cc thit b di ng.
- Gm c 8 nhn x l c lp
- Gii m tt hnh nh 3D.
- Xem phim Full HD 1080p.
- H tr my nh 12MP.
- Tiu th in nng khong 500mW.

Mt board mch my tnh s dng Tegra 2

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