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Trng i hc SPKT
Khoa: CNTT
trnh o to: H
H Thng Nhng
M hc phn: ESYS431080
Nhng khi nim tng quan v m hnh h thng nhng, tnh cht, cc ng dng nhng
Cung cp kin thc v mt s h thng nhng.
Cc Phng php thit k h thng nhng
Vi iu khin ARM
Tp lnh ca vi iu khin ARM
Cung cp kin thc v nguyn tc lp trnh nhng, cc cng c lp trnh phn mm nhng
M t
Chun u ra
(Goal description)
CTT
(Hc phn ny trang b cho sinh vin:)
Cc khi nim lin quan ti h thng nhng, tnh cht, cc thnh 1.2, 1.3
phn to nn h nhng.
G2
2.1, 2.2
G3
3.1,3.2
G4
Kh nng vn dng kin thc lp trnh nhng gii quyt mt s 4.4, 4.5
vn n gin trong thc t.
9. Chun u ra hc phn
Mc
tiu
G1
Chun
u ra
hc phn
M t
(Sau khi hc xong mn hc ny, ngi hc c th:)
Chun
u ra
CDIO
G1.1
1.2
G1.2
1.2
G1.3
1.3
G1.4
1.3
G1.5
1.3
G1.6
G2.1
1.3
G2.2
G3.1
3.1.1,
3.1.2,
3.1.3
G3.2
3.2.6
G4.1
4.3
G4.2
4.5.
G2
G3
G4
2.1, 2.3
2.5
[1] Frank Vahid and Tony Givargis , Embedded System Design: A Unified
Hardware/Software Approach, John Wiley & Sons, Inc. 2002
[2] inh Cng oan, bi ging cu trc my tnh v hp ng, khoa CNTT i hc SPKT
TP.HCM
[3] Joseph Yiu, The Definitive Guide to the ARM Cortex-M3, Elsevier Newnes, 2007
[4] Jonathan W Valvano, Embedded Systems: Introduction to Arm Cortex(TM)-M
Microcontrollers(Volume 1), 2012
[5] Jonathan W Valvano, Embedded Systems: Real-Time Interfacing to Arm CortexM Microcontroller, 2012
12. T l Phn trm cc thnh phn im v cc hnh thc nh gi sinh vin :
Hnh
thc
KT
Thang im 10
K hoch kim tra nh sau :
Cng c KT
Ni dung
Thi im
Chun
u ra
KT
Bi tp
BT#1
BT#2
BT#3
T l
(%)
30
Tun 5
Bi tp nh
trn lp
G1.1
Tun 9
Bi tp nh
trn lp
G2.1
G2.2
Tun 10
Bi tp nh
trn lp
G2.1
G2.2
Bi tp ln (Project)
Nhm sinh vin t 2-3 ngi chn 1 trong
cc bi tp c a ra
10
Tun 8
nh gi sn
phm
BL#1
Tiu lun - Bo co
Mi nhm sinh vin t 2-3 ngi chn 1
trong cc ti sau tm hiu v trnh by
bo co:
G3.1
G2.1
G2.2
G4.3
G4.5
10
Tun 10-15
Tiu lun Bo co
G3.2
Thi cui k
50
Thi t lun,
hoc tiu
lun, vn p
G1.1
G1.2
G2.1
G2.2
G4.3
G4.5
13. K hoch thc hin (Ni dung chi tit) hc phn theo tun
Tun
Ni dung
Chun u
ra hc phn
G1.1
Tm tt cc PPGD chnh:
+ Thuyt trnh.
+ Trnh chiu PowerPoint.
+ Lm mu.
+ Tng tc hi p vi sinh vin
B/ Cc ni dung cn t hc nh: (6)
Cc ni dung t hc:
1.9 Cc ng dng thc tin ca h thng nhng
1.10
n tp li kin trc phn cng CPU 8086/8088
G1.2
G1.2
G1.3
- Cc ti liu hc tp cn thit
+ [1] inh Cng oan, bi ging h thng nhng, khoa CNTT i hc
SPKT TP.HCM
+ [2] Embedded Systems Architecture: A Comprehensive Guide for
G1.3
G2.2
G4.1
Ni dung GD:
4-5
6-7
G1.4
G1.5
G4.2
Ni dung GD l thuyt:
G4.1
G4.2
6. Chng 6
6.1. T chc chng trnh v b nh vi iu khin
6.2. Kiu d liu, hng, bin
6.3. a ch Thanh ghi vi iu khin/ a ch port
6.4. Cc thao tc s hc, logic, dch
6.5. Cu trc iu khin
6.6. Hm
6.7. Chng trnh phc vc ngt
PPGD chnh:
7
G1.6
+ Thuyt trnh.
+ Lm mu.
+ Tng tc hi p vi sinh vin
G2.1
G2.2
Chng 7 :
A/ Cc ni dung v PPGD chnh trn lp: (3)
Ni dung GD l thuyt:
9-10
G1.6
PPGD chnh:
+ Thuyt trnh.
+ Trnh chiu PowerPoint.
+ Lm mu.
+ Tng tc hi p vi sinh vin
B/ Cc ni dung cn t hc nh: (6)
Lm cc bi tp c giao
G1.1
G1.2
Cc bi thc hnh
11-14
G3.1
G3.2
Ni dung GD:
Lab 1 : Lm quen vi mi trng lp trnh Keil
Lab 2 : Lm quen vi phn mm m phng Proteus
Lab 3 : GPIO
Lab 4 : iu khin Led
PPGD chnh:
+ Thuyt trnh.
G4.1
G4.2
+ Lm mu.
+ Tng tc hi p vi sinh vin
B/ Cc ni dung cn t hc nh: (6)
Lm cc bi tp c giao
n tp v kim tra
A/ Cc ni dung v PPGD chnh trn lp: (3)
Ni dung GD l thuyt:
G1.1
G1.2
PPGD chnh:
+ Thuyt trnh.
15
+ Lm mu.
+ Tng tc hi p vi sinh vin
G1.1
G1.2
T trng BM
<ngi cp nht k
v ghi r h tn)
T trng B mn:
<ngi cp nht k
v ghi r h tn)
T trng B mn:
10