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Spectre RF Noise-Aware PLL Methodology
Spectre RF Noise-Aware PLL Methodology
Introduction
Phase locked loops are essential blocks in most analog mixedsignal and radio frequency (RF) applications today.
Because of the complexity of PLLs, the different time constants
involved (two widely-spaced time constants), and the fact that the
voltage-controlled oscillator (VCO) frequency often oscillates
several order of magnitude faster than the reference frequency,
simulating PLLs at a transistor level presents multiple challenges
and is extremely time demanding.
Cadence SpectreRF Noise-aware PLL flow enables designers to
efficiently and accurately predict PLL response using a non-linear
model approach to capture the VCO dynamic behavior
Ref
PFD
CP
LPF
VCO
Div
N * fref
fref
Divide by N
Out
Ref
PFD
CP
LPF
VCO
Out
Div
N * fref
fref
Divide by N
Compute
PSS-PNoise
Automatically
generate model
50
V/ Hz
20 V/ Hz
10
V/ Hz
5 V/ Hz
V
PFD
VCO
CP
2 V/ Hz
1 V/ Hz
500 nV/ Hz
200 nV/ Hz
100 nV/ Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
Place DUT
in Testbench
Start ADE and
Setup Test
Simulate
PSS/PNOISE
Automatically
Generate Model
Create PLL
Testbench
Start ADE and
Setup Test
Simulate
Transient
Analyze
Results
10
(power supply
noise injection)
(custom veriloga)
(PPV model)
(LC tank
noise injection)
(schematic)
(utility for freq output and saving
periods.txt for phase noise/jitter
calculation)
Cell: pll_bench
11
Model Overview
12
13
14
Phase
Deviation
Steady-State
xs(t)
15
(t ) = v1 n(t )
16
(10)
[6]
17
18
19
20
21
22
The test circuit used was a N-Integer 2.4 GHz PLL including a PFD,
charge pump, VCO and divider available in Cadence RFKit ([8], [9]).
Simulation
results
Spectre
Transistor level
simulation
Spectre
PPV CMI/VerilogA
simulation
Simulation
Ratio
PPV Sampling*=1
46 hours
(165.08Ks)
10.8 s
15285
320
PPV Sampling*=50
*Sampling refers to the number of sample points per period. To calculate the phase accurately, the transient time step is
bounded as ((1/(vco frequency)) / sample points per period
23
25
26
Conclusions
27
References
28
[1] Emad Hegazi, Jacob Rael, Asad Abidi. The Designers Guide to
High-Purity Oscillators. Kluwer Academic Publishers, 2005
[2] Hajimiri A, Lee T H. A General Theory of Phase Noise in
Electrical Oscillators. IEEE Journal of Solid-State Circuits, 1998,
33(2): 179~194
[3] Lee T H, Hajimiri A. Oscillator Phase Noise: A Tutorial. IEEE
Journal of Solid-State Circuits,2002, 35(3): 326~336
[4] Demir A, Liu E W Y, and Sangiovanni-Vincentelli A L. Timedomain non Monte-Carlo noise simulation for nonlinear dynamic
circuits with arbitrary excitations. IEEE Transactions for ComputerAided Design, 1996, 15(5): 493~505
[5] Vanassche P, Gielen G and Sensen W. On the Difference
between Two Widely Publized Methods for Analyzing Oscillator
Phase Noise Behavior. Proceeding IEEE/ACM ICCAD 2002
References
29
30