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Arm 32
Arm 32
STM32F417xx
ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,
crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Datasheet - production data
FBGA
WLCSP90
UFBGA176
(10 10 mm)
Features
Core: ARM 32-bit Cortex-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait state execution
from Flash memory, frequency up to 168 MHz,
memory protection unit, 210 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
Up to 1 Mbyte of Flash memory
Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data
RAM
Flexible static memory controller
supporting Compact Flash, SRAM,
PSRAM, NOR and NAND memories
LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
1.8 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low power
Sleep, Stop and Standby modes
VBAT supply for RTC, 2032 bit backup
registers + optional 4 KB backup SRAM
312-bit, 2.4 MSPS A/D converters: up to 24
channels and 7.2 MSPS in triple interleaved
mode
212-bit D/A converters
General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 168 MHz, each with up to 4
June 2013
This is information on a product in full production.
Part number
STM32F415xx
STM32F417xx
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www.st.com
Contents
STM32F415xx, STM32F417xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/186
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.14
2.2.15
2.2.16
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.17
2.2.18
2.2.19
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.20
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.21
2.2.22
2.2.23
2.2.24
2.2.25
2.2.26
2.2.27
2.2.28
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35
2.2.29
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STM32F415xx, STM32F417xx
Contents
2.2.30
2.2.31
2.2.32
2.2.33
Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2.34
2.2.35
2.2.36
2.2.37
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.38
2.2.39
2.2.40
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.1
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.5
5.1.6
5.1.7
5.2
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
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Contents
STM32F415xx, STM32F417xx
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
5.3.16
5.3.17
5.3.18
5.3.19
5.3.20
5.3.21
5.3.22
5.3.23
5.3.24
5.3.25
5.3.26
5.3.27
5.3.28
6.2
4/186
A.1
A.2
A.3
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STM32F415xx, STM32F417xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F415xx and STM32F417xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32F41x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
STM32F41x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 80
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 81
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 81
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 82
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 84
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 89
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 90
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
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STM32F415xx, STM32F417xx
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Table 96.
Table 97.
Table 98.
List of tables
DocID022063 Rev 4
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List of figures
STM32F415xx, STM32F417xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
8/186
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STM32F415xx, STM32F417xx
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
List of figures
DocID022063 Rev 4
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List of figures
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
10/186
STM32F415xx, STM32F417xx
USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 173
USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Introduction
Introduction
This datasheet provides the description of the STM32F415xx and STM32F417xx lines of
microcontrollers. For more details on the whole STMicroelectronics STM32 family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F415xx and STM32F417xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex-M4 core, please refer to the Cortex-M4 programming
manual (PM0214) available from www.st.com.
DocID022063 Rev 4
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Description
STM32F415xx, STM32F417xx
Description
The STM32F415xx and STM32F417xx family is based on the high-performance ARM
Cortex-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4
core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances application security. The
Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document.
The STM32F415xx and STM32F417xx family incorporates high-speed embedded
memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of
backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
a true random number generator (RNG), and a cryptographic acceleration cell. They also
feature standard and advanced communication interfaces.
Up to three I2Cs
Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals
can be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
Two CANs
An SDIO/MMC interface
New advanced peripherals include an SDIO, an enhanced flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more), a camera
interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2:
STM32F415xx and STM32F417xx: features and peripheral counts for the list of peripherals
available on each part number.
The STM32F415xx and STM32F417xx family operates in the 40 to +105 C temperature
range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the
device operates in the 0 to 70 C temperature range using an external power supply
supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F415xx and STM32F417xx family offers devices in various packages ranging
from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.
12/186
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Medical equipment
STM32F415xx, STM32F417xx
These features make the STM32F415xx and STM32F417xx microcontroller family suitable for a wide range of applications:
STM32F415RG
SRAM in
Kbytes
STM32F415VG
STM32F415ZG
512
192(112+16+64)
Backup
Ethernet
1024
STM32F417Zx
512
1024
STM32F417Ix
512
1024
Yes(1)
No
No
Yes
Generalpurpose
10
Advancedcontrol
Basic
IWDG
Yes
WWDG
Yes
RTC
Yes
STM32F417Vx
1024
System
Timers
STM32F415OG
Yes
Description
13/186
Peripherals
STM32F415RG
STM32F415OG
STM32F415VG
SPI / I2S
4/2
USB OTG FS
Yes
USB OTG HS
Yes
CAN
SDIO
Yes
Camera interface
No
Yes
DocID022063 Rev 4
51
72
82
114
82
114
140
16
24
24
LQFP144
UFBGA176
LQFP176
3
16
13
16
12-bit DAC
Number of channels
24
Yes
2
168 MHz
1.8 to 3.6 V(3)
Operating voltage
Operating temperatures
WLCSP90
LQFP100
LQFP144
LQFP100
1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip
Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this
package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF).
STM32F415xx, STM32F417xx
Package
STM32F417Ix
Yes
Cryptography
12-bit ADC
Number of channels
STM32F417Zx
USART/UART
GPIOs
STM32F417Vx
I2C
Communicatio
n interfaces
STM32F415ZG
Description
14/186
STM32F415xx, STM32F417xx
2.1
Description
VSS
VSS
48
33
32
47
49
31
VSS
VSS
17
64
1
16
ai18489
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Description
STM32F415xx, STM32F417xx
Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package
76
75
73
VSS
51
50
49
VSS
VSS
100
99 (VSS)
19
26
20
0
resistor or soldering bridge
present for the STM32F10xxx
configuration, not present in the
STM32F4xx configuration
25
VSS
VDD V
SS
ai18488c
VSS
108
109
73
72
106
71
VSS
VSS
Signal from
external power
supply
supervisor
143 (PDR_ON)
30
144
31
37
36
VSS
VDD VSS
Two 0 resistors connected to:
- VSS for the STM32F10xx
VDD
VSS
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ai18487d
STM32F415xx, STM32F417xx
Description
89
88
133
171 (PDR_ON)
176
45
1
44
VDD VSS
Two 0 resistors connected to:
- VSS, VDD or NC for the STM32F2xx
- VDD or signal from external power supply supervisor for the STM32F4xx
MS19919V3
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Description
2.2
STM32F415xx, STM32F417xx
Device overview
Figure 5. STM32F41x block diagram
CCM data RAM 64 KB
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG & SW
ETM
AHB3
MPU
NVIC
External memory
controller (FSMC)
SRAM, PSRAM, NOR Flash,
PC Card (ATA), NAND Flash
TRACECLK
D-BUS
TDES, AES256
FIFO
USB
OTG HS
DMA/
FIFO
DMA2
8 Streams
FIFO
DMA1
8 Streams
FIFO
RNG
1 MB
FIFO
DMA/
Flash
up to
SRAM 112 KB
HSYNC, VSYNC
Camera
interface
PUIXCLK, D[13:0]
SRAM 16 KB
FIFO
DP, DM
PHY
MDIO as AF
Ethernet MAC
10/100
MII or RMII as AF
INTN, NIIS16 as AF
HASH
I-BUS
S-BUS
PHY
ARM Cortex-M4
168 MHz
FPU
ART ACCEL/
CACHE
TRACED[3:0]
USB
OTG FS
DP
DM
ID, VBUS, SOF
Power managmt
Voltage
regulator
3.3 to 1.2 V
@VDD
@VDDA
PA[15:0]
RC HS
GPIO PORT A
RC L S
PB[15:0]
GPIO PORT B
PC[15:0]
GPIO PORT C
PD[15:0]
GPIO PORT D
POR
reset
Int
Supply
supervision
POR/PDR
BOR
P L L1&2
NRST
@VDD
@VDDA
XTAL OSC
4- 16MHz
GPIO PORT E
GPIO PORT F
PWR
interface
FCLK
GPIO PORT G
PH[15:0]
TIM1 / PWM
TIM8 / PWM
2 channels as AF
1 channel as AF
TIM10
16b
1 channel as AF
TIM11
16b
USART1
smcard
irDA
USART6
MOSI, MISO,
SCK, NSS as AF
AHB/APB1
16b
16b
smcard
irDA
AHB/APB2
16b
TIM9
DMA1
DMA2
WWDG
SPI1
@VDDA
VDDREF_ADC
Temperature sensor
ADC1
ADC2
TIM6
16b
TIM7
16b
@VDDA
DAC1
ITF
DAC2
IF
A P B(max)
1 3 0 M Hz
APB142 MHz
OSC32_OUT
4 KB BKPSRAM
TIM2
32b
4 channels, ETR as AF
TIM3
16b
4 channels, ETR as AF
TIM4
16b
4 channels, ETR as AF
TIM5
32b
4 channels
TIM12
16b
2 channels as AF
TIM13
16b
1 channel as AF
TIM14
16b
1 channel as AF
USART2
smcard
irDA
RX, TX as AF
CTS, RTS as AF
USART3
smcard
irDA
RX, TX as AF
CTS, RTS as AF
UART4
RX, TX as AF
UART5
RX, TX as AF
as AF
SP3/I2S3
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
bxCAN2
DAC1_OUT
SP2/I2S2
bxCAN1
ADC3
RTC_AF1
RTC_AF1
AWU
Backup register
FIFO
LS
GPIO PORT I
APB2 84 MHz
D[7:0]
CMD, CK as AF
OSC32_IN
XTAL 32 kHz
RTC
FIFO
140 AF
LS
GPIO PORT H
PI[11:0]
OSC_OUT
IWDG
clockA G T
M AN
control
PCLKx
PF[15:0]
PG[15:0]
OSC_IN
Reset &
HCLKx
PE[15:0]
VDDA, VSSA
PVD
TX, RX
TX, RX
DAC2_OUT
as AF
ai18511d
1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration
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STM32F415xx, STM32F417xx
Description
2.2.1
Note:
2.2.2
2.2.3
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Description
2.2.4
STM32F415xx, STM32F417xx
2.2.5
2.2.6
Embedded SRAM
All STM32F41x products embed:
Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
2.2.7
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STM32F415xx, STM32F417xx
Description
Figure 6. Multi-AHB matrix
S2
S4
S5
S6
USB_HS_M
MAC
USB OTG
Ethernet
HS
ETHERNET_M
DMA_P2
DMA_MEM2
DMA_PI
DMA_MEM1
S3
GP
DMA2
S7
M0
ICODE
M1 DCODE
ACCEL
S1
GP
DMA1
S-bus
I-bus
S0
D-bus
ARM
Cortex-M4
64-Kbyte
CCM data RAM
Flash
memory
M2
SRAM1
112 Kbyte
M3
SRAM2
16 Kbyte
AHB1
peripherals
AHB2
peripherals
M4
M5
M6
APB1
APB2
FSMC
Static MemCtl
Bus matrix-S
ai18490c
2.2.8
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Description
STM32F415xx, STM32F417xx
The DMA can be used with the main peripherals:
2.2.9
I2C
USART
DAC
SDIO
Cryptographic acceleration
ADC.
Write FIFO
2.2.10
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.2.11
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STM32F415xx, STM32F417xx
Description
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
2.2.12
2.2.13
Boot modes
At startup, boot pins are used to select one out of three boot options:
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
2.2.14
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced
temperature range, and with the use of an external power supply supervisor (refer to
Section : Internal reset OFF).
Refer to Table 2 in order to identify the packages supporting this option.
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Description
2.2.15
STM32F415xx, STM32F417xx
PDR_ON
NRST
Application reset
signal (optional)
VDD
MS31383V3
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
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STM32F415xx, STM32F417xx
Description
The VDD specified threshold, below which the device must be maintained under reset, is
1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the
0 to 70 C temperature range.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
VBAT functionality is no more available and VBAT pin should be connected to VDD
All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset
through the PDR_ON signal.
Figure 8. PDR_ON and NRST control with internal reset OFF
V DD
time
Reset by other source than
power supply supervisor
NRST
PDR_ON
PDR_ON
time
MS19009V6
1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.
2.2.16
Voltage regulator
The regulator has four operating modes:
Regulator ON
Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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Description
STM32F415xx, STM32F417xx
There are three power modes configured by software when regulator is ON:
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
Refer to Table 14: General operating conditions.
Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to
Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions.
All packages have regulator ON feature.
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not manage internally, the external voltage value must
be aligned with the targetted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
Refer to Figure 21: Power supply scheme
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode the following features are no more supported:
26/186
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Description
Figure 9. Regulator OFF
V12
VDD
PA0
VDD
NRST
BYPASS_REG
V12
VCAP_1
VCAP_2
ai18498V4
Note:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see
Figure 11).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then
a reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application
(see Table 14: General operating conditions).
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Description
STM32F415xx, STM32F417xx
Figure 10. Startup in regulator OFF mode: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
VDD
PDR = 1.7 V or 1.8 V (2)
V12
Min V12
VCAP_1/VCAP_2
time
NRST
time
ai18491e
1. This figure is valid both whatever the internal reset mode (onON or OFFoff).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.
time
1. This figure is valid both whatever the internal reset mode (onON or offOFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.
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ai18492d
STM32F415xx, STM32F417xx
2.2.17
Description
Yes
LQFP144
LQFP176
WLCSP90
UFBGA176
2.2.18
Regulator OFF
Internal reset ON
Internal reset
OFF
Yes
No
Yes
PDR_ON set to
VDD
Yes
PDR_ON
connected to an
external power
supply supervisor
No
Yes
Yes
BYPASS_REG set BYPASS_REG set
to VDD
to VSS
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
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Description
STM32F415xx, STM32F417xx
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
2.2.19
Low-power modes
The STM32F415xx and STM32F417xx support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V12 domain is powered off. The PLL,
the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the V12 domain is controlled by an external power.
2.2.20
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.2.21
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STM32F415xx, STM32F417xx
Description
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Timer
type
Counter
Counter Prescaler
Timer resolutio
type
factor
n
16-bit
Up,
Any integer
Down,
between 1
Up/dow
and 65536
n
Yes
Yes
84
168
32-bit
Up,
Any integer
Down,
between 1
Up/dow
and 65536
n
Yes
No
42
84
TIM3,
TIM4
16-bit
Up,
Any integer
Down,
between 1
Up/dow
and 65536
n
Yes
No
42
84
TIM9
16-bit
Up
Any integer
between 1
and 65536
No
No
84
168
TIM10
,
TIM11
16-bit
Up
Any integer
between 1
and 65536
No
No
84
168
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
No
42
84
TIM13
,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
No
42
84
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
No
42
84
Advanced TIM1,
-control
TIM8
TIM2,
TIM5
General
purpose
Basic
DMA
Max
Max
Capture/
request
Complementar interface timer
compare
generatio
y output
clock
clock
channels
n
(MHz) (MHz)
Input capture
Output compare
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
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Description
STM32F415xx, STM32F417xx
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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STM32F415xx, STM32F417xx
Description
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
2.2.22
A 24-bit downcounter
Autoreload capability
2.2.23
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Description
STM32F415xx, STM32F417xx
Table 5. USART feature comparison
Max. baud rate Max. baud rate
Smartcard
in Mbit/s
in Mbit/s
(ISO 7816) (oversampling (oversampling
by 16)
by 8)
USART
name
Standard
features
Modem
(RTS/
CTS)
USART1
5.25
10.5
APB2
(max.
84 MHz)
USART2
2.62
5.25
APB1
(max.
42 MHz)
USART3
2.62
5.25
APB1
(max.
42 MHz)
UART4
2.62
5.25
APB1
(max.
42 MHz)
UART5
2.62
5.25
APB1
(max.
42 MHz)
USART6
5.25
10.5
APB2
(max.
84 MHz)
2.2.24
SPI
LIN
master
irDA
APB
mapping
2.2.25
2.2.26
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STM32F415xx, STM32F417xx
Description
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
2.2.27
2.2.28
Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral available only on the STM32F417xx devices.
The STM32F417xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The
STM32F417xx requires an external physical interface device (PHY) to connect to the
physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F417xx MII
port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz
(MII) from the STM32F417xx.
The STM32F417xx includes the following features:
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F40x reference manual for details)
Several address filtering modes for physical and multicast address (multicast and
group addresses)
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
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Description
2.2.29
STM32F415xx, STM32F417xx
2.2.30
2.2.31
Combined Rx and Tx FIFO size of 320 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
36/186
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
DocID022063 Rev 4
STM32F415xx, STM32F417xx
2.2.32
Description
2.2.33
Programmable polarity for the input pixel clock and synchronization signals
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Cryptographic acceleration
The STM32F415xx and STM32F417xx devices embed a cryptographic accelerator. This
cryptographic accelerator provides a set of hardware acceleration for the advanced
cryptographic algorithms usually needed to provide confidentiality, authentication, data
integrity and non repudiation when exchanging messages with a peer.
These algorithms consists of:
Encryption/Decryption
AES (advanced encryption standard): ECB, CBC and CTR (counter mode)
chaining algorithms, 128, 192 or 256-bit key
Universal hash
MD5
HMAC
2.2.34
2.2.35
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Description
2.2.36
STM32F415xx, STM32F417xx
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.2.37
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.2.38
noise-wave generation
triangular-wave generation
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.2.39
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STM32F415xx, STM32F417xx
Description
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.2.40
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STM32F415xx, STM32F417xx
VDD
VSS
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD
VCAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VCAP_1
VDD
VBAT
PC13
PC14
PC15
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0_WKUP
PA1
PA2
ai18493b
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STM32F415xx, STM32F417xx
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
LQFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD
VSS
VCAP_2
PA13
PA12
PA 11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP_1
VDD
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
VSS
VDD
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
ai18495c
DocID022063 Rev 4
41/186
STM32F415xx, STM32F417xx
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
VCAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
42/186
DocID022063 Rev 4
VCAP_1
VDD
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14
PC15
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
ai18496b
STM32F415xx, STM32F417xx
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
LQFP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
V
102
V
101
100
99
98
97
96
95
94
93
92
91
90
89
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PH4
PH5
PA3
BYPASS_REG
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP_1
VDD
PH6
PH7
PH8
PH9
PH10
PH11
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14
PC15
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0
PH1
NRST
PC0
PC1
PC2
PC3
VDDA
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
PH3
DocID022063 Rev 4
MS19916V3
43/186
STM32F415xx, STM32F417xx
Figure 16. STM32F41x UFBGA176 ballout
10
11
12
13
14
15
PE3
PE2
PE1
PE0
PB8
PB5
PG14
PG13
PB4
PB3
PD7
PC12
PA15
PA14
PA13
PE4
PE5
PE6
PB9
PB7
PB6
PG15
PG12
PG11
PG10
PD6
PD0
PC11
PC10
PA12
VBAT
PI7
PI6
PI5
VDD
PDR_ON
VDD
VDD
VDD
PG9
PD5
PD1
PI3
PI2
PA11
PC13
PI8
PI9
PI4
VSS
BOOT0
VSS
VSS
VSS
PD4
PD3
PD2
PH15
PI1
PA10
PC14
PF0
PI10
PI11
PH13
PH14
PI0
PA9
PC15
VSS
VDD
PH2
VSS
VSS
VSS
VSS
VSS
VSS
VCAP_2
PC9
PA8
PH0
VSS
VDD
PH3
VSS
VSS
VSS
VSS
VSS
VSS
VDD
PC8
PC7
PH1
PF2
PF1
PH4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
PG8
PC6
NRST
PF3
PF4
PH5
VSS
VSS
VSS
VSS
VSS
VDD
VDD
PG7
PG6
PF7
PF6
PF5
VDD
VSS
VSS
VSS
VSS
VSS
PH12
PG5
PG4
PG3
PF10
PF9
PF8
BYPASS_
REG
PH11
PH10
PD15
PG2
VSSA
PC0
PC1
PC2
PC3
PB2
PG1
VSS
VSS
PH6
PH8
PH9
PD14
PD13
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
VDD
VDD
VDD
PE13
PH7
PD12
PD11
PD10
VREF+
PA2
PA6
PA5
PC5
PF12
PF15
PE8
PE9
PE11
PE14
PB12
PB13
PD9
PD8
VDDA
PA3
PA7
PB1
PB0
PF11
PF14
PE7
PE10
PE12
PE15
PB10
PB11
PB14
PB15
VCAP_1
ai18497b
44/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
PC13
PDR_ON
BOOT0
PB4
PD7
PD4
PC12
PA14
VDD
PC15
VDD
PB7
PB3
PD6
PD2
PA15
PI1
VCAP_2
PA0
VSS
PB9
PB6
PD5
PD1
PC11
PI0
PA12
PA11
PC2
BYPASS_
REG
PB8
PB5
PD0
PC10
PA13
PA10
PA9
PA8
PC0
PC3
VSS
VSS
VDD
VSS
VDD
PC9
PC8
PC7
PH0
PH1
PA1
VDD
PE10
PE14
VCAP_1
PC6
PD14
PD15
NRST
VDDA
PA5
PB0
PE7
PE13
PE15
PD10
PD12
PD11
VSSA
PA3
PA6
PB1
PE8
PE12
PB10
PD9
PD8
PB15
PA2
PA4
PA7
PB2
PE9
PE11
PB11
PB12
PB14
PB13
VBAT
PC14
MS30402V1
Pin type
I/O structure
Notes
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I/O
FT
5 V tolerant I/O
TTa
RST
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Additional
functions
DocID022063 Rev 4
45/186
STM32F415xx, STM32F417xx
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
(function after
reset)(1)
Pin type
I / O structure
A2
PE2
I/O
FT
TRACECLK/ FSMC_A23 /
ETH_MII_TXD3 /
EVENTOUT
A1
PE3
I/O
FT
TRACED0/FSMC_A19 /
EVENTOUT
B1
PE4
I/O
FT
TRACED1/FSMC_A20 /
DCMI_D4/ EVENTOUT
B2
PE5
I/O
FT
TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6 /
EVENTOUT
B3
PE6
I/O
FT
TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7 /
EVENTOUT
A10
C1
VBAT
D2
PI8
I/O
FT
A9
D1
PC13
I/O
FT
B10
E1
PC14/OSC32_IN
I/O
(PC14)
FT
B9
F1
10
PC15/
OSC32_OUT
(PC15)
I/O
FT
D3
11
PI9
I/O
FT
CAN1_RX / EVENTOUT
E3
12
PI10
I/O
FT
ETH_MII_RX_ER /
EVENTOUT
E4
13
PI11
I/O
FT
OTG_HS_ULPI_DIR /
EVENTOUT
F2
14
VSS
F3
15
VDD
10
E2
16
PF0
I/O
FT
FSMC_A0 / I2C2_SDA /
EVENTOUT
46/186
Pin name
Notes
LQFP64
Pin number
Alternate functions
(2)(
3)
(2)
(3)
(2)(
3)
(2)(
3)
DocID022063 Rev 4
Additional functions
EVENTOUT
RTC_TAMP1,
RTC_TAMP2,
RTC_TS
EVENTOUT
RTC_OUT,
RTC_TAMP1,
RTC_TS
EVENTOUT
OSC32_IN(4)
EVENTOUT
OSC32_OUT(4)
STM32F415xx, STM32F417xx
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
(function after
reset)(1)
Pin type
I / O structure
11
H3
17
PF1
I/O
FT
FSMC_A1 / I2C2_SCL /
EVENTOUT
12
H2
18
PF2
I/O
FT
FSMC_A2 / I2C2_SMBA /
EVENTOUT
13
J2
19
PF3
I/O
FT
(4)
FSMC_A3/EVENTOUT
ADC3_IN9
FT
(4)
FSMC_A4/EVENTOUT
ADC3_IN14
FT
(4)
FSMC_A5/EVENTOUT
ADC3_IN15
14
J3
20
Pin name
PF4
I/O
Notes
LQFP64
Pin number
Alternate functions
Additional functions
15
K3
21
PF5
I/O
C9
10
16
G2
22
VSS
B8
11
17
G3
23
VDD
18
K2
24
PF6
I/O
FT
(4)
TIM10_CH1 /
FSMC_NIORD/
EVENTOUT
ADC3_IN4
19
K1
25
PF7
I/O
FT
(4)
TIM11_CH1/FSMC_NREG
/ EVENTOUT
ADC3_IN5
20
L3
26
PF8
I/O
FT
(4)
TIM13_CH1 /
FSMC_NIOWR/
EVENTOUT
ADC3_IN6
21
L2
27
PF9
I/O
FT
(4)
TIM14_CH1 / FSMC_CD/
EVENTOUT
ADC3_IN7
22
L1
28
PF10
I/O
FT
(4)
FSMC_INTR/ EVENTOUT
ADC3_IN8
F10 12
23
G1
29
PH0/OSC_IN
(PH0)
I/O
FT
EVENTOUT
OSC_IN(4)
F9
13
24
H1
30
PH1/OSC_OUT
(PH1)
I/O
FT
EVENTOUT
OSC_OUT(4)
G10 14
25
J1
31
NRST
I/O
RS
T
E10 15
26
M2
32
PC0
I/O
FT
(4)
OTG_HS_ULPI_STP/
EVENTOUT
ADC123_IN10
27
M3
33
PC1
I/O
FT
(4)
ETH_MDC/ EVENTOUT
ADC123_IN11
FT
(4)
SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
/I2S2ext_SD/ EVENTOUT
ADC123_IN12
16
10 D10 17
28
M4
34
PC2
I/O
DocID022063 Rev 4
47/186
STM32F415xx, STM32F417xx
11
E9
18
29
M5
35
PC3
I/O
19
30
G3
36
VDD
12 H10 20
31
M1
37
VSSA
N1
VREF
21
32
P1
38
VREF+
13
G9
22
33
R1
39
VDDA
14 C10 23
34
N3
40
PA0/WKUP
(PA0)
I/O
Notes
(function after
reset)(1)
I / O structure
Pin name
Pin type
LQFP176
UFBGA176
LQFP144
LQFP100
WLCSP90
LQFP64
Pin number
Alternate functions
Additional functions
FT
(4)
SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK/
EVENTOUT
ADC123_IN13
(5)
USART2_CTS/
UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR/
EVENTOUT
ADC123_IN1
ADC123_IN2
FT
24
35
N2
41
PA1
I/O
FT
(4)
USART2_RTS /
UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2/
EVENTOUT
16 J10 25
36
P2
42
PA2
I/O
FT
(4)
USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO/ EVENTOUT
15
F8
F4
43
PH2
I/O
FT
ETH_MII_CRS/EVENTOU
T
G4
44
PH3
I/O
FT
ETH_MII_COL/EVENTOU
T
H4
45
PH4
I/O
FT
I2C2_SCL /
OTG_HS_ULPI_NXT/
EVENTOUT
J4
46
PH5
I/O
FT
I2C2_SDA/ EVENTOUT
48/186
DocID022063 Rev 4
ADC123_IN0/WKUP(4
)
STM32F415xx, STM32F417xx
Notes
(function after
reset)(1)
Alternate functions
Additional functions
(4)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT
ADC123_IN3
I/O TTa
(4)
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
ADC12_IN4
/DAC_OUT1
I/O TTa
(4)
SPI1_SCK/
OTG_HS_ULPI_CK /
ADC12_IN5/DAC_OU
TIM2_CH1_ETR/
T2
TIM8_CH1N/ EVENTOUT
(4)
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK /
TIM3_CH1 / TIM1_BKIN/
EVENTOUT
ADC12_IN6
ADC12_IN7
17
H9
26
37
R2
47
PA3
I/O
18
E5
27
38
VSS
L4
48
BYPASS_REG
K4
49
VDD
D9
19
20
21
22
E4
J9
G8
H8
28
29
30
31
39
40
41
42
N4
P4
P3
50
51
52
PA4
PA5
PA6
I / O structure
Pin name
Pin type
LQFP176
UFBGA176
LQFP144
LQFP100
WLCSP90
LQFP64
Pin number
I/O
FT
FT
FT
23
J8
32
43
R3
53
PA7
I/O
FT
(4)
SPI1_MOSI/ TIM8_CH1N
/ TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT
24
33
44
N5
54
PC4
I/O
FT
(4)
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
ADC12_IN14
25
34
45
P5
55
PC5
I/O
FT
(4)
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
ADC12_IN15
(4)
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
ADC12_IN8
26
G7
35
46
R5
56
PB0
I/O
FT
DocID022063 Rev 4
49/186
STM32F415xx, STM32F417xx
Notes
57
PB1
I/O
FT
28
J7
37
48
M6
58
PB2/BOOT1
(PB2)
I/O
FT
EVENTOUT
49
R6
59
PF11
I/O
FT
DCMI_D12/ EVENTOUT
50
P6
60
PF12
I/O
FT
FSMC_A6/ EVENTOUT
51
M8
61
VSS
52
N8
62
VDD
53
N6
63
PF13
I/O
FT
FSMC_A7/ EVENTOUT
54
R7
64
PF14
I/O
FT
FSMC_A8/ EVENTOUT
55
P7
65
PF15
I/O
FT
FSMC_A9/ EVENTOUT
56
N7
66
PG0
I/O
FT
FSMC_A10/ EVENTOUT
57
M7
67
PG1
I/O
FT
FSMC_A11/ EVENTOUT
G6
38
58
R8
68
PE7
I/O
FT
FSMC_D4/TIM1_ETR/
EVENTOUT
H6
39
59
P8
69
PE8
I/O
FT
FSMC_D5/ TIM1_CH1N/
EVENTOUT
J6
40
60
P9
70
PE9
I/O
FT
FSMC_D6/TIM1_CH1/
EVENTOUT
61
M9
71
VSS
62
N9
72
VDD
F6
41
63
R9
73
PE10
I/O
FT
FSMC_D7/TIM1_CH2N/
EVENTOUT
J5
42
64
P10
74
PE11
I/O
FT
FSMC_D8/TIM1_CH2/
EVENTOUT
H5
43
65
R10
75
PE12
I/O
FT
FSMC_D9/TIM1_CH3N/
EVENTOUT
G5
44
66
N11
76
PE13
I/O
FT
FSMC_D10/TIM1_CH3/
EVENTOUT
50/186
Pin name
(function after
reset)(1)
Pin type
R4
LQFP176
47
UFBGA176
36
LQFP144
H7
TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
TIM1_CH3N/ EVENTOUT
LQFP100
27
(4)
WLCSP90
Alternate functions
LQFP64
I / O structure
Pin number
DocID022063 Rev 4
Additional functions
ADC12_IN9
STM32F415xx, STM32F417xx
WLCSP90
LQFP100
LQFP144
UFBGA176
LQFP176
(function after
reset)(1)
Pin type
I / O structure
F5
45
67
P11
77
PE14
I/O
FT
FSMC_D11/TIM1_CH4/
EVENTOUT
G4
46
68
R11
78
PE15
I/O
FT
FSMC_D12/TIM1_BKIN/
EVENTOUT
FT
SPI2_SCK / I2S2_CK /
I2C2_SCL/ USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
TIM2_CH3/ EVENTOUT
FT
I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
TIM2_CH4/ EVENTOUT
29
H4
47
69
R12
79
Pin name
PB10
I/O
Notes
LQFP64
Pin number
Alternate functions
30
J4
48
70
R13
80
PB11
I/O
31
F4
49
71
M10
81
VCAP_1
32
50
72
N10
82
VDD
M11
83
PH6
I/O
FT
I2C2_SMBA / TIM12_CH1
/ ETH_MII_RXD2/
EVENTOUT
N12
84
PH7
I/O
FT
I2C3_SCL /
ETH_MII_RXD3/
EVENTOUT
M12
85
PH8
I/O
FT
I2C3_SDA /
DCMI_HSYNC/
EVENTOUT
M13
86
PH9
I/O
FT
I2C3_SMBA /
TIM12_CH2/ DCMI_D0/
EVENTOUT
L13
87
PH10
I/O
FT
TIM5_CH1 / DCMI_D1/
EVENTOUT
L12
88
PH11
I/O
FT
TIM5_CH2 / DCMI_D2/
EVENTOUT
K12
89
PH12
I/O
FT
TIM5_CH3 / DCMI_D3/
EVENTOUT
H12
90
VSS
J12
91
VDD
DocID022063 Rev 4
Additional functions
51/186
STM32F415xx, STM32F417xx
33
34
35
J3
J1
J2
51
52
53
73
74
75
P12
P13
R14
92
93
94
PB12
PB13
PB14
I/O
I/O
I/O
Notes
(function after
reset)(1)
I / O structure
Pin name
Pin type
LQFP176
UFBGA176
LQFP144
LQFP100
WLCSP90
LQFP64
Pin number
Alternate functions
FT
SPI2_NSS / I2S2_WS /
I2C2_SMBA/
USART3_CK/ TIM1_BKIN
/ CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT
FT
SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT
FT
SPI2_MISO/ TIM1_CH2N
/ TIM12_CH1 /
OTG_HS_DM/
USART3_RTS /
TIM8_CH2N/I2S2ext_SD/
EVENTOUT
36
H1
54
76
R15
95
PB15
I/O
FT
SPI2_MOSI / I2S2_SD/
TIM1_CH3N / TIM8_CH3N
/ TIM12_CH2 /
OTG_HS_DP/
EVENTOUT
H2
55
77
P15
96
PD8
I/O
FT
FSMC_D13 /
USART3_TX/ EVENTOUT
H3
56
78
P14
97
PD9
I/O
FT
FSMC_D14 /
USART3_RX/ EVENTOUT
G3
57
79
N15
98
PD10
I/O
FT
FSMC_D15 /
USART3_CK/ EVENTOUT
G1
58
80
N14
99
PD11
I/O
FT
FSMC_CLE /
FSMC_A16/USART3_CT
S/ EVENTOUT
FT
FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/
EVENTOUT
G2
52/186
59
81
N13 100
PD12
I/O
DocID022063 Rev 4
Additional functions
OTG_HS_VBUS
RTC_REFIN
STM32F415xx, STM32F417xx
FT
FSMC_A18/TIM4_CH2/
EVENTOUT
I/O
FT
FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT
PD15
I/O
FT
FSMC_D1/TIM4_CH4/
EVENTOUT
L15 106
PG2
I/O
FT
FSMC_A12/ EVENTOUT
88
K15 107
PG3
I/O
FT
FSMC_A13/ EVENTOUT
89
K14 108
PG4
I/O
FT
FSMC_A14/ EVENTOUT
90
K13 109
PG5
I/O
FT
FSMC_A15/ EVENTOUT
91
J15 110
PG6
I/O
FT
FSMC_INT2/ EVENTOUT
92
J14
111
PG7
I/O
FT
FSMC_INT3
/USART6_CK/
EVENTOUT
93
H14 112
PG8
I/O
FT
USART6_RTS /
ETH_PPS_OUT/
EVENTOUT
94
G12 113
VSS
95
H13 114
VDD
FT
I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT
WLCSP90
LQFP100
LQFP144
60
82
83
84
J13 103
VDD
F2
61
85
M14 104
PD14
F1
62
86
L14 105
87
37
F3
63
96
LQFP176
LQFP64
Pin name
(function after
reset)(1)
PD13
102
VSS
M15 101
-
H15 115
PC6
I/O
Notes
I / O structure
I/O
UFBGA176
Pin type
Pin number
Alternate functions
38
E1
64
97
G15 116
PC7
I/O
FT
I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT
39
E2
65
98
G14 117
PC8
I/O
FT
TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK
/ DCMI_D2/ EVENTOUT
DocID022063 Rev 4
Additional functions
53/186
STM32F415xx, STM32F417xx
40
E3
66
99
F14 118
PC9
I/O
Notes
(function after
reset)(1)
I / O structure
Pin name
Pin type
LQFP176
UFBGA176
LQFP144
LQFP100
WLCSP90
LQFP64
Pin number
Alternate functions
FT
I2S_CKIN/ MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4/ EVENTOUT
41
D1
PA8
I/O
FT
MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF/
EVENTOUT
42
D2
PA9
I/O
FT
USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0/
EVENTOUT
43
D3
PA10
I/O
FT
USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT
FT
USART1_CTS / CAN1_RX
/ TIM1_CH4 /
OTG_FS_DM/
EVENTOUT
44
C1
PA11
I/O
45
C2
PA12
I/O
FT
USART1_RTS /
CAN1_TX/ TIM1_ETR/
OTG_FS_DP/
EVENTOUT
46
D4
PA13
(JTMS-SWDIO)
I/O
FT
JTMS-SWDIO/
EVENTOUT
47
B1
VCAP_2
E7
VSS
48
E6
VDD
E12 128
PH13
I/O
FT
TIM8_CH1N / CAN1_TX/
EVENTOUT
E13 129
PH14
I/O
FT
TIM8_CH2N / DCMI_D4/
EVENTOUT
D13 130
PH15
I/O
FT
TIM8_CH3N / DCMI_D11/
EVENTOUT
C3
E14 131
PI0
I/O
FT
TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13/
EVENTOUT
54/186
DocID022063 Rev 4
Additional functions
OTG_FS_VBUS
STM32F415xx, STM32F417xx
LQFP144
Pin type
I / O structure
D14 132
PI1
I/O
FT
SPI2_SCK / I2S2_CK /
DCMI_D8/ EVENTOUT
C14 133
PI2
I/O
FT
TIM8_CH4 /SPI2_MISO /
DCMI_D9 / I2S2ext_SD/
EVENTOUT
C13 134
PI3
I/O
FT
TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10/
EVENTOUT
D9
135
VSS
C9
136
VDD
49
A2
PA14
(JTCK/SWCLK)
I/O
FT
JTCK-SWCLK/
EVENTOUT
PA15
(JTDI)
FT
JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ET
R / SPI1_NSS /
EVENTOUT
FT
SPI3_SCK / I2S3_CK/
UART4_TX/SDIO_D2 /
DCMI_D8 / USART3_TX/
EVENTOUT
FT
UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX /
I2S3ext_SD/ EVENTOUT
50
51
52
B3
D5
C4
Pin name
(function after
reset)(1)
PC10
PC11
I/O
I/O
I/O
Notes
LQFP100
B2
LQFP176
WLCSP90
UFBGA176
LQFP64
Pin number
Alternate functions
53
A3
PC12
I/O
FT
UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI
/I2S3_SD / USART3_CK/
EVENTOUT
D6
PD0
I/O
FT
FSMC_D2/CAN1_RX/
EVENTOUT
C5
PD1
I/O
FT
FSMC_D3 / CAN1_TX/
EVENTOUT
54
B4
PD2
I/O
FT
TIM3_ETR/UART5_RX/
SDIO_CMD / DCMI_D11/
EVENTOUT
DocID022063 Rev 4
Additional functions
55/186
STM32F415xx, STM32F417xx
I / O structure
I/O
FT
FSMC_CLK/
USART2_CTS/
EVENTOUT
A4
PD4
I/O
FT
FSMC_NOE/
USART2_RTS/
EVENTOUT
C6
PD5
I/O
FT
FSMC_NWE/USART2_TX
/ EVENTOUT
120
D8
148
VSS
121
C8
149
VDD
B5
PD6
I/O
FT
FSMC_NWAIT/
USART2_RX/ EVENTOUT
A5
PD7
I/O
FT
USART2_CK/FSMC_NE1/
FSMC_NCE2/
EVENTOUT
PG9
I/O
FT
USART6_RX /
FSMC_NE2/FSMC_NCE3
/ EVENTOUT
PG10
I/O
FT
FSMC_NCE4_1/
FSMC_NE3/ EVENTOUT
Pin name
(function after
reset)(1)
Notes
Pin type
PD3
LQFP176
UFBGA176
LQFP144
WLCSP90
LQFP100
LQFP64
Pin number
Alternate functions
126
B9
154
PG11
I/O
FT
FSMC_NCE4_2 /
ETH_MII_TX_EN/
ETH _RMII_TX_EN/
EVENTOUT
127
B8
155
PG12
I/O
FT
FSMC_NE4 /
USART6_RTS/
EVENTOUT
FT
FSMC_A24 /
USART6_CTS
/ETH_MII_TXD0/
ETH_RMII_TXD0/
EVENTOUT
FT
FSMC_A25 / USART6_TX
/ETH_MII_TXD1/
ETH_RMII_TXD1/
EVENTOUT
56/186
128
129
A8
A7
156
157
PG13
PG14
I/O
I/O
DocID022063 Rev 4
Additional functions
STM32F415xx, STM32F417xx
LQFP100
LQFP144
UFBGA176
LQFP176
E8
130
D7
158
VSS
F7
131
C7
159
VDD
132
B7
160
PG15
I/O
55
B6
56
A6
90 134
57
58
D7
C7
91 135
92 136
A9
A6
B6
162
163
164
USART6_CTS /
DCMI_D13/ EVENTOUT
PB3
(JTDO/
TRACESWO)
I/O
FT
JTDO/ TRACESWO/
SPI3_SCK / I2S3_CK /
TIM2_CH2 / SPI1_SCK/
EVENTOUT
PB4
(NJTRST)
I/O
FT
NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO /
I2S3ext_SD/ EVENTOUT
FT
I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH
2 / SPI1_MOSI/
SPI3_MOSI / DCMI_D10 /
I2S3_SD/ EVENTOUT
FT
I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
DCMI_D5/USART1_TX/
EVENTOUT
I2C1_SDA / FSMC_NL /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2/
EVENTOUT
PB5
PB6
I/O
I/O
B7
93 137
B5
165
PB7
I/O
FT
60
A7
94 138
D6
166
BOOT0
62
D8
C8
95 139
96 140
A5
B4
167
168
Alternate functions
FT
59
61
Notes
WLCSP90
(function after
reset)(1)
I / O structure
LQFP64
Pin name
Pin type
Pin number
PB8
PB9
I/O
I/O
Additional functions
VPP
FT
TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
ETH_MII_TXD3 /
I2C1_SCL/ CAN1_RX/
EVENTOUT
FT
SPI2_NSS/ I2S2_WS /
TIM4_CH4/ TIM11_CH1/
SDIO_D5 / DCMI_D7 /
I2C1_SDA / CAN1_TX/
EVENTOUT
DocID022063 Rev 4
57/186
STM32F415xx, STM32F417xx
LQFP176
Pin type
I / O structure
97 141
A4
169
PE0
I/O
FT
TIM4_ETR / FSMC_NBL0
/ DCMI_D2/ EVENTOUT
98 142
A3
170
PE1
I/O
FT
FSMC_NBL1 / DCMI_D3/
EVENTOUT
63
99
D5
VSS
A8
143
C6
171
PDR_ON
64
A1
10
144
0
C5
172
VDD
D4
173
PI4
I/O
FT
TIM8_BKIN / DCMI_D5/
EVENTOUT
C4
174
PI5
I/O
FT
TIM8_CH1 /
DCMI_VSYNC/
EVENTOUT
C3
175
PI6
I/O
FT
TIM8_CH2 / DCMI_D6/
EVENTOUT
C2
176
PI7
I/O
FT
TIM8_CH3 / DCMI_D7/
EVENTOUT
Pin name
Notes
UFBGA176
LQFP144
WLCSP90
(function after
reset)(1)
LQFP100
LQFP64
Pin number
Alternate functions
Additional functions
FT
58/186
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
LQFP100(2)
PE2
A23
A23
Yes
PE3
A19
A19
Yes
DocID022063 Rev 4
WLCSP90
(2)
STM32F415xx, STM32F417xx
Pins
(1)
CF
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
LQFP100(2)
PE4
A20
A20
Yes
PE5
A21
A21
Yes
PE6
A22
A22
Yes
WLCSP90
(2)
PF0
A0
A0
PF1
A1
A1
PF2
A2
A2
PF3
A3
A3
PF4
A4
A4
PF5
A5
A5
PF6
NIORD
PF7
NREG
PF8
NIOWR
PF9
CD
PF10
INTR
PF12
A6
A6
PF13
A7
A7
PF14
A8
A8
PF15
A9
A9
PG0
A10
A10
A11
PG1
PE7
D4
D4
DA4
D4
Yes
Yes
PE8
D5
D5
DA5
D5
Yes
Yes
PE9
D6
D6
DA6
D6
Yes
Yes
PE10
D7
D7
DA7
D7
Yes
Yes
PE11
D8
D8
DA8
D8
Yes
Yes
PE12
D9
D9
DA9
D9
Yes
Yes
PE13
D10
D10
DA10
D10
Yes
Yes
PE14
D11
D11
DA11
D11
Yes
Yes
PE15
D12
D12
DA12
D12
Yes
Yes
PD8
D13
D13
DA13
D13
Yes
Yes
PD9
D14
D14
DA14
D14
Yes
Yes
PD10
D15
D15
DA15
D15
Yes
Yes
A16
A16
CLE
Yes
Yes
PD11
DocID022063 Rev 4
59/186
STM32F415xx, STM32F417xx
Table 8. FSMC pin definition (continued)
FSMC
Pins
(1)
CF
NOR/PSRAM/
NOR/PSRAM Mux NAND 16 bit
SRAM
PD12
A17
A17
PD13
A18
A18
ALE
LQFP100(2)
WLCSP90
Yes
Yes
(2)
Yes
PD14
D0
D0
DA0
D0
Yes
Yes
PD15
D1
D1
DA1
D1
Yes
Yes
PG2
A12
PG3
A13
PG4
A14
PG5
A15
PG6
INT2
PG7
INT3
PD0
D2
D2
DA2
D2
Yes
Yes
PD1
D3
D3
DA3
D3
Yes
Yes
CLK
CLK
PD3
Yes
PD4
NOE
NOE
NOE
NOE
Yes
Yes
PD5
NWE
NWE
NWE
NWE
Yes
Yes
PD6
NWAIT
NWAIT
NWAIT
NWAIT
Yes
Yes
PD7
NE1
NE1
NCE2
Yes
Yes
PG9
NE2
NE2
NCE3
NE3
NE3
PG10
NCE4_1
PG11
NCE4_2
PG12
NE4
NE4
PG13
A24
A24
PG14
A25
A25
PB7
NADV
NADV
Yes
Yes
PE0
NBL0
NBL0
Yes
PE1
NBL1
NBL1
Yes
1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on
smaller packages are given in the dedicated package column.
2. Ports F and G are not available in devices delivered in 100-pin packages.
60/186
DocID022063 Rev 4
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
PA0
TIM2_CH1_E
TR
TIM 5_CH1
TIM8_ETR
USART2_CTS
UART4_TX
ETH_MII_CRS
EVENTOUT
PA1
TIM2_CH2
TIM5_CH2
USART2_RTS
UART4_RX
ETH_MII
_RX_CLK
ETH_RMII__REF
_CLK
EVENTOUT
PA2
TIM2_CH3
TIM5_CH3
ETH_MDIO
EVENTOUT
ETH _MII_COL
EVENTOUT
Port
PA3
TIM2_CH4
TIM5_CH4
TIM9_CH1
USART2_TX
TIM9_CH2
USART2_RX
PA4
DocID022063 Rev 4
Port A
SPI1_NSS
PA5
TIM2_CH1_E
TR
PA6
TIM1_BKIN
PA7
PA8
TIM1_CH1N
MCO1
PA9
TIM3_CH1
TIM3_CH2
OTG_HS_ULPI_
D0
TIM8_CH1N
SPI1_SCK
TIM8_BKIN
SPI1_MISO
TIM8_CH1N
SPI3_NSS
I2S3_WS
OTG_HS_SO
F
USART2_CK
AF14
DCMI_HSYN
C
OTG_HS_ULPI_
CK
DCMI_PIXCK
ETH_MII _RX_DV
ETH_RMII
_CRS_DV
TIM14_CH1
TIM1_CH1
I2C3_SCL
USART1_CK
TIM1_CH2
I2C3_SMB
A
USART1_TX
EVENTOUT
EVENTOUT
OTG_FS_SOF
OTG_FS_ID
EVENTOUT
EVENTOUT
TIM13_CH1
SPI1_MOSI
AF15
EVENTOUT
DCMI_D0
EVENTOUT
DCMI_D1
EVENTOUT
PA10
TIM1_CH3
USART1_RX
PA11
TIM1_CH4
USART1_CTS
CAN1_RX
OTG_FS_DM
EVENTOUT
PA12
TIM1_ETR
USART1_RTS
CAN1_TX
OTG_FS_DP
EVENTOUT
JTMSSWDIO
EVENTOUT
PA14
JTCKSWCLK
EVENTOUT
PA15
JTDI
SPI1_NSS
SPI3_NSS/
I2S3_WS
EVENTOUT
61/186
PA13
TIM 2_CH1
TIM 2_ETR
STM32F415xx, STM32F417xx
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
PB0
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
OTG_HS_ULPI_
D1
ETH _MII_RXD2
EVENTOUT
PB1
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
OTG_HS_ULPI_
D2
ETH _MII_RXD3
EVENTOUT
Port
AF14
PB2
DocID022063 Rev 4
Port B
EVENTOUT
PB3
JTDO/
TRACES
WO
PB4
NJTRST
TIM2_CH2
TIM3_CH1
SPI1_SCK
SPI3_SCK
I2S3_CK
SPI1_MISO
SPI3_MISO
SPI1_MOSI
SPI3_MOSI
I2S3_SD
EVENTOUT
I2S3ext_SD
PB5
TIM3_CH2
I2C1_SMB
A
PB6
TIM4_CH1
I2C1_SCL
USART1_TX
PB7
TIM4_CH2
I2C1_SDA
USART1_RX
PB8
TIM4_CH3
TIM10_CH1
I2C1_SCL
PB9
TIM4_CH4
TIM11_CH1
I2C1_SDA
SPI2_NSS
I2S2_WS
SPI2_SCK
I2S2_CK
CAN2_RX
OTG_HS_ULPI_
D7
I2C2_SCL
PB11
TIM2_CH4
I2C2_SDA
PB12
TIM1_BKIN
I2C2_SMB
A
PB13
TIM1_CH1N
PB14
TIM1_CH2N
TIM8_CH2N
SPI2_MISO
TIM1_CH3N
TIM8_CH3N
SPI2_MOSI
I2S2_SD
ETH _PPS_OUT
DCMI_D10
EVENTOUT
DCMI_D5
EVENTOUT
FSMC_NL
DCMI_VSYN
C
EVENTOUT
SDIO_D4
DCMI_D6
EVENTOUT
SDIO_D5
DCMI_D7
EVENTOUT
CAN2_TX
ETH _MII_TXD3
CAN1_TX
USART3_TX
OTG_HS_ULPI_
D3
ETH_ MII_RX_ER
EVENTOUT
USART3_RX
OTG_HS_ULPI_
D4
ETH _MII_TX_EN
ETH
_RMII_TX_EN
EVENTOUT
SPI2_NSS
I2S2_WS
USART3_CK
CAN2_RX
OTG_HS_ULPI_
D5
ETH _MII_TXD0
ETH _RMII_TXD0
SPI2_SCK
I2S2_CK
USART3_CTS
CAN2_TX
OTG_HS_ULPI_
D6
ETH _MII_TXD1
ETH _RMII_TXD1
USART3_RTS
TIM12_CH1
OTG_HS_DM
EVENTOUT
TIM12_CH2
OTG_HS_DP
EVENTOUT
I2S2ext_SD
OTG_HS_ID
EVENTOUT
EVENTOUT
STM32F415xx, STM32F417xx
TIM2_CH3
RTC_
REFIN
EVENTOUT
CAN1_RX
PB10
PB15
AF15
62/186
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
OTG_HS_ULPI_
STP
PC0
PC1
Port C
AF14
AF15
EVENTOUT
ETH_MDC
EVENTOUT
OTG_HS_ULPI_
DIR
ETH _MII_TXD2
EVENTOUT
OTG_HS_ULPI_
NXT
ETH
_MII_TX_CLK
EVENTOUT
PC4
ETH_MII_RXD0
ETH_RMII_RXD0
EVENTOUT
PC5
ETH _MII_RXD1
ETH _RMII_RXD1
EVENTOUT
PC2
SPI2_MISO
PC3
SPI2_MOSI
I2S2_SD
DocID022063 Rev 4
PC6
TIM3_CH1
TIM8_CH1
PC7
TIM3_CH2
TIM8_CH2
PC8
TIM3_CH3
TIM8_CH3
TIM3_CH4
TIM8_CH4
PC9
MCO2
I2S2_MCK
PC12
USART6_TX
I2S3_MCK
I2C3_SDA
I2S3ext_SD
SDIO_D6
DCMI_D0
EVENTOUT
USART6_RX
SDIO_D7
DCMI_D1
EVENTOUT
USART6_CK
SDIO_D0
DCMI_D2
EVENTOUT
SDIO_D1
DCMI_D3
EVENTOUT
I2S_CKIN
PC10
PC11
I2S2ext_SD
SPI3_SCK/
I2S3_CK
USART3_TX/
UART4_TX
SDIO_D2
DCMI_D8
EVENTOUT
SPI3_MISO/
USART3_RX
UART4_RX
SDIO_D3
DCMI_D4
EVENTOUT
SPI3_MOSI
I2S3_SD
USART3_CK
UART5_TX
SDIO_CK
DCMI_D9
EVENTOUT
PC13
EVENTOUT
PC14
EVENTOUT
PC15
EVENTOUT
STM32F415xx, STM32F417xx
63/186
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
PD0
CAN1_RX
PD1
PD2
CAN1_TX
TIM3_ETR
UART5_RX
AF14
FSMC_D2
EVENTOUT
FSMC_D3
SDIO_CMD
AF15
EVENTOUT
DCMI_D11
EVENTOUT
PD3
USART2_CTS
FSMC_CLK
EVENTOUT
PD4
USART2_RTS
FSMC_NOE
EVENTOUT
PD5
USART2_TX
FSMC_NWE
EVENTOUT
PD6
USART2_RX
FSMC_NWAIT
EVENTOUT
PD7
USART2_CK
FSMC_NE1/
FSMC_NCE2
EVENTOUT
Port D
DocID022063 Rev 4
PD8
USART3_TX
FSMC_D13
EVENTOUT
PD9
USART3_RX
FSMC_D14
EVENTOUT
PD10
USART3_CK
FSMC_D15
EVENTOUT
PD11
USART3_CTS
FSMC_A16
EVENTOUT
USART3_RTS
FSMC_A17
EVENTOUT
PD12
TIM4_CH1
PD13
TIM4_CH2
FSMC_A18
EVENTOUT
PD14
TIM4_CH3
FSMC_D0
EVENTOUT
PD15
TIM4_CH4
FSMC_D1
EVENTOUT
64/186
STM32F415xx, STM32F417xx
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
FSMC_NBL0
DCMI_D2
EVENTOUT
FSMC_NBL1
DCMI_D3
EVENTOUT
Port
PE0
TIM4_ETR
PE1
Port E
AF14
AF15
PE2
TRACECL
K
PE3
TRACED0
FSMC_A19
PE4
TRACED1
FSMC_A20
DCMI_D4
EVENTOUT
PE5
TRACED2
TIM9_CH1
FSMC_A21
DCMI_D6
EVENTOUT
PE6
TRACED3
TIM9_CH2
FSMC_A22
DCMI_D7
ETH _MII_TXD3
FSMC_A23
EVENTOUT
EVENTOUT
STM32F415xx, STM32F417xx
EVENTOUT
DocID022063 Rev 4
PE7
TIM1_ETR
FSMC_D4
EVENTOUT
PE8
TIM1_CH1N
FSMC_D5
EVENTOUT
PE9
TIM1_CH1
FSMC_D6
EVENTOUT
PE10
TIM1_CH2N
FSMC_D7
EVENTOUT
PE11
TIM1_CH2
FSMC_D8
EVENTOUT
PE12
TIM1_CH3N
FSMC_D9
EVENTOUT
PE13
TIM1_CH3
FSMC_D10
EVENTOUT
PE14
TIM1_CH4
FSMC_D11
EVENTOUT
PE15
TIM1_BKIN
FSMC_D12
EVENTOUT
65/186
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
AF14
AF15
PF0
I2C2_SDA
FSMC_A0
EVENTOUT
PF1
I2C2_SCL
FSMC_A1
EVENTOUT
PF2
I2C2_
SMBA
FSMC_A2
EVENTOUT
PF3
FSMC_A3
EVENTOUT
PF4
FSMC_A4
EVENTOUT
PF5
FSMC_A5
EVENTOUT
PF6
TIM10_CH1
FSMC_NIORD
EVENTOUT
PF7
TIM11_CH1
FSMC_NREG
EVENTOUT
FSMC_
NIOWR
EVENTOUT
66/186
Port F
DocID022063 Rev 4
PF8
TIM13_CH1
PF9
TIM14_CH1
PF10
FSMC_CD
EVENTOUT
FSMC_INTR
EVENTOUT
PF11
DCMI_D12
EVENTOUT
PF12
FSMC_A6
EVENTOUT
PF13
FSMC_A7
EVENTOUT
PF14
FSMC_A8
EVENTOUT
PF15
FSMC_A9
EVENTOUT
STM32F415xx, STM32F417xx
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
PG0
Port G
AF14
AF15
FSMC_A10
EVENTOUT
PG1
FSMC_A11
EVENTOUT
PG2
FSMC_A12
EVENTOUT
PG3
FSMC_A13
EVENTOUT
PG4
FSMC_A14
EVENTOUT
PG5
FSMC_A15
EVENTOUT
PG6
FSMC_INT2
EVENTOUT
FSMC_INT3
EVENTOUT
PG7
USART6_CK
PG8
USART6_
RTS
PG9
USART6_RX
ETH _PPS_OUT
DocID022063 Rev 4
PG10
ETH _MII_TX_EN
ETH _RMII_
TX_EN
PG11
STM32F415xx, STM32F417xx
EVENTOUT
FSMC_NE2/
FSMC_NCE3
EVENTOUT
FSMC_
NCE4_1/
FSMC_NE3
EVENTOUT
FSMC_NCE4_
2
EVENTOUT
FSMC_NE4
EVENTOUT
PG12
USART6_
RTS
PG13
UART6_CTS
ETH _MII_TXD0
ETH _RMII_TXD0
FSMC_A24
EVENTOUT
PG14
USART6_TX
ETH _MII_TXD1
ETH _RMII_TXD1
FSMC_A25
EVENTOUT
PG15
USART6_
CTS
DCMI_D13
EVENTOUT
67/186
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
AF14
PH0
AF15
EVENTOUT
PH1
EVENTOUT
PH2
PH3
PH4
I2C2_SDA
PH6
I2C2_SMB
A
PH7
I2C3_SCL
EVENTOUT
ETH _MII_COL
EVENTOUT
OTG_HS_ULPI_
NXT
I2C2_SCL
PH5
ETH _MII_CRS
EVENTOUT
EVENTOUT
TIM12_CH1
ETH _MII_RXD2
68/186
EVENTOUT
ETH _MII_RXD3
EVENTOUT
Port H
DocID022063 Rev 4
PH8
I2C3_SDA
PH9
I2C3_SMB
A
TIM12_CH2
DCMI_HSYN
C
EVENTOUT
DCMI_D0
EVENTOUT
PH10
TIM5_CH1
DCMI_D1
EVENTOUT
PH11
TIM5_CH2
DCMI_D2
EVENTOUT
PH12
TIM5_CH3
DCMI_D3
EVENTOUT
PH13
TIM8_CH1N
PH14
TIM8_CH2N
CAN1_TX
DCMI_D4
EVENTOUT
EVENTOUT
PH15
TIM8_CH3N
DCMI_D11
EVENTOUT
STM32F415xx, STM32F417xx
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/1
1
I2C1/2/3
SPI1/SPI2/
I2S2/I2S2ext
SPI3/I2Sext/
I2S3
USART1/2/3/
I2S3ext
UART4/5/
USART6
CAN1/
CAN2/
TIM12/13/14
OTG_FS/
OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
Port
PI0
TIM5_CH4
PI1
PI2
Port I
AF14
AF15
SPI2_NSS
I2S2_WS
DCMI_D13
EVENTOUT
SPI2_SCK
I2S2_CK
DCMI_D8
EVENTOUT
DCMI_D9
EVENTOUT
DCMI_D10
EVENTOUT
TIM8_CH4
SPI2_MISO
PI3
TIM8_ETR
SPI2_MOSI
I2S2_SD
I2S2ext_SD
PI4
TIM8_BKIN
DCMI_D5
EVENTOUT
PI5
TIM8_CH1
DCMI_
VSYNC
EVENTOUT
PI6
TIM8_CH2
DCMI_D6
EVENTOUT
PI7
TIM8_CH3
DCMI_D7
EVENTOUT
PI8
DocID022063 Rev 4
PI9
EVENTOUT
CAN1_RX
EVENTOUT
PI10
PI11
STM32F415xx, STM32F417xx
ETH _MII_RX_ER
OTG_HS_ULPI_
DIR
EVENTOUT
EVENTOUT
69/186
Memory mapping
STM32F415xx, STM32F417xx
Memory mapping
The memory map is shown in Figure 18.
Figure 18. STM32F41x memory map
Reserved
CORTEX-M4 internal peripherals
Reserved
AHB3
Reserved
AHB2
0xFFFF FFFF
0xE000 0000
0xDFFF FFFF
512-Mbyte
block 7
Cortex-M4's
internal
peripherals
Reserved
0x5000 0000
0x4008 0000 - 0x4FFF FFFF
0x4007 FFFF
512-Mbyte
block 6
Not used
0xC000 0000
0xBFFF FFFF
AHB1
512-Mbyte
block 5
FSMC registers
0xA000 0000
0x9FFF FFFF
512-Mbyte
block 4
FSMC bank 3
& bank4
Reserved
0x4002 000
0x4001 5800 - 0x4001 FFFF
0x4001 57FF
0x8000 0000
0x7FFF FFFF
0x6000 0000
0x5FFF FFFF
512-Mbyte
block 3
FSMC bank1
& bank2
512-Mbyte
block 2
Peripherals
APB2
0x4000 0000
0x3FFF FFFF
512-Mbyte
block 1
SRAM
0x2000 0000
0x1FFF FFFF
512-Mbyte
block 0
Code
0x0000 0000
Reserved
SRAM (16 KB aliased
by bit-banding)
SRAM (112 KB aliased
by bit-banding)
Reserved
Option Bytes
Reserved
System memory + OTP
Reserved
CCM data RAM
(64 KB data SRAM)
Reserved
Flash
Reserved
Aliased to Flash, system
memory or SRAM depending
on the BOOT pins
Reserved
0x4001 0000
0x4000 7800 - 0x4000 FFFF
0x4000 7FFF
ai18513f
70/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Memory mapping
Cortex-M4
AHB3
AHB2
Boundary address
Peripheral
Reserved
Reserved
FSMC bank 4
FSMC bank 3
FSMC bank 2
FSMC bank 1
Reserved
RNG
HASH
CRYP
Reserved
DCMI
Reserved
USB OTG FS
Reserved
DocID022063 Rev 4
71/186
Memory mapping
STM32F415xx, STM32F417xx
Table 10. STM32F41x register boundary addresses (continued)
Bus
Boundary address
Peripheral
USB OTG HS
Reserved
ETHERNET MAC
AHB1
72/186
Reserved
DMA2
DMA1
Reserved
BKPSRAM
RCC
Reserved
CRC
Reserved
GPIOI
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Memory mapping
APB2
Boundary address
Peripheral
Reserved
TIM11
TIM10
TIM9
EXTI
SYSCFG
Reserved
SPI1
SDIO
Reserved
Reserved
USART6
USART1
Reserved
TIM8
TIM1
Reserved
DocID022063 Rev 4
73/186
Memory mapping
STM32F415xx, STM32F417xx
Table 10. STM32F41x register boundary addresses (continued)
Bus
APB1
74/186
Boundary address
Peripheral
Reserved
DAC
PWR
Reserved
CAN2
CAN1
Reserved
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
IWDG
WWDG
Reserved
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the
1.8 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 19.
5.1.5
STM32F pin
STM32F pin
C = 50 pF
VIN
MS19010V1
MS19011V1
DocID022063 Rev 4
75/186
Electrical characteristics
5.1.6
STM32F415xx, STM32F417xx
GPIOs
IN
VCAP_1
VCAP_2
2 2.2 F
VDD
1/2/...14/15
VSS
1/2/...14/15
15 100 nF
+ 1 4.7 F
Level shifter
OUT
VDD
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers,
backup RAM)
Power
switch
IO
Logic
Kernel logic
(CPU, digital
& RAM)
Voltage
regulator
Flash memory
BYPASS_REG
PDR_ON
VDD
VDDA
VREF
100 nF
+ 1 F
Reset
controller
100 nF
+ 1 F
VREF+
VREF-
ADC
Analog:
RCs,
PLL,..
VSSA
MS19911V2
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These
capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the
PCB to ensure the good functionality of the device.
2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15:
Power supply supervisor.
3. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
4. The 4.7 F ceramic capacitor must be connected to one of the VDD pin.
5. VDDA=VDD and VSSA=VSS.
76/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
5.1.7
Electrical characteristics
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Ratings
VDDVSS
VIN
|VDDx|
|VSSX VSS|
VESD(HBM)
Min
Max
0.3
4.0
VSS0.3
VDD+4
VSS0.3
4.0
50
50
pin(2)
Unit
mV
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.
DocID022063 Rev 4
77/186
Electrical characteristics
STM32F415xx, STM32F417xx
Table 12. Current characteristics
Symbol
Ratings
Max.
IVDD
150
IVSS
(1)
150
25
25
IIO
IINJ(PIN) (2)
IINJ(PIN)
(4)
(3)
Unit
mA
5/+0
(4)
(5)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC
characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Ratings
Storage temperature range
Value
Unit
65 to +150
125
5.3
Operating conditions
5.3.1
Symbol
Parameter
Conditions
Min
Typ
Max
144
168
fHCLK
fPCLK1
42
fPCLK2
84
1.8(2)
3.6
1.8(2)
2.4
2.4
3.6
1.65
3.6
VDD
VDDA(3)(4)
VBAT
78/186
DocID022063 Rev 4
Unit
MHz
STM32F415xx, STM32F417xx
Electrical characteristics
Parameter
Min
Typ
Max
Unit
1.08
1.14
1.20
1.20
1.26
1.32
Regulator OFF:
1.2 V external voltage must be
supplied from external regulator
on VCAP_1/VCAP_2 pins
1.10
1.14
1.20
1.20
1.26
1.30
2 V VDD 3.6 V
0.3
5.5
VDD 2 V
0.3
5.2
0.3
VDDA+
0.3
5.5
Regulator ON:
1.2 V internal voltage on
VCAP_1/VCAP_2 pins
V12
VIN
Conditions
VOS bit in PWR_CR register =
Max frequency 144MHz
0(1)
PD
Power dissipation at TA = 85 C
for suffix 6 or TA = 105 C for
suffix 7(7)
LQFP64
435
LQFP100
465
LQFP144
500
LQFP176
526
UFBGA176
513
WLCSP90
543
40
85
40
105
40
105
40
125
6 suffix version
40
105
7 suffix version
40
125
(8)
(8)
mW
1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole
temperature range, when the system clock frequency is between 30 and 144 MHz.
2. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
3. When the ADC is used, refer to Table 67: ADC characteristics.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. To sustain a voltage higher than VDD+0.3, the internal pull-up and pull-down resistors must be disabled.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Operating
power
supply
range
ADC
operation
VDD =1.8 to
2.1 V(3)
Conversion
time up to
1.2 Msps
VDD = 2.1 to
2.4 V
Conversion
time up to
1.2 Msps
VDD = 2.4 to
2.7 V
VDD = 2.7 to
3.6 V(5)
Conversion
time up to
2.4 Msps
Conversion
time up to
2.4 Msps
Maximum
Flash
memory
access
frequency
with no wait
state
(fFlashmax)
20 MHz
(4)
22 MHz
24 MHz
30 MHz
Maximum Flash
memory access
frequency
with wait
states(1) (2)
I/O operation
Possible
Flash
memory
operations
Clock output
Frequency on
I/O pins
Degraded
speed
performance up to 30 MHz
No I/O
compensation
8-bit erase
and program
operations
only
Degraded
speed
performance up to 30 MHz
No I/O
compensation
16-bit erase
and program
operations
Degraded
speed
performance
up to 48 MHz
I/O
compensation
works
16-bit erase
and program
operations
up to
60 MHz
Full-speed
when VDD =
operation
3.0 to 3.6 V
I/O
up to
compensation
48 MHz
works
when VDD =
2.7 to 3.0 V
32-bit erase
and program
operations
1. It applies only when code executed from Flash memory access, when code executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator allows to achieve
a performance equivalent to 0 wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use
of an external power supply supervisor (refer to Section : Internal reset OFF).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
5.3.2
80/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Figure 23. External capacitor CEXT
C
ESR
R Leak
MS19044V2
Parameter
Conditions
CEXT
2.2 F
ESR
<2
1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
5.3.3
5.3.4
Parameter
Min
Max
20
20
Unit
s/V
tVCAP
Parameter
Conditions
Min
Max
Power-up
20
Power-down
20
20
20
Power-down
Unit
s/V
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
minimum value of V12.
5.3.5
DocID022063 Rev 4
81/186
Electrical characteristics
STM32F415xx, STM32F417xx
VPVD
82/186
Parameter
Conditions
Min
Typ
Max
Unit
PLS[2:0]=000 (rising
edge)
2.09
2.14
2.19
PLS[2:0]=000 (falling
edge)
1.98
2.04
2.08
PLS[2:0]=001 (rising
edge)
2.23
2.30
2.37
PLS[2:0]=001 (falling
edge)
2.13
2.19
2.25
PLS[2:0]=010 (rising
edge)
2.39
2.45
2.51
PLS[2:0]=010 (falling
edge)
2.29
2.35
2.39
2.54
2.60
2.65
2.44
2.51
2.56
2.70
2.76
2.82
PLS[2:0]=100 (falling
edge)
2.59
2.66
2.71
PLS[2:0]=101 (rising
edge)
2.86
2.93
2.99
PLS[2:0]=101 (falling
edge)
2.65
2.84
3.02
2.96
3.03
3.10
PLS[2:0]=110 (falling
edge)
2.85
2.93
2.99
3.07
3.14
3.21
PLS[2:0]=111 (falling
edge)
2.95
3.03
3.09
100
Falling edge
1.60
1.68
1.76
Rising edge
1.64
1.72
1.80
40
PLS[2:0]=011 (falling
Programmable voltage edge)
detector level selection
PLS[2:0]=100 (rising
edge)
VPVDhyst(1)
PVD hysteresis
VPOR/PDR
Power-on/power-down
reset threshold
VPDRhyst(1)
PDR hysteresis
VBOR1
Brownout level 1
threshold
Falling edge
2.13
2.19
2.24
Rising edge
2.23
2.29
2.33
VBOR2
Brownout level 2
threshold
Falling edge
2.44
2.50
2.56
Rising edge
2.53
2.59
2.63
VBOR3
Brownout level 3
threshold
Falling edge
2.75
2.83
2.88
Rising edge
2.85
2.92
2.97
DocID022063 Rev 4
mV
mV
STM32F415xx, STM32F417xx
Electrical characteristics
Table 19. Embedded reset and power control block characteristics (continued)
Symbol
VBORhyst
(1)
Parameter
Conditions
Min
Typ
100
0.5
1.5
3.0
ms
160
200
mA
5.4
BOR hysteresis
InRush current on
voltage regulator
power-on (POR or
wakeup from Standby)
ERUSH(1)
InRush energy on
voltage regulator
power-on (POR or
wakeup from Standby)
IRUSH
Max
Unit
mV
5.3.6
The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states
from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2, except is explicitly mentioned.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 C and VDD = 3.3 V unless otherwise specified.
DocID022063 Rev 4
83/186
Electrical characteristics
STM32F415xx, STM32F417xx
Table 20. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM (1)
Max(2)
Typ
Symbol
Parameter
Conditions
IDD
Supply current in
Run mode
fHCLK
TA =
25 C
TA =
85 C
TA =
105 C
168 MHz
87
102
109
144 MHz
67
80
86
120 MHz
56
69
75
90 MHz
44
56
62
60 MHz
30
42
49
30 MHz
16
28
35
25 MHz
12
24
31
16 MHz(6)
20
28
8 MHz
17
24
4 MHz
15
22
2 MHz
14
21
168 MHz
40
54
61
144 MHz
31
43
50
120 MHz
26
38
45
90 MHz
20
32
39
60 MHz
14
26
33
30 MHz
20
27
25 MHz
18
25
16
24
8 MHz
15
22
4 MHz
14
21
2 MHz
14
21
16 MHz
(6)
Unit
mA
1. Code and data processing running from SRAM1 using boot pins.
2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
6. In this case HCLK = system clock/2.
84/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Table 21. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Max(1)
Typ
Symbol
Parameter
Conditions
fHCLK
External clock(2),
all peripherals
enabled(3)(4)
IDD
Supply current
in Run mode
External clock(2),
all peripherals
disabled(3)(4)
Unit
TA = 25 C TA = 85 C TA = 105 C
168 MHz
93
109
117
144 MHz
76
89
96
120 MHz
67
79
86
90 MHz
53
65
73
60 MHz
37
49
56
30 MHz
20
32
39
25 MHz
16
27
35
16 MHz
11
23
30
8 MHz
18
25
4 MHz
16
23
2 MHz
15
22
168 MHz
46
61
69
144 MHz
40
52
60
120 MHz
37
48
56
90 MHz
30
42
50
60 MHz
22
33
41
30 MHz
12
24
31
25 MHz
10
21
29
16 MHz
19
26
8 MHz
16
23
4 MHz
15
22
2 MHz
14
21
mA
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption
should be considered.
4.
When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
DocID022063 Rev 4
85/186
Electrical characteristics
STM32F415xx, STM32F417xx
Figure 24. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF
50
45
40
IDD RUN(mA)
35
-45 C
30
0 C
25
25 C
20
55 C
85 C
15
105 C
10
5
0
0
20
40
60
80
100
120
140
160
180
Figure 25. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator ON) or RAM, and peripherals ON
100
90
80
IDD RUN(mA)
70
-45C
60
0C
50
25C
40
55C
85C
30
105C
20
10
0
0
20
40
60
80
100
120
140
160
180
86/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Figure 26. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF
60
50
IDD RUN(mA)
40
-45C
0C
30
25C
55C
20
85C
105C
10
0
0
20
40
60
80
100
120
140
160
180
Figure 27. Typical current consumption versus temperature, Run mode, code with data
processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON
120
100
IDD RUN(mA)
80
-45C
0C
60
25C
55C
40
85C
105C
20
0
0
20
40
60
80
100
120
140
160
180
DocID022063 Rev 4
87/186
Electrical characteristics
STM32F415xx, STM32F417xx
Typ
Symbol
Parameter
Conditions
External clock(2),
all peripherals enabled(3)
IDD
Supply current in
Sleep mode
fHCLK
TA =
25 C
TA =
85 C
TA =
105 C
168 MHz
59
77
84
144 MHz
46
61
67
120 MHz
38
53
60
90 MHz
30
44
51
60 MHz
20
34
41
30 MHz
11
24
31
25 MHz
21
28
16 MHz
18
25
8 MHz
16
23
4 MHz
15
22
2 MHz
14
21
168 MHz
12
27
35
144 MHz
22
29
120 MHz
20
28
90 MHz
19
26
60 MHz
17
24
30 MHz
16
23
25 MHz
15
22
16 MHz
14
21
8 MHz
14
21
4 MHz
13
21
2 MHz
13
21
Unit
mA
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
88/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Parameter
Supply
current in
Stop mode
with main
regulator in
Run mode
IDD_STOP
Supply
current in
Stop mode
with main
regulator in
Low Power
mode
Conditions
Max
TA =
25 C
TA =
25 C
Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed
oscillator OFF (no independent watchdog)
0.45
1.5
11.00
20.00
0.40
1.5
11.00
20.00
Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed
oscillator OFF (no independent watchdog)
0.31
1.1
8.00
15.00
0.28
1.1
8.00
15.00
TA =
TA =
85 C 105 C
Unit
mA
Typ
Symbol
Parameter
TA =
85 C
TA = 25 C
Conditions
TA =
105 C
VDD =
1.8 V
VDD=
2.4 V
VDD =
3.3 V
3.0
3.4
4.0
20
36
2.4
2.7
3.3
16
32
2.4
2.6
3.0
12.5
24.8
1.7
1.9
2.2
9.8
19.2
Unit
VDD = 3.6 V
DocID022063 Rev 4
89/186
Electrical characteristics
STM32F415xx, STM32F417xx
Typ
Symbol
Parameter
Backup
IDD_VBA domain
supply
T
current
TA =
85 C
TA = 25 C
Conditions
TA =
105 C
VBAT
=
1.8 V
VBAT=
2.4 V
VBAT
=
3.3 V
VBAT = 3.6 V
1.29
1.42
1.68
11
0.62
0.73
0.96
0.79
0.81
0.86
10
0.10
0.10
0.10
Unit
Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF)
3.5
IVBAT in (A)
2.5
1.65V
1.8V
2V
2.4V
1.5
2.7V
3V
3.3V
1
3.6V
0.5
0
0
10
20
30
40
50
60
70
80
90
100
Temperature in (C)
MS19990V1
90/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON)
IVBAT in (A)
4
1.65V
1.8V
2V
2.4V
2.7V
3V
2
3.3V
3.6V
0
0
10
20
30
40
50
60
70
80
90
100
Temperature in (C)
MS19991V1
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 27: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the MCU
DocID022063 Rev 4
91/186
Electrical characteristics
STM32F415xx, STM32F417xx
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DD f SW C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
92/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Parameter
Conditions(1)
I/O toggling
frequency (fSW)
Typ
2 MHz
0.02
8 MHz
0.14
25 MHz
0.51
50 MHz
0.86
60 MHz
1.30
2 MHz
0.10
8 MHz
0.38
25 MHz
1.18
50 MHz
2.47
60 MHz
2.86
2 MHz
0.17
8 MHz
0.66
25 MHz
1.70
50 MHz
2.65
60 MHz
3.48
2 MHz
0.23
8 MHz
0.95
25 MHz
3.20
50 MHz
4.69
60 MHz
8.06
2 MHz
0.30
8 MHz
1.22
25 MHz
3.90
50 MHz
8.82
60 MHz
-(3)
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
IDDIO
I/O switching
current
VDD = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
VDD = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
Unit
mA
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP package pin (pad removal).
3. At 60 MHz, C maximum load is specified 30 pF.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
The code is running from Flash memory and the Flash memory access time is equal to
5 wait states at 168 MHz.
The code is running from Flash memory and the Flash memory access time is equal to
4 wait states at 144 MHz, and the power scale mode is set to 2.
When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2.
The typical values are obtained for VDD = 3.3 V and TA= 25 C, unless otherwise
specified.
Table 27. Peripheral current consumption
Peripheral(1)
AHB1
AHB2
94/186
168 MHz
144 MHz
GPIO A
0.49
0.36
GPIO B
0.45
0.33
GPIO C
0.45
0.34
GPIO D
0.45
0.34
GPIO E
0.47
0.35
GPIO F
0.45
0.33
GPIO G
0.44
0.33
GPIO H
0.45
0.34
GPIO I
0.44
0.33
OTG_HS + ULPI
4.57
3.55
CRC
0.07
0.06
BKPSRAM
0.11
0.08
DMA1
6.15
4.75
DMA2
6.24
4.8
ETH_MAC +
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
3.28
2.54
OTG_FS
4.59
3.69
DCMI
1.04
0.80
DocID022063 Rev 4
Unit
mA
mA
STM32F415xx, STM32F417xx
Electrical characteristics
AHB2
AHB3
APB1
168 MHz
144 MHz
RNG
0.29
0.23
HASH
1.71
1.31
CRYPTO
0.41
0.31
FSMC
2.18
1.67
TIM2
0.80
0.61
TIM3
0.58
0.44
TIM4
0.62
0.48
TIM5
0.79
0.61
TIM6
0.15
0.11
TIM7
0.16
0.12
TIM12
0.33
0.26
TIM13
0.27
0.21
TIM14
0.27
0.21
PWR
0.04
0.03
USART2
0.17
0.13
USART3
0.17
0.13
UART4
0.17
0.13
UART5
0.17
0.13
I2C1
0.17
0.13
I2C2
0.18
0.13
I2C3
0.18
0.13
SPI2/I2S2(2)
0.17/0.16
0.13/0.12
(2)
0.16/0.14
0.12/0.12
CAN1
0.27
0.21
CAN2
0.26
0.20
SPI3/I2S3
DAC
0.14
0.10
(3)
0.91
0.89
2(4)
0.91
0.89
1.69
1.68
WWDG
0.04
0.04
DAC channel 1
DAC channel
DocID022063 Rev 4
Unit
mA
mA
95/186
Electrical characteristics
STM32F415xx, STM32F417xx
Table 27. Peripheral current consumption (continued)
Peripheral(1)
APB2
168 MHz
144 MHz
SDIO
0.64
0.54
TIM1
1.47
1.14
TIM8
1.58
1.22
TIM9
0.68
0.54
TIM10
0.45
0.36
TIM11
0.47
0.38
(5)
2.20
2.10
ADC2(5)
2.04
1.93
(5)
2.10
2.00
SPI1
0.14
0.12
USART1
0.34
0.27
USART6
0.34
0.28
ADC1
ADC3
Unit
mA
5.3.7
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 14.
Table 28. Low-power mode wakeup timings
Symbol
tWUSLEEP(2)
tWUSTOP(2)
tWUSTDBY(2)(3)
Min(1)
Typ(1)
Max(1)
Unit
13
17
40
110
260
375
480
Parameter
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STM32F415xx, STM32F417xx
5.3.8
Electrical characteristics
Parameter
Conditions
Min
Typ
Max
Unit
50
MHz
fHSE_ext
VHSEH
0.7VDD
VDD
VHSEL
VSS
0.3VDD
tw(HSE)
tw(HSE)
tr(HSE)
tf(HSE)
10
pF
45
55
ns
Cin(HSE)
IL
Parameter
Conditions
Min
Typ
Max
Unit
32.768
1000
kHz
0.7VDD
VDD
fLSE_ext
VLSEH
VLSEL
VSS
0.3VDD
tw(LSE)
tf(LSE)
450
tr(LSE)
tf(LSE)
50
pF
30
70
Cin(LSE)
DuCy(LSE)
IL
ns
Duty cycle
OSC32_IN Input leakage current
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Electrical characteristics
STM32F415xx, STM32F417xx
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE) t
tW(HSE)
THSE
External
clock source
fHSE_ext
OSC_IN
IL
STM32F
ai17528
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE) t
TLSE
External
clock source
fLSE_ext
STM32F
ai17529
98/186
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STM32F415xx, STM32F417xx
Electrical characteristics
IDD
gm
tSU(HSE(3)
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator frequency
26
MHz
Feedback resistor
200
VDD=3.3 V,
ESR= 30 ,
CL=5 pF@25 MHz
449
VDD=3.3 V,
ESR= 30 ,
CL=10 pF@25 MHz
532
Startup
mA/V
VDD is stabilized
ms
Oscillator transconductance
Startup time
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on electing the crystal, refer to the application note AN2867 Oscillator
design guide for ST microcontrollers available from the ST website www.st.com.
Figure 32. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
8 MH z
resonator
CL2
fHSE
OSC_IN
REXT(1)
RF
OSC_OU T
Bias
controlled
gain
STM32F
ai17530
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
18.4
IDD
gm
Oscillator Transconductance
2.8
A/V
VDD is stabilized
Note:
For information on electing the crystal, refer to the application note AN2867 Oscillator
design guide for ST microcontrollers available from the ST website www.st.com.
Figure 33. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 kH z
resonator
RF
Bias
controlled
gain
OSC32_OU T
CL2
STM32F
ai17531
5.3.9
Parameter
Conditions
Min
Typ
Max
Unit
16
MHz
TA = 40 to
105 C(2)
4.5
TA = 10 to 85 C(2)
TA = 25 C
HSI oscillator
startup time
2.2
HSI oscillator
power consumption
60
80
Frequency
User-trimmed with the RCC_CR
register
ACCHSI
tsu(HSI)(3)
IDD(HSI)
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STM32F415xx, STM32F417xx
Electrical characteristics
Parameter
fLSI(2)
tsu(LSI)
Frequency
Min
Typ
Max
Unit
17
32
47
kHz
(3)
15
40
(3)
0.4
0.6
IDD(LSI)
50
max
40
avg
min
30
20
10
0
-10
-20
-30
-40
-45
-35
-25
-15
-5
15
25
35
45
Temperat ure (C)
55
65
75
85
95
105
MS19013V1
5.3.10
PLL characteristics
The parameters given in Table 35 and Table 36 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 14.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 35. Main PLL characteristics
Symbol
Parameter
Min
Typ
Max
Unit
0.95(2)
2.10
MHz
24
168
MHz
48
75
MHz
192
432
MHz
75
200
100
300
RMS
25
peak
to
peak
150
RMS
15
peak
to
peak
200
32
40
330
IDD(PLL)(4)
0.15
0.45
0.40
0.75
mA
IDDA(PLL)(4)
0.30
0.55
0.40
0.85
mA
fPLL_IN
fPLL_OUT
fPLL48_OUT
fVCO_OUT
tLOCK
Conditions
Cycle-to-cycle jitter
System clock
120 MHz
Period Jitter
Jitter(3)
ps
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Parameter
fPLLI2S_IN
PLLI2S input
fPLLI2S_OUT
fVCO_OUT
tLOCK
102/186
Conditions
Min
Typ
Max
Unit
0.95(2)
2.10
MHz
216
MHz
192
432
MHz
75
200
100
300
clock(1)
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Parameter
Conditions
Min
Typ
Max
RMS
90
peak
to
peak
280
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
90
ps
400
ps
IDD(PLLI2S)(4)
0.15
0.45
0.40
0.75
mA
IDDA(PLLI2S)(4)
0.40
0.85
mA
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
0.30
0.55
Unit
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Based on characterization, not tested in production.
5.3.11
Parameter
Min
Typ
Max(1)
Unit
fMod
Modulation frequency
10
KHz
md
0.25
2151
MODEPER * INCSTEP
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ( 4 fMod ) ]
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Electrical characteristics
STM32F415xx, STM32F417xx
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round [ ( ( 2
15
15
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
md quantized % = ( MODEPER INCSTEP 100 5 ) ( ( 2
15
1 ) PLLN )
As a result:
md quantized % = ( 250 126 100 5 ) ( ( 2
15
1 ) 240 ) = 2.002%(peak)
Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 35. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT)
md
F0
md
tmode
2 x tmode
Time
ai17291
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STM32F415xx, STM32F417xx
Electrical characteristics
F0
2 x md
tmode
Time
2 x tmode
ai17292
5.3.12
Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 105 C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 38. Flash memory characteristics
Symbol
IDD
Parameter
Supply current
Conditions
Min
Typ
Max
12
Unit
mA
Parameter
Word programming time
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism
(PSIZE) = x 8/16/32
16
100(2)
Program/erase parallelism
(PSIZE) = x 8
400
800
Program/erase parallelism
(PSIZE) = x 16
300
600
Program/erase parallelism
(PSIZE) = x 32
250
500
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ms
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 39. Flash memory programming (continued)
Symbol
tME
Vprog
Conditions
Min(1)
Typ
Program/erase parallelism
(PSIZE) = x 8
1200
2400
Program/erase parallelism
(PSIZE) = x 16
700
1400
Program/erase parallelism
(PSIZE) = x 32
550
1100
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
1.3
2.6
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8
16
32
Program/erase parallelism
(PSIZE) = x 16
11
22
Program/erase parallelism
(PSIZE) = x 32
16
2.7
3.6
2.1
3.6
1.8
3.6
Parameter
Programming voltage
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Max(1) Unit
ms
STM32F415xx, STM32F417xx
Electrical characteristics
Table 40. Flash memory programming with VPP
Symbol
Parameter
Conditions
tprog
tERASE16KB
tERASE64KB
Min(1)
Typ
Max(1)
Unit
16
100(2)
230
490
875
6.9
2.7
3.6
TA = 0 to +40 C
VDD = 3.3 V
VPP = 8.5 V
ms
Vprog
Programming voltage
VPP
IPP
10
mA
hour
tVPP(3)
NEND
tRET
Parameter
Endurance
Data retention
Conditions
Min(1)
10
1 kcycle(2) at TA = 85 C
30
1 kcycle
(2)
10 kcycles
at TA = 105 C
10
(2)
20
at TA = 55 C
Unit
kcycles
Years
5.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
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Electrical characteristics
STM32F415xx, STM32F417xx
Parameter
Conditions
Level/
Class
VFESD
2B
VEFTB
4A
Unexpected reset
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics
Table 43. EMI characteristics
Symbol
Parameter
Max vs.
[fHSE/fCPU]
Monitored
frequency band
Conditions
Unit
25/168 MHz
VDD = 3.3 V, TA = 25 C, LQFP176
package, conforming to SAE J1752/3
EEMBC, code running from Flash with
ART accelerator enabled
SEMI
5.3.14
Peak level
VDD = 3.3 V, TA = 25 C, LQFP176
package, conforming to SAE J1752/3
EEMBC, code running from Flash with
ART accelerator and PLL spread
spectrum enabled
0.1 to 30 MHz
32
30 to 130 MHz
25
29
0.1 to 30 MHz
19
30 to 130 MHz
16
18
3.5
dBV
dBV
Ratings
Conditions
Class
Maximum
value(1)
2000(2)
VESD(HBM)
Electrostatic discharge
voltage (human body
model)
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
Unit
V
II
500
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A current injection is applied to each input, output and configurable I/O pin
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 45. Electrical sensitivities
Symbol
LU
5.3.15
Parameter
Static latch-up class
Conditions
Class
II level A
IINJ(1)
Description
Negative
injection
Positive
injection
+0
+5
Unit
mA
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
5.3.16
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STM32F415xx, STM32F417xx
Electrical characteristics
Table 47. I/O static characteristics
Symbol
VIL
VIH
(1)
Parameter
Conditions
Min
Typ
Max
TTL ports
2.7 V VDD 3.6 V
0.8
2.0
0.3VDD
200
5% VDD(3)
VIN = 5 V
30
40
50
PA10 and
PB12
11
15
All pins
except for
PA10 and
PB12
30
40
50
11
15
VIL
VIH(1)
CMOS ports
1.8 V VDD 3.6 V
(2)
Ilkg
RPU
RPD
Weak pull-down
equivalent resistor
All pins
except for
PA10 and
PB12
mV
VIN = VSS
VIN = VDD
PA10 and
PB12
CIO(6)
0.7VDD
Unit
pF
1. Tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
6. Guaranteed by design, not tested in production.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
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Electrical characteristics
STM32F415xx, STM32F417xx
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 12).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 12).
Parameter
VOL(2)
VOH(3)
VOL (2)
VOH
(3)
VOL(2)(4)
VOH(3)(4)
VOL(2)(4)
VOH(3)(4)
Conditions
Min
Max
CMOS port
IIO = +8 mA
2.7 V < VDD < 3.6 V
0.4
TTL port
IIO =+ 8mA
2.7 V < VDD < 3.6 V
IIO = +20 mA
2.7 V < VDD < 3.6 V
IIO = +6 mA
2 V < VDD < 2.7 V
Unit
V
VDD0.4
0.4
V
2.4
1.3
V
VDD1.3
0.4
V
VDD0.4
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed
should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current
source (e.g. to drive an LED).
2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 37 and
Table 49, respectively.
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STM32F415xx, STM32F417xx
Electrical characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.
Table 49. I/O AC characteristics(1)(2)(3)
OSPEEDRy
[1:0] bit
value(1)
Symbol
Parameter
Conditions
tr(IO)out
Min
Typ
Max
TBD
TBD
TBD
TBD
25
12.5(5)
50(5)
TBD
Unit
MHz
ns
tf(IO)out
TBD
TBD
tr(IO)out
TBD
TBD
50(5)
25
100(5)
TBD
CL = 50 pF,
2.4 < VDD < 2.7 V
TBD
TBD
CL = 50 pF,
2.4 < VDD < 2.7 V
TBD
TBD
10
tf(IO)out
tr(IO)out
DocID022063 Rev 4
MHz
ns
MHz
ns
113/186
Electrical characteristics
STM32F415xx, STM32F417xx
Symbol
Fmax(IO)ou
t
11
tf(IO)out
tr(IO)out
tEXTIpw
Parameter
Conditions
Maximum frequency(4)
Min
Typ
Max
100(5)
50(5)
200(5)
TBD
CL = 20 pF,
2.4 < VDD < 2.7 V
TBD
TBD
CL = 20 pF,
2.4 < VDD < 2.7 V
TBD
TBD
10
Unit
MHz
ns
ns
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON 50pF
tr(IO)out
tr(IO)out
T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.17
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Electrical characteristics
Table 50. NRST pin characteristics
Symbol
VIL(NRST)(1)
Parameter
NRST Input low level voltage
Min
Typ
Max
TTL ports
2.7 V VDD
3.6 V
0.8
CMOS ports
1.8 V VDD
3.6 V
VF(NRST)(1)
(1)
TNRST_OUT
0.3VDD
0.7VDD
200
mV
30
40
50
100
ns
300
ns
Internal
Reset source
20
VIN = VSS
Unit
RPU
VNF(NRST)
Conditions
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal Reset
Filter
0.1 F
STM32Fxxx
ai14132c
5.3.18
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
tres(TIM)
Parameter
Conditions
AHB/APB1
prescaler distinct
from 1, fTIMxCLK =
84 MHz
AHB/APB1
prescaler = 1,
fTIMxCLK = 42 MHz
fEXT
ResTIM
tCOUNTER
Min
Max
Unit
tTIMxCLK
11.9
ns
tTIMxCLK
23.8
ns
fTIMxCLK/2
MHz
42
MHz
Timer resolution
16/32
bit
65536
tTIMxCLK
780
tTIMxCLK
0.0119
51130563
65536 65536
tTIMxCLK
51.1
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.
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Electrical characteristics
tres(TIM)
Parameter
Conditions
AHB/APB2
prescaler distinct
from 1, fTIMxCLK =
168 MHz
AHB/APB2
prescaler = 1,
fTIMxCLK = 84 MHz
fEXT
ResTIM
tCOUNTER
Min
Max
Unit
tTIMxCLK
5.95
ns
tTIMxCLK
11.9
ns
fTIMxCLK/2
MHz
84
MHz
16
bit
65536
tTIMxCLK
32768
tTIMxCLK
fTIMxCLK =
168 MHz
APB2 = 84 MHz
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
5.3.19
Communications interfaces
I2C interface characteristics
The STM32F415xx and STM32F417xx I2C interface meets the requirements of the
standard I2C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not true open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 53. I2C characteristics
Standard mode I2C(1)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
4.7
1.3
tw(SCLH)
4.0
0.6
tsu(SDA)
250
100
th(SDA)
0(3)
900(4)
tr(SDA)
tr(SCL)
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
300
300
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 53. I2C characteristics (continued)
Standard mode I2C(1)
Symbol
Parameter
Unit
Min
Max
Min
Max
th(STA)
4.0
0.6
tsu(STA)
4.7
0.6
tsu(STO)
4.0
0.6
tw(STO:STA)
4.7
1.3
Cb
400
400
pF
V DD_I2C
RP
RP
STM32Fxx
RS
SDA
IC bus
RS
SCL
S T AR T REPEATED
S T AR T
S T AR T
tsu(STA)
SD A
tf(SDA)
tr(SDA)
th(STA)
tsu(SDA)
tw(SCLL)
th(SDA)
tw(STO:STA)
S TOP
SCL
tw(SCLH)
tr(SCL)
tf(SCL)
tsu(STO)
ai14979c
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STM32F415xx, STM32F417xx
Electrical characteristics
RP = 4.7 k
400
0x8019
300
0x8021
200
0x8032
100
0x0096
50
0x012C
20
0x02EE
Capacitive load C = 30 pF
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 55. SPI dynamic characteristics(1)
Symbol
Parameter
fSCK
SPI clock frequency
1/tc(SCK)
Duty(SCK)
Conditions
Slave mode
DocID022063 Rev 4
Min
Typ
Max
Unit
42
-
42
MHz
21
21
30
50
70
119/186
Electrical characteristics
STM32F415xx, STM32F417xx
Parameter
tw(SCKH)
SCK high and low time
tw(SCKL)
Conditions
Master mode, SPI presc = 2,
2.7V < VDD < 3.6V
Master mode, SPI presc = 2,
1.7V < VDD < 3.6V
Min
TPCLK-2
4 x TPCLK
th(NSS)
2 x TPCLK
tsu(SI)
th(MI)
th(SI)
ta(SO)
(2)
tdis(SO)
(3)
tv(SO)
Data output valid/hold time
th(SO)
tv(MO)
th(MO)
Max
Unit
tsu(NSS)
tsu(MI)
Typ
TPCLK
TPCLK+2
Master mode
6.5
Slave mode
2.5
Master mode
2.5
Slave mode
4 x TPCLK
7.5
16.5
11
13
12
16.5
15.5
19
18
20.5
2.5
4.5
ns
120/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
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Electrical characteristics
STM32F415xx, STM32F417xx
Figure 42. SPI timing diagram - master mode
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
122/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Capacitive load C = 30 pF
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 56. I2S dynamic characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
256 x
8K
256 x FS(2)
MHz
64 x FS
64 x FS
fMCK
fCK
DCK
30
70
tv(WS)
WS valid time
Master mode
th(WS)
WS hold time
Master mode
tsu(WS)
WS setup time
Slave mode
th(WS)
WS hold time
Slave mode
Master receiver
7.5
Slave receiver
Master receiver
Slave receiver
27
20
2.5
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
MHz
%
ns
Note:
Refer to the I2S section of RM0090 reference manual for more details on the sampling
frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The
value of these parameters might be slightly impacted by the source clock accuracy. DCK
depends mainly on the value of ODD bit. The digital contribution leads to a minimum value
of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV +
ODD). FS maximum value is supported for each mode/condition.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Figure 43. I2S slave timing diagram (Philips protocol)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
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DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Table 57. USB OTG FS startup time
Symbol
tSTARTUP(1)
Parameter
USB OTG FS transceiver startup time
Max
Unit
Input
levels
Parameter
Conditions
3.6
I(USB_FS_DP/DM,
USB_HS_DP/DM)
0.2
VCM(3)
0.8
2.5
VSE(3)
1.3
2.0
VOL
0.3
2.8
3.6
17
21
24
0.65
1.1
2.0
Output
levels
RPD
RPU
VOH
VSS(4)
VIN = VDD
k
VIN = VSS
1.5
1.8
2.1
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS
0.25
0.37
0.55
1. All the voltages are measured from the local ground potential.
2. The STM32F415xx and STM32F417xx USB OTG FS functionality is ensured down to 2.7 V but not the full
USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design, not tested in production.
4. RL is the load connected on the USB OTG FS drivers
Figure 45. USB OTG FS timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tf
tr
ai14137
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 59. USB OTG FS electrical characteristics(1)
Driver characteristics
Symbol
Parameter
Rise time(2)
tr
Fall time
tf
(2)
Conditions
Min
Max
Unit
CL = 50 pF
20
ns
CL = 50 pF
20
ns
tr/tf
90
110
1.3
2.0
trfm
VCRS
USB HS characteristics
Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 61
and VDD supply voltage conditions summarized in Table 60, with the following configuration:
Capacitive load C = 30 pF
Refer to Section Section 5.3.16: I/O port characteristics for more details on the
input/outputcharacteristics.
Table 60. USB HS DC electrical characteristics
Symbol
Input level
Parameter
VDD
Min.(1)
Max.(1)
Unit
2.7
3.6
1. All the voltages are measured from the local ground potential.
Symbol
8-bit 10%
FSTART_8BIT
FSTEADY
DSTART_8BIT
DSTEADY
Max
54
60
66
MHz
59.97
60
60.03
MHz
40
50
60
49.975
50
50.025
1.4
ms
TSTART_DEV
5.6
Host
TSTART_HOST
DocID022063 Rev 4
Unit
MHz
Peripheral
126/186
Nominal
30
Min
ms
s
STM32F415xx, STM32F417xx
Electrical characteristics
Symbol
tSC
Unit
Min.
Max.
2.0
1.5
tHC
tSD
2.0
tHD
tDC
9.2
tDD
10.7
ns
tSC
tHC
tSD
tHD
data In
(8-bit)
tDC
Control out
(ULPI_STP)
tDC
tDD
data out
(8-bit)
ai17361c
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 14 and VDD supply voltage conditions summarized in
Table 63, with the following configuration:
Capacitive load C = 30 pF
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output
characteristics.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 63. Ethernet DC electrical characteristics
Symbol
Input level
Parameter
VDD
Min.(1)
Max.(1)
Unit
2.7
3.6
1. All the voltages are measured from the local ground potential.
Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 47 shows the corresponding timing diagram.
Figure 47. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
Parameter
Min
Typ
Max
411
420
425
tMDC
Td(MDIO)
10
13
tsu(MDIO)
12
th(MDIO)
Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the
corresponding timing diagram.
Figure 48. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667
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DocID022063 Rev 4
Unit
ns
STM32F415xx, STM32F417xx
Electrical characteristics
Rating
Min
Typ
Max
Unit
tsu(RXD)
ns
tih(RXD)
ns
tsu(CRS)
0.5
ns
tih(CRS)
ns
td(TXEN)
9.5
11
ns
td(TXD)
8.5
10
11.5
ns
Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the
corresponding timing diagram.
Figure 49. Ethernet MII timing diagram
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668
Parameter
Min
Typ
Max
tsu(RXD)
tih(RXD)
10
tsu(DV)
tih(DV)
tsu(ER)
tih(ER)
td(TXEN)
10
14
td(TXD)
10
15
Unit
ns
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Electrical characteristics
STM32F415xx, STM32F417xx
5.3.20
Symbol
VDDA
VREF+
fADC
fTRIG(4)
VAIN
RAIN(4)
Parameter
Conditions
Min
Typ
Max
Unit
1.8(1)
3.6
1.8(1)(2)(3)
VDDA
VDDA = 1.8(1)(3) to
2.4 V
0.6
15
18
MHz
0.6
30
36
MHz
fADC = 30 MHz,
12-bit resolution
1764
kHz
17
1/fADC
VREF+
50
pF
0.100
3(7)
1/fADC
0.067
Power supply
Positive reference voltage
ADC clock frequency
tlat(4)
fADC = 30 MHz
tlatr(4)
fADC = 30 MHz
tS(4)
Sampling time
tSTAB(4)
Power-up time
130/186
fADC = 30 MHz
DocID022063 Rev 4
(7)
1/fADC
0.100
16
480
1/fADC
STM32F415xx, STM32F417xx
Electrical characteristics
tCONV(4)
Parameter
Conditions
Min
Typ
Max
Unit
fADC = 30 MHz
12-bit resolution
0.50
16.40
fADC = 30 MHz
10-bit resolution
0.43
16.34
fADC = 30 MHz
8-bit resolution
0.37
16.27
fADC = 30 MHz
6-bit resolution
0.30
16.20
fS(4)
Sampling rate
(fADC = 30 MHz, and
tS = 3 ADC cycles)
1/fADC
12-bit resolution
Single ADC
Msps
12-bit resolution
Interleave Dual ADC
mode
3.75
Msps
12-bit resolution
Interleave Triple ADC
mode
Msps
IVREF+(4)
300
500
IVDDA(4)
1.6
1.8
mA
1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
3. VDDA -VREF+ < 1.2 V.
4. Based on characterization, not tested in production.
5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
( k 0.5 )
- R ADC
= ------------------------------------------------------------f ADC C ADC ln ( 2
N+2
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 68. ADC accuracy at fADC = 30 MHz(1)
Symbol
Parameter
Test conditions
ET
EO
Offset error
EG
Gain error
ED
EL
fPCLK2 = 60 MHz,
fADC = 30 MHz, RAIN < 10 k,
VDDA = 1.8(3) to 3.6 V
Typ
Max(2)
1.5
2.5
1.5
1.5
Unit
LSB
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on characterization, not tested in production.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range,
and with the use of an external power supply supervisor (refer to Section : Internal reset OFF).
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in
Section 5.3.16 does not affect the ADC accuracy.
Figure 50. ADC accuracy characteristics
[1LSB IDEAL =
V REF+
4096
(or
V DDA
4096
depending on package)]
EG
4095
4094
4093
(2)
ET
(3)
(1)
6
5
EO
EL
ED
2
1L SBIDEAL
1
0
456
V SSA
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STM32F415xx, STM32F417xx
Electrical characteristics
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
VDD
RAIN(1)
VT
0.6 V
RADC(1)
AINx
VAIN
Cparasitic
VT
0.6 V
IL1 A
12-bit
converter
CADC(1)
ai17534
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Electrical characteristics
STM32F415xx, STM32F417xx
V REF+
(See note 1)
1 F // 10 nF
V DDA
1 F // 10 nF
V SSA/V REF(See note 1)
ai17535
1. VREF+ and VREF inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF are not available, they are internally connected to VDDA and VSSA.
Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA
(See note 1)
1 F // 10 nF
VREF/VSSA
(See note 1)
ai17536
1. VREF+ and VREF inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF are not available, they are internally connected to VDDA and VSSA.
134/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
5.3.21
Electrical characteristics
Symbol
Parameter
TL(1)
Avg_Slope
(1)
V25(1)
tSTART(2)
TS_temp
(3)(2)
Min
Typ
Max
Unit
Average slope
2.5
mV/C
Voltage at 25 C
0.76
Startup time
10
10
Parameter
Memory address
5.3.22
Symbol
Parameter
Min
Typ
Max
Unit
K
50
Error on Q
+1
Er
(1)
TS_vbat(2)(2)
DocID022063 Rev 4
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Electrical characteristics
5.3.23
STM32F415xx, STM32F417xx
Symbol
VREFINT
TS_vrefint(1)
VRERINT_s(2)
Parameter
Internal reference voltage
Conditions
Min
Typ
1.18
1.21
1.24
10
mV
VDD = 3 V
Max
Unit
TCoeff(2)
Temperature coefficient
30
50
ppm/C
tSTART(2)
Startup time
10
5.3.24
Parameter
Memory address
Symbol
Parameter
Min
Typ
Max
Unit
VDDA
1.8(1)
3.6
VREF+
1.8(1)
3.6
VSSA
Ground
RLOAD(2)
Comments
VREF+ VDDA
15
Capacitive load
50
pF
0.2
VDDA 0.2
RO(2)
CLOAD(2)
136/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Min
Typ
Max
Unit
0.5
mV
VREF+ 1LSB
170
240
IVREF+(4)
IDDA(4)
DNL(4)
INL(4)
Offset(4)
Gain
error(4)
Parameter
50
75
280
380
475
625
0.5
LSB
LSB
LSB
LSB
10
mV
Offset error
(difference between
measured value at Code
(0x800) and the ideal value
= VREF+/2)
LSB
12
LSB
Gain error
0.5
CLOAD 50 pF,
RLOAD 5 k
dB
CLOAD 50 pF,
RLOAD 5 k
Comments
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Table 74. DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Comments
Update
rate(2)
MS/s
6.5
10
67
40
dB
No RLOAD, CLOAD = 50 pF
CLOAD 50 pF,
RLOAD 5 k
1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of
an external power supply supervisor (refer to Section : Internal reset OFF).
2. Guaranteed by design, not tested in production.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization, not tested in production.
12-bit
digital to
analog
converter
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
5.3.25
FSMC characteristics
Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 14, with the following configuration:
Capacitive load C = 30 pF
Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output
characteristics.
138/186
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STM32F415xx, STM32F417xx
Electrical characteristics
AddressSetupTime = 1
AddressHoldTime = 0x1
DataSetupTime = 0x1
BusTurnAroundDuration = 0x0
FSMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FSMC_NOE
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
t h(A_NOE)
Address
tv(BL_NE)
t h(BL_NOE)
FSMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE)
th(Data_NOE)
t su(Data_NE)
Data
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14991c
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
Min
Max
2THCLK0.5 2 THCLK+1
Unit
ns
0.5
ns
2THCLK2
2THCLK+ 2
ns
ns
4.5
ns
ns
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
1.5
ns
th(BL_NOE)
ns
tsu(Data_NE)
THCLK+4
ns
tsu(Data_NOE)
THCLK+4
ns
th(Data_NOE)
ns
th(Data_NE)
ns
tv(NADV_NE)
ns
THCLK
ns
tw(NADV)
1. CL = 30 pF.
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FSMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FSMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14990
140/186
Parameter
Min
Max
Unit
3THCLK
3THCLK+ 4
ns
THCLK0.5
THCLK+0.5
ns
THCLK1
THCLK+2
ns
THCLK1
ns
ns
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
tv(BL_NE)
THCLK 2
ns
1.5
ns
THCLK 1
ns
th(BL_NWE)
tv(Data_NE)
THCLK+3
ns
th(Data_NWE)
THCLK1
ns
tv(NADV_NE)
ns
THCLK+0.5
ns
tw(NADV)
1. CL = 30 pF.
FSMC_NE
tv(NOE_NE)
t h(NE_NOE)
FSMC_NOE
t w(NOE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
t h(A_NOE)
Address
tv(BL_NE)
th(BL_NOE)
FSMC_NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
tsu(Data_NOE)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NOE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14892b
Parameter
Min
Max
Unit
3THCLK1
3THCLK+1
ns
2THCLK0.5
2THCLK+0.5
ns
THCLK1
THCLK+1
ns
ns
ns
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
tw(NADV)
th(AD_NADV)
ns
THCLK 2
THCLK+1
ns
THCLK
ns
THCLK1
ns
th(A_NOE)
th(BL_NOE)
ns
tv(BL_NE)
ns
tsu(Data_NE)
THCLK+4
ns
THCLK+4
ns
ns
ns
th(Data_NE)
1. CL = 30 pF.
2. Based on characterization, not tested in production.
FSMC_NEx
FSMC_NOE
tv(NWE_NE)
tw(NWE)
t h(NE_NWE)
FSMC_NWE
tv(A_NE)
FSMC_A[25:16]
th(A_NWE)
Address
tv(BL_NE)
th(BL_NWE)
FSMC_NBL[1:0]
NBL
t v(A_NE)
t v(Data_NADV)
Address
FSMC_AD[15:0]
t v(NADV_NE)
th(Data_NWE)
Data
th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14891B
142/186
Parameter
Min
Max
Unit
4THCLK0.5
4THCLK+3
ns
THCLK0.5
THCLK -0.5
ns
2THCLK0.5
2THCLK+3
ns
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
THCLK
ns
ns
ns
THCLK 2
THCLK+ 1
ns
th(AD_NADV)
THCLK2
ns
th(A_NWE)
THCLK
ns
th(BL_NWE)
THCLK2
ns
1.5
ns
tv(Data_NADV)
THCLK0.5
ns
th(Data_NWE)
THCLK
ns
tv(A_NE)
tv(NADV_NE)
tw(NADV)
tv(BL_NE)
1. CL = 30 pF.
2. Based on characterization, not tested in production.
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
In all timing tables, the THCLK is the HCLK clock period (with maximum
FSMC_CLK = 60 MHz).
DocID022063 Rev 4
143/186
Electrical characteristics
STM32F415xx, STM32F417xx
tw(CLK)
tw(CLK)
FSMC_CLK
Data latency = 0
td(CLKL-NExL)
t d(CLKL-NExH)
FSMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FSMC_NADV
td(CLKL-AIV)
td(CLKL-AV)
FSMC_A[25:16]
td(CLKL-NOEH)
td(CLKL-NOEL)
FSMC_NOE
td(CLKL-ADIV)
tsu(ADV-CLKH)
td(CLKL-ADV)
FSMC_AD[15:0]
AD[15:0]
th(CLKH-ADV)
tsu(ADV-CLKH)
D1
tsu(NWAITV-CLKH)
th(CLKH-ADV)
D2
th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14893g
Parameter
FSMC_CLK period
Max
Unit
2THCLK
ns
td(CLKL-NExL)
ns
td(CLKL-NExH)
ns
td(CLKL-NADVL)
ns
ns
144/186
Min
td(CLKL-AV)
ns
td(CLKL-AIV)
ns
td(CLKL-NOEL)
ns
td(CLKL-NOEH)
ns
td(CLKL-ADV)
4.5
ns
td(CLKL-ADIV)
ns
tsu(ADV-CLKH)
ns
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
th(CLKH-NWAIT)
ns
ns
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
tw(CLK)
tw(CLK)
FSMC_CLK
Data latency = 0
td(CLKL-NExL)
td(CLKL-NExH)
FSMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FSMC_NADV
td(CLKL-AV)
td(CLKL-AIV)
FSMC_A[25:16]
td(CLKL-NWEL)
td(CLKL-NWEH)
FSMC_NWE
td(CLKL-ADIV)
td(CLKL-Data)
td(CLKL-Data)
td(CLKL-ADV)
AD[15:0]
FSMC_AD[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
td(CLKL-NBLH)
FSMC_NBL
ai14992g
Parameter
FSMC_CLK period
Min
Max
Unit
2THCLK
ns
td(CLKL-NExL)
ns
td(CLKL-NExH)
ns
td(CLKL-NADVL)
ns
ns
ns
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Electrical characteristics
STM32F415xx, STM32F417xx
ns
td(CLKL-NWEL)
0.5
ns
td(CLKL-NWEH)
ns
td(CLKL-ADIV)
ns
td(CLKL-DATA)
ns
td(CLKL-NBLH)
ns
ns
th(CLKH-NWAIT)
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
tw(CLK)
tw(CLK)
FSMC_CLK
td(CLKL-NExL)
td(CLKL-NExH)
Data latency = 0
FSMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FSMC_NADV
td(CLKL-AIV)
td(CLKL-AV)
FSMC_A[25:0]
td(CLKL-NOEL)
td(CLKL-NOEH)
FSMC_NOE
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
FSMC_D[15:0]
D1
tsu(NWAITV-CLKH)
th(CLKH-DV)
D2
th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
t h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14894f
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Parameter
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
DocID022063 Rev 4
Min
Max
Unit
2THCLK 0.5
ns
0.5
ns
STM32F415xx, STM32F417xx
Electrical characteristics
ns
td(CLKL-NADVL)
ns
td(CLKL-NADVH)
ns
td(CLKL-AV)
ns
td(CLKL-AIV)
ns
td(CLKL-NOEL)
0.5
ns
td(CLKL-NOEH)
1.5
ns
tsu(DV-CLKH)
ns
th(CLKH-DV)
ns
ns
th(CLKH-NWAIT)
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
BUSTURN = 0
tw(CLK)
FSMC_CLK
td(CLKL-NExL)
td(CLKL-NExH)
Data latency = 0
FSMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FSMC_NADV
td(CLKL-AV)
td(CLKL-AIV)
FSMC_A[25:0]
td(CLKL-NWEL)
td(CLKL-NWEH)
FSMC_NWE
td(CLKL-Data)
FSMC_D[15:0]
td(CLKL-Data)
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
td(CLKL-NBLH)
th(CLKH-NWAITV)
FSMC_NBL
ai14993g
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Symbol
tw(CLK)
d(CLKL-NExL)
Parameter
FSMC_CLK period
Min
Max Unit
2THCLK
ns
ns
td(CLKL-NExH)
ns
td(CLKL-NADVL)
ns
td(CLKL-NADVH)
ns
td(CLKL-AV)
ns
td(CLKL-AIV)
ns
td(CLKL-NWEL)
ns
td(CLKL-NWEH)
ns
td(CLKL-Data)
ns
td(CLKL-NBLH)
ns
tsu(NWAIT-CLKH)
ns
th(CLKH-NWAIT)
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
COM.FSMC_SetupTime = 0x04;
COM.FSMC_WaitSetupTime = 0x07;
COM.FSMC_HoldSetupTime = 0x04;
COM.FSMC_HiZSetupTime = 0x00;
ATT.FSMC_SetupTime = 0x04;
ATT.FSMC_WaitSetupTime = 0x07;
ATT.FSMC_HoldSetupTime = 0x04;
ATT.FSMC_HiZSetupTime = 0x00;
IO.FSMC_SetupTime = 0x04;
IO.FSMC_WaitSetupTime = 0x07;
IO.FSMC_HoldSetupTime = 0x04;
IO.FSMC_HiZSetupTime = 0x00;
TCLRSetupTime = 0;
TARSetupTime = 0.
148/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
tv(NCEx-A)
FSMC_A[10:0]
th(NCEx-NREG)
th(NCEx-NIORD)
th(NCEx-NIOWR)
td(NREG-NCEx)
td(NIORD-NCEx)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
td(NCE4_1-NOE)
FSMC_NOE
tw(NOE)
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14895b
FSMC_NCE4_2
High
tv(NCE4_1-A)
th(NCE4_1-AI)
FSMC_A[10:0]
th(NCE4_1-NREG)
th(NCE4_1-NIORD)
th(NCE4_1-NIOWR)
td(NREG-NCE4_1)
td(NIORD-NCE4_1)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NCE4_1-NWE)
tw(NWE)
td(NWE-NCE4_1)
FSMC_NWE
FSMC_NOE
MEMxHIZ =1
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14896b
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Electrical characteristics
STM32F415xx, STM32F417xx
th(NCE4_1-AI)
High
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1)
th(NCE4_1-NREG)
FSMC_NREG
FSMC_NWE
td(NCE4_1-NOE)
tw(NOE)
td(NOE-NCE4_1)
FSMC_NOE
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0](1)
ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
150/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
FSMC_NCE4_2
High
tv(NCE4_1-A)
th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1)
th(NCE4_1-NREG)
FSMC_NREG
td(NCE4_1-NWE)
tw(NWE)
FSMC_NWE
td(NWE-NCE4_1)
FSMC_NOE
tv(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
th(NCE4_1-AI)
tv(NCEx-A)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
tw(NIORD)
td(NIORD-NCE4_1)
FSMC_NIORD
tsu(D-NIORD)
td(NIORD-D)
FSMC_D[15:0]
ai14899B
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Electrical characteristics
STM32F415xx, STM32F417xx
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access
FSMC_NCE4_1
FSMC_NCE4_2
tv(NCEx-A)
th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIORD
td(NCE4_1-NIOWR)
tw(NIOWR)
FSMC_NIOWR
ATTxHIZ =1
th(NIOWR-D)
tv(NIOWR-D)
FSMC_D[15:0]
ai14900c
Table 83. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space(1)(2)
Symbol
Parameter
Min
Max
Unit
tv(NCEx-A)
ns
th(NCEx_AI)
ns
td(NREG-NCEx)
3.5
ns
th(NCEx-NREG)
THCLK+4
ns
td(NCEx-NWE)
5THCLK+0.5
ns
td(NCEx-NOE)
5THCLK +0.5
ns
8THCLK1
8THCLK+1
ns
5THCLK+2.5
ns
4.5
ns
ns
8THCLK0.5
8THCLK+ 3
ns
5THCLK1
ns
tw(NOE)
td(NOE_NCEx)
tsu (D-NOE)
th(N0E-D)
tw(NWE)
td(NWE_NCEx)
td(NCEx-NWE)
5THCLK+ 1
ns
ns
tv(NWE-D)
th (NWE-D)
8THCLK 1
ns
td (D-NWE)
13THCLK 1
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
152/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Table 84. Switching characteristics for PC Card/CF read and write cycles
in I/O space(1)(2)
Symbol
Parameter
tw(NIOWR)
tv(NIOWR-D)
th(NIOWR-D)
Min
Max
Unit
8THCLK 1
ns
5THCLK 1
ns
8THCLK 2
ns
5THCLK+ 2.5
ns
5THCLK1.5
ns
5THCLK+ 2
ns
td(NIORD-NCEx)
th(NCEx-NIORD)
5THCLK 1.5
ns
8THCLK0.5
ns
tw(NIORD)
tsu(D-NIORD)
ns
td(NIORD-D)
ns
1. CL = 30 pF.
2. Based on characterization, not tested in production.
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
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Electrical characteristics
STM32F415xx, STM32F417xx
Figure 69. NAND controller waveforms for read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FSMC_NOE (NRE)
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14901c
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NWE)
th(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14902c
154/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Electrical characteristics
Figure 71. NAND controller waveforms for common memory read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
th(NOE-ALE)
FSMC_NWE
tw(NOE)
FSMC_NOE
tsu(D-NOE)
th(NOE-D)
FSMC_D[15:0]
ai14912c
Figure 72. NAND controller waveforms for common memory write access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FSMC_NWE
FSMC_NOE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FSMC_D[15:0]
ai14913c
Parameter
FSMC_NOE low width
Min
Max
Unit
4THCLK
0.5
4THCLK+ 3
ns
tsu(D-NOE)
10
ns
th(NOE-D)
ns
td(ALE-NOE)
3THCLK
ns
th(NOE-ALE)
3THCLK 2
ns
1. CL = 30 pF.
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Electrical characteristics
STM32F415xx, STM32F417xx
Parameter
FSMC_NWE low width
Min
Max
Unit
4THCLK1
4THCLK+ 3
ns
ns
tv(NWE-D)
th(NWE-D)
3THCLK 2
ns
td(D-NWE)
5THCLK3
ns
3THCLK
ns
3THCLK2
ns
td(ALE-NWE)
th(NWE-ALE)
1. CL = 30 pF.
5.3.26
th(HSYNC)
tsu(VSYNC)
th(HSYNC)
HSYNC
VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V1
156/186
Parameter
Min
Max
0.4
DCMI_PIXCLK
54
MHz
Dpixel
30
70
DocID022063 Rev 4
Unit
STM32F415xx, STM32F417xx
Electrical characteristics
Table 87. DCMI characteristics(1) (continued)
Symbol
Parameter
Min
Max
2.5
tsu(DATA)
th(DATA)
tsu(HSYNC),
tsu(VSYNC)
th(HSYNC),
th(VSYNC)
0.5
Unit
ns
5.3.27
Capacitive load C = 30 pF
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output
characteristics.
Figure 74. SDIO high-speed mode
tf
tr
tC
tW(CKH)
tW(CKL)
CK
tOV
tOH
D, CMD
(output)
tISU
tIH
D, CMD
(input)
ai14887
DocID022063 Rev 4
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Electrical characteristics
STM32F415xx, STM32F417xx
Figure 75. SD default mode
CK
tOVD
tOHD
D, CMD
(output)
ai14888
Parameter
Conditions
Min
Typ
Max
Unit
48
MHz
-
8/3
tW(CKL)
fpp = 48 MHz
8.5
tW(CKH)
fpp = 48 MHz
8.3
10
ns
fpp = 48 MHz
tIH
fpp = 48 MHz
ns
fpp = 48 MHz
4.5
tOH
fpp = 48 MHz
ns
fpp = 24 MHz
1.5
tIHD
fpp = 24 MHz
0.5
ns
fpp = 24 MHz
4.5
tOHD
fpp = 24 MHz
0.5
ns
5.3.28
RTC characteristics
Table 89. RTC characteristics
158/186
Symbol
Parameter
Conditions
Any read/write operation
from/to an RTC register
DocID022063 Rev 4
Min
Max
STM32F415xx, STM32F417xx
Package characteristics
Package characteristics
6.1
DocID022063 Rev 4
159/186
Package characteristics
STM32F415xx, STM32F417xx
Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline
e1
A1 ball location
D
Detail A
E
e2
G
A2
F
A
Bump side
Side view
Detail A
rotated by 90 C
A1
eee
Seating plane
A0JW_ME
Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
0.520
0.570
0.620
0.0205
0.0224
0.0244
A1
0.165
0.190
0.215
0.0065
0.0075
0.0085
A2
0.350
0.380
0.410
0.0138
0.015
0.0161
0.240
0.270
0.300
0.0094
0.0106
0.0118
4.178
4.218
4.258
0.1645
0.1661
0.1676
3.964
3.969
4.004
0.1561
0.1563
0.1576
0.400
0.0157
e1
3.600
0.1417
e2
3.200
0.126
0.312
0.0123
0.385
0.0152
eee
0.050
160/186
DocID022063 Rev 4
0.0020
STM32F415xx, STM32F417xx
Package characteristics
E1
D1
D
L1
L
ai14398b
Table 91. LQFP64 10 x 10 mm 64 pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
1.600
A1
0.050
A2
1.350
0.170
0.090
Max
0.0630
0.150
0.0020
0.0059
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
0.0079
12.000
0.4724
D1
10.000
0.3937
12.000
0.4724
E1
10.000
0.3937
0.500
0.0197
3.5
3.5
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
N
1.000
0.0394
Number of pins
64
DocID022063 Rev 4
161/186
Package characteristics
STM32F415xx, STM32F417xx
Figure 78. LQFP64 recommended footprint
48
33
0.3
49
12.7
32
0.5
10.3
10.3
64
17
1.2
1
16
7.8
12.7
ai14909
162/186
DocID022063 Rev 4
STM32F415xx, STM32F417xx
Package characteristics
A1
A2
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
A1
K
ccc C
L1
D1
D3
51
75
50
100
E3
E1
76
26
PIN 1
1
IDENTIFICATION
25
e
1L_ME_V4
Table 92. LQPF100 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1)
millimeters
inches
Symbol
Min
Typ
Max
Min
Typ
1.600
A1
0.050
A2
1.350
0.170
0.090
15.800
D1
13.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
16.000
16.200
0.6220
0.6299
0.6378
14.000
14.200
0.5433
0.5512
0.5591
12.000
0.0059
0.0079
0.4724
15.80v
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
12.000
0.4724
0.500
0.0197
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0
3.5
0.0236
0.0295
0.0394
7
0.080
3.5
7
0.0031
DocID022063 Rev 4
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Package characteristics
STM32F415xx, STM32F417xx
Figure 80. LQFP100 recommended footprint
75
51
76
50
0.5
0.3
16.7
14.3
100
26
1.2
25
12.3
16.7
ai14906
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DocID022063 Rev 4
STM32F415xx, STM32F417xx
Package characteristics
Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
Seating plane
C
A2 A1
0.25 mm
gage plane
ccc
C
k
D
D1
A1
D3
L
L1
108
73
72
109
E3 E1
144
37
Pin 1
identification
36
ME_1A
Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
1.600
A1
0.050
A2
1.350
0.170
0.090
21.800
D1
19.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
22.000
22.200
0.8583
0.8661
0.874
20.000
20.200
0.7795
0.7874
0.7953
17.500
0.0059
0.0079
0.689
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
17.500
0.6890
0.500
0.0197
L
L1
0.450
0.600
0.750
1.000
0.0177
0.0236
0.0295
0.0394
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Package characteristics
STM32F415xx, STM32F417xx
Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
k
Min
Typ
Max
Min
Typ
Max
3.5
3.5
ccc
0.080
0.0031
108
109
73
1.35
72
0.35
0.5
17.85
19.9
144
22.6
37
1
36
19.9
22.6
ai14905c
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Package characteristics
Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm,
package outline
C Seating plane
A2
ddd
A1
A1 ball
A1 ball
identifier index area
e
A
F
e
B
R
15
BOTTOM VIEW
TOP VIEW
b (176 + 25 balls)
eee M C A B
fff M C
A0E7_ME_V4
Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.002
0.0031
0.0043
0.400
0.450
0.500
0.0157
0.0177
0.0197
0.230
0.280
0.330
0.0091
0.0110
0.0130
9.900
10.000
10.100
0.3898
0.3937
0.3976
9.900
10.000
10.100
0.3898
0.3937
0.3976
A2
e
F
0.650
0.425
0.450
0.0256
0.475
0.0167
0.0177
0.0187
ddd
0.080
0.0031
eee
0.150
0.0059
fff
0.080
0.0031
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Package characteristics
STM32F415xx, STM32F417xx
Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline
C Seating plane
0.25 mm
gauge plane
A A2
A1
ccc C
A1
HD
L1
ZD
ZE
89
132
88
133
b
176
Pin 1
identification
HE
45
1
44
e
1T_ME
Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
1.600
Max
0.0630
A1
0.050
0.150
0.0020
A2
1.350
1.450
0.0531
0.0060
0.170
0.270
0.0067
0.0106
0.090
0.200
0.0035
0.0079
23.900
24.100
0.9409
0.9488
23.900
24.100
0.9409
0.9488
0.500
0.0197
HD
25.900
26.100
1.0200
1.0276
HE
25.900
26.100
1.0200
1.0276
0.450
0.750
0.0177
0.0295
L1
1.000
0.0394
ZD
1.250
0.0492
ZE
1.250
0.0492
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Package characteristics
Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
ccc
Min
Typ
Max
0.080
0.0031
1.2
1
176
133
132
0.5
21.8
26.7
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
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Package characteristics
6.2
STM32F415xx, STM32F417xx
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL IOL) + ((VDD VOH) IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 96. Package thermal characteristics
Symbol
JA
Parameter
Value
46
43
40
38
39
Unit
C/W
38.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Part numbering
Part numbering
Table 97. Ordering information scheme
Example:
STM32
F 415 R E
6 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
415 = STM32F41x, connectivity, cryptographic acceleration
417= STM32F41x, connectivity, camera interface, Ethernet
cryptographic acceleration, Ethernet,
Pin count
R = 64 pins
O = 90 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
Package
T = LQFP
H = UFBGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, 40 to 85 C.
7 = Industrial temperature range, 40 to 105 C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Appendix A
A.1
STM32F415xx, STM32F417xx
VBUS
DM
OSC_IN
PA11//PB14
DP
PA12/PB15
VSS
OSC_OUT
STM32F4xx
MS19000V5
1. External voltage regulator only needed when building a VBUS powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Figure 87. USB controller configured as host-only and used in full speed mode
VDD
EN
GPIO
GPIO+IRQ
Overcurrent
Current limiter
power switch(1)
5 V Pwr
VBUS
OSC_IN
PA11//PB14
PA12/PB15
DM
DP
VSS
OSC_OUT
STM32F4xx
MS19001V4
1. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
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Figure 88. USB controller configured in dual mode and used in full speed mode
VDD
5 V to VDD
VDD
EN
GPIO+IRQ
Overcurrent
Current limiter
power switch(2)
5 V Pwr
STM32F4xx
VBUS
PA9/PB13
DM
PA11/PB14
OSC_IN
OSC_OUT
PA12/PB15
PA10/PB12
DP
ID
(3)
VSS
USBmicro-AB connector
GPIO
MS19002V3
1. External voltage regulator only needed when building a VBUS powered device.
2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
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A.2
STM32F415xx, STM32F417xx
FS PHY
USB HS
OTG Ctrl
DP
DM
not connected
DP
ULPI_CLK
DM
ULPI_D[7:0]
ULPI
ID(2)
ULPI_DIR
VBUS
ULPI_STP
USB
connector
VSS
ULPI_NXT
High speed
OTG PHY
PLL
XT1
24 or 26 MHz XT(1)
MCO1 or MCO2
XI
MS19005V2
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F41x
with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible
connection.
2. The ID pin is required in dual role only.
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A.3
STM32
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
MII_CRS
MII_COL
MCU
Ethernet
MAC 10/100
HCLK(1)
Ethernet
PHY 10/100
MII
= 15 pins
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
IEEE1588 PTP
Timer
input
trigger Timestamp
TIM2
comparator
MII + MDC
= 17 pins
MDIO
MDC
PPS_OUT(2)
XTAL
25 MHz
OSC
HCLK
PLL
PHY_CLK 25 MHz
MCO1/MCO2
XT1
MS19968V1
STM32
Ethernet
PHY 10/100
MCU
RMII_TX_EN
Ethernet
MAC 10/100
RMII_TXD[1:0]
RMII_RXD[1:0]
HCLK(1)
RMII_CRX_DV
RMII_REF_CLK
IEEE1588 PTP
Timer
input
trigger Timestamp
TIM2
comparator
RMII
= 7 pins
RMII + MDC
= 9 pins
MDIO
MDC
/2 or /20
2.5 or 25 MHz synchronous 50 MHz
OSC
50 MHz
HCLK
PLL
PHY_CLK
50 MHz
XT1
50 MHz
MS19969V1
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STM32F415xx, STM32F417xx
Figure 92. RMII with a 25 MHz crystal and PHY with PLL
STM32F
Ethernet
PHY 10/100
MCU
RMII_TX_EN
Ethernet
MAC 10/100
RMII_TXD[1:0]
RMII_RXD[1:0]
HCLK(1)
RMII_CRX_DV
RMII_REF_CLK
IEEE1588 PTP
RMII
= 7 pins
REF_CLK
MDIO
Timer
input
trigger Timestamp
TIM2
comparator
RMII + MDC
= 9 pins
MDC
/2 or /20
2.5 or 25 MHz synchronous 50 MHz
XTAL
25 MHz
OSC
PLL
HCLK
PLL
MCO1/MCO2
MS19970V1
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Revision history
Revision history
Table 98. Document revision history
Date
Revision
15-Sep-2011
Initial release.
24-Jan-2012
Changes
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Revision history
STM32F415xx, STM32F417xx
Table 98. Document revision history (continued)
Date
24-Jan-2012
178/186
Revision
Changes
Added V12 in Table 19: Embedded reset and power control block
characteristics.
Updated Table 21: Typical and maximum current consumption in Run
mode, code with data processing running from Flash memory (ART
accelerator disabled) and Table 20: Typical and maximum current
consumption in Run mode, code with data processing running from
Flash memory (ART accelerator enabled) or RAM. Added Figure ,
Figure 25, Figure 26, and Figure 27.
Updated Table 22: Typical and maximum current consumption in Sleep
mode and removed Note 1.
Updated Table 23: Typical and maximum current consumptions in Stop
mode and Table 24: Typical and maximum current consumptions in
Standby mode, Table 25: Typical and maximum current consumptions
in VBAT mode, and Table 26: Switching output I/O current
consumption.
Section : On-chip peripheral current consumption: modified conditions,
and updated Table 27: Peripheral current consumption and Note 2.
Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in
Table 29: High-speed external user clock characteristics.
2
Added Cin(LSE) in Table 30: Low-speed external user clock
(continued) characteristics.
Updated maximum PLL input clock frequency, removed related note,
and deleted jitter for MCO for RMII Ethernet typical value in Table 35:
Main PLL characteristics. Updated maximum PLLI2S input clock
frequency and removed related note in Table 36: PLLI2S (audio PLL)
characteristics.
Updated Section : Flash memory to specify that the devices are
shipped to customers with the Flash memory erased. Updated
Table 38: Flash memory characteristics, and added tME in Table 39:
Flash memory programming.
Updated Table 42: EMS characteristics, and Table 43: EMI
characteristics.
Updated Table 56: I2S dynamic characteristics
Updated Figure 46: ULPI timing diagram and Table 62: ULPI timing.
Added tCOUNTER and tMAX_COUNT in Table 51: Characteristics of TIMx
connected to the APB1 domain and Table 52: Characteristics of TIMx
connected to the APB2 domain. Updated Table 65: Dynamic
characteristics: Ethernet MAC signals for RMII.
Removed USB-IF certification in Section : USB OTG FS
characteristics.
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Revision history
Table 98. Document revision history (continued)
Date
24-Jan-2012
Revision
Changes
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Revision history
STM32F415xx, STM32F417xx
Table 98. Document revision history (continued)
Date
31-May-2012
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Revision
Changes
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Revision history
Table 98. Document revision history (continued)
Date
31-May-2012
Revision
Changes
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Revision history
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Table 98. Document revision history (continued)
Date
04-Jun-2013
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Revision
Changes
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Revision history
Table 98. Document revision history (continued)
Date
04-Jun-2013
Revision
Changes
Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array
10 10 0.6 mm, package outline
Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array
10 10 0.6 mm mechanical data
Updated Figure 5: STM32F41x block diagram
Updated Section 2: Description
Updated footnote (3) in Table 2: STM32F415xx and STM32F417xx:
features and peripheral counts
Updated Figure 3: Compatible board design between
STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Updated Figure 4: Compatible board design between STM32F2xx and
STM32F4xx for LQFP176 and BGA176 packages
Updated Section 2.2.14: Power supply schemes
Updated Section 2.2.15: Power supply supervisor
Updated Section 2.2.16: Voltage regulator, including figures.
Updated Table 14: General operating conditions, including footnote (2).
Updated Table 15: Limitations depending on the operating power
supply range, including footnote (3).
Updated footnote (1) in Table 67: ADC characteristics.
Updated footnote (3) in Table 68: ADC accuracy at fADC = 30 MHz.
Updated footnote (1) in Table 74: DAC characteristics.
Updated Figure 9: Regulator OFF.
Updated Figure 7: Power supply supervisor interconnection with
4
internal reset OFF.
(continued)
Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF
availability.
Updated footnote (2) of Figure 21: Power supply scheme.
Replaced respectively I2S3S_WS" by "I2S3_WS, I2S3S_CK by
I2S3_CK and FSMC_BLN1 by FSMC_NBL1 in Table 9: Alternate
function mapping.
Added EVENTOUT as alternate function AF15 for pin PC13, PC14,
PC15, PH0, PH1, PI8 in Table 9: Alternate function mapping
Replaced DCMI_12 by DCMI_D12 in Table 7: STM32F41x pin and
ball definitions.
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Revision history
STM32F415xx, STM32F417xx
Table 98. Document revision history (continued)
Date
04-Jun-2013
184/186
Revision
Changes
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Revision history
Table 98. Document revision history (continued)
Date
04-Jun-2013
Revision
Changes
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