entity contador is

Port ( Clk : in bit;

Rst : in bit;
Load_p : in bit;
Cta_BCD : in bit;
SW : in bit_VECTOR (11 downto 0);
Qreg : out bit_VECTOR (11 downto 0);
Tc : out bit);
end contador;
architecture Behavioral of contador is
signal u,d,c :bit_VECTOR (3 downto 0):="0000";
------------------------------------------sobrecarga del operado +
function "+" (A: in bit_vector; B: in bit_vector)
return bit_vector is
variable a_v: bit_vector(A'Range);
variable b_v: bit_vector(A'Range);
variable c: bit;
variable sum: bit_vector(A'range);
begin
a_v:=A;
b_v:=B;
c:='0';
for i in a'reverse_range loop
sum(i):= a_v(i) xor b_v(i) xor c;
c:= (a_v(i) and b_v(i)) or (b_v(i) and c) or (a_v(i) and c);
end loop;
return sum;
end function"+";
begin
Reg:
process(Clk)
begin if(clk'event and clk='1') then
if(Rst='1') then
u <="0000";
d <="0000";
c <="0000";
elsif(Load_p='1') then
u <=SW(3 downto 0);
d <=SW(7 downto 4);
c <=SW(11 downto 8);
elsif(Cta_BCD='1') then
u<=u+"0001";
if(u="1001") then
d<=d+"0001";
u <="0000";
if(d="1001") then
c<= c+"0001";
d <="0000";
if(c="1001") then
c<="0000";
end if;
end if;
end if;
end if;
end if;
end process Reg;
-----------------------------------------Qreg <= c & d & u;

Tc<='1' when ( c="1001" and d="1001" and u="1001" and

Cta_BCD='1') else '0';
end Behavioral;