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Pic 16 F 630
Pic 16 F 630
Data Sheet
14-Pin FLASH-Based 8-Bit
CMOS Microcontrollers
DS40039C
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, dsPIC, dsPICDEM.net, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming,
ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net,
PowerCal, PowerInfo, PowerTool, rfPIC, rfLAB, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS40039C - page ii
PIC16F630/676
14-Pin FLASH-Based 8-Bit CMOS Microcontroller
High Performance RISC CPU:
Standby Current:
- 1 nA @ 2.0V, typical
Operating Current:
- 8.5 A @ 32 kHz, 2.0V, typical
- 100 A @ 1 MHz, 2.0V, typical
Watchdog Timer Current
- 300 nA @ 2.0V, typical
Timer1 oscillator current:
- 4 A @ 32 kHz, 2.0V, typical
Peripheral Features:
Device
Program
Memory
Data Memory
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
128
12
1/1
128
12
1/1
FLASH
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F630
1024
64
PIC16F676
1024
64
DS40039C-page 1
PIC16F630/676
Pin Diagrams
14-pin PDIP, SOIC, TSSOP
DS40039C-page 2
1
2
3
4
5
6
7
PIC16F676
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/AN3/CLKOUT
RA3/MCLR/VPP
RC5
RC4
RC3/AN7
1
2
3
4
5
6
7
PIC16F630
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5
RC4
RC3
14
13
12
11
10
9
8
14
13
12
11
10
9
8
VSS
RA0/CIN+/ICSPDAT
RA1/CIN-/ICSPCLK
RA2/COUT/T0CKI/INT
RC0
RC1
RC2
VSS
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
PIC16F630/676
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization .................................................................................................................................................................. 7
3.0 Ports A and C ............................................................................................................................................................................ 19
4.0 Timer0 Module .......................................................................................................................................................................... 29
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 32
6.0 Comparator Module .................................................................................................................................................................. 37
7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only) ................................................................................................... 43
8.0 Data EEPROM Memory............................................................................................................................................................ 49
9.0 Special Features of the CPU .................................................................................................................................................... 53
10.0 Instruction Set Summary ........................................................................................................................................................... 71
11.0 Development Support ............................................................................................................................................................... 79
12.0 Electrical Specifications ............................................................................................................................................................ 85
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 107
14.0 Packaging Information ............................................................................................................................................................ 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 121
Appendix B: Device Differences ....................................................................................................................................................... 121
Appendix C: Device Migrations ......................................................................................................................................................... 122
Appendix D: Migrating from other PICmicro Devices ...................................................................................................................... 122
Index ................................................................................................................................................................................................. 123
On-Line Support ................................................................................................................................................................................ 127
Systems Information and Upgrade Hot Line ..................................................................................................................................... 127
Reader Response ............................................................................................................................................................................. 128
Product Identification System ........................................................................................................................................................... 129
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
DS40039C-page 3
PIC16F630/676
NOTES:
DS40039C-page 4
PIC16F630/676
1.0
DEVICE OVERVIEW
FIGURE 1-1:
Data Bus
Program Counter
PORTA
RA0
FLASH
RA1
1K x 14
Program
Memory
Program
Bus
8-Level Stack
(13-bit)
14
RAM
RA2
64
bytes
RA3
RA4
File
Registers
RAM Addr
RA5
Addr MUX
Instruction reg
7
Direct Addr
Indirect
Addr
FSR reg
STATUS reg
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
Power-up
Timer
Instruction
Decode &
Control
OSC1/CLKIN
Oscillator
Start-up Timer
Power-on
Reset
Timing
Generation
ALU
8
Watchdog
Timer
Brown-out
Detect
OSC2/CLKOUT
MUX
W reg
Internal
Oscillator
T1G
MCLR VDD
VSS
T1CKI
Timer0
Timer1
T0CKI
Analog
Comparator
and reference
EEDATA
8 128 bytes
DATA
EEPROM
EEADDR
DS40039C-page 5
PIC16F630/676
TABLE 1-1:
Name
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/
ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RA3/MCLR/VPP
RA4/T1G/AN3/OSC2/
CLKOUT
RA5/T1CKI/OSC1/CLKIN
RC0/AN4
RC1/AN5
RC2/AN6
RC3/AN7
RC4
RC5
VSS
VDD
Legend:
Function
Input
Type
Output
Type
RA0
TTL
CMOS
AN0
CIN+
ICSPDAT
AN
AN
TTL
CMOS
RA1
TTL
CMOS
AN1
CINVREF
ICSPCLK
AN
AN
AN
ST
RA2
ST
CMOS
AN2
COUT
T0CKI
INT
RA3
MCLR
VPP
RA4
AN
ST
ST
TTL
ST
HV
TTL
CMOS
CMOS
T1G
AN3
OSC2
CLKOUT
ST
AN3
XTAL
CMOS
RA5
TTL
CMOS
T1CKI
ST
OSC1
XTAL
CLKIN
ST
RC0
TTL
AN4
AN4
RC1
TTL
AN5
AN5
RC2
TTL
AN6
AN6
RC3
TTL
AN7
AN7
RC4
TTL
RC5
TTL
VSS
Power
VDD
Power
Shade = PIC16F676 only
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
DS40039C-page 6
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
Bi-directional I/O w/ programmable pull-up and
Interrupt-on-change
A/D Channel 0 input
Comparator input
Serial Programming Data I/O
Bi-directional I/O w/ programmable pull-up and
Interrupt-on-change
A/D Channel 1 input
Comparator input
External Voltage reference
Serial Programming Clock
Bi-directional I/O w/ programmable pull-up and
Interrupt-on-change
A/D Channel 2 input
Comparator output
Timer0 clock input
External Interrupt
Input port with Interrupt-on-change
Master Clear
Programming voltage
Bi-directional I/O w/ programmable pull-up and
Interrupt-on-change
Timer1 gate
A/D Channel 3 input
Crystal/Resonator
FOSC/4 output
Bi-directional I/O w/ programmable pull-up and
Interrupt-on-change
Timer1 clock
Crystal/Resonator
External clock input/RC oscillator connection
Bi-directional I/O
A/D Channel 4 input
Bi-directional I/O
A/D Channel 5 input
Bi-directional I/O
A/D Channel 6 input
Bi-directional I/O
A/D Channel 7 input
Bi-directional I/O
Bi-directional I/O
Ground reference
Positive supply
PIC16F630/676
2.0
MEMORY ORGANIZATION
2.2
2.1
FIGURE 2-1:
CALL, RETURN
RETFIE, RETLW
2.2.1
13
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
1FFFh
DS40039C-page 7
PIC16F630/676
2.2.2
FIGURE 2-2:
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON
ADRESH(2)
ADCON0(2)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Registers
File
Address
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCAL
ANSEL(2)
WPUA
IOCA
VRCON
EEDAT
EEADR
EECON1
EECON2(1)
ADRESL(2)
ADCON1(2)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
Bank 0
FFh
Bank 1
DS40039C-page 8
PIC16F630/676
TABLE 2-1:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOD
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
18,61
01h
TMR0
xxxx xxxx
29
02h
PCL
0000 0000
17
03h
STATUS
0001 1xxx
11
04h
FSR
05h
PORTA
06h
07h
(2)
IRP
(2)
RP1
RP0
TO
PD
DC
PORTC
xxxx xxxx
18
--xx xxxx
19
--xx xxxx
26
Unimplemented
08h
Unimplemented
09h
Unimplemented
---0 0000
17
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
13
PIR1
EEIF
ADIF
CMIF
TMR1IF
00-- 0--0
15
0Ah
PCLATH
0Bh
0Ch
0Dh
0Eh
TMR1L
Unimplemented
Holding register for the Least Significant Byte of the 16-bit TMR1
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
10h
T1CON
11h
12h
13h
xxxx xxxx
32
xxxx xxxx
32
-000 0000
34
Unimplemented
Unimplemented
Unimplemented
14h
Unimplemented
15h
Unimplemented
16h
Unimplemented
17h
Unimplemented
18h
Unimplemented
-0-0 0000
37
19h
CMCON
T1GE
COUT
T1CKPS1
T1CKPS0
CINV
T1OSCEN
CIS
T1SYNC
TMR1CS
CM2
CM1
TMR1ON
CM0
1Ah
Unimplemented
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh
ADRESH(3)
xxxx xxxx
44
1Fh
ADCON0(3)
00-0 0000
45,61
Legend:
Note 1:
2:
3:
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM
VCFG
CHS2
CHS1
CHS0
GO/DONE
ADON
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP & RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
DS40039C-page 9
PIC16F630/676
TABLE 2-2:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOD
Page
xxxx xxxx
1111 1111
18,61
12,30
Bank 1
80h
81h
82h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
OPTION_REG
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
RAPU
PCL
Program Counter's (PC) Least Significant Byte
83h
STATUS
84h
FSR
IRP(2)
RP1(2)
RP0
Indirect data memory address pointer
85h
86h
TRISA
Unimplemented
87h
88h
TRISC
Unimplemented
89h
8Ah
8Bh
PCLATH
INTCON
8Ch
8Dh
PIE1
8Eh
PCON
8Fh
90h
OSCCAL
91h
92h
ANSEL(3)
93h
94h
TO
PD
DC
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Unimplemented
GIE
PEIE
EEIE
ADIE
Unimplemented
CAL5
T0IE
RAIF
0000 0000
17
0001 1xxx
11
xxxx xxxx
18
--11 1111
19
--11 1111
---0 0000
0000 0000
17
13
CMIE
TMR1IE
00-- 0--0
14
POR
BOD
16
1000 00--
16
1111 1111
46
CAL4
CAL3
CAL2
CAL1
CAL0
ANS7
ANS6
Unimplemented
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
Unimplemented
Unimplemented
95h
WPUA
WPUA5
WPUA4
WPUA2
WPUA1
WPUA0
--11 -111
20
96h
IOCA
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
21
0-0- 0000
0000 0000
42
49
0000 0000
---- x000
49
50
49
44
-000 ----
45,61
97h
98h
99h
9Ah
VRCON
EEDAT
9Bh
9Ch
EEADR
EECON1
9Dh
9Eh
EECON2
ADRESL(3)
9Fh
ADCON1(3)
Legend:
Note 1:
2:
3:
Unimplemented
Unimplemented
VREN
VRR
VR3
VR2
VR1
VR0
WRERR
WREN
WR
RD
ADCS2
ADCS1
ADCS0
= Unimplemented locations read as 0, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP & RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
DS40039C-page 10
PIC16F630/676
2.2.2.1
STATUS Register
REGISTER 2-1:
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
DC
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
For borrow the polarity is reversed. A subtraction is executed by adding the twos
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 11
PIC16F630/676
2.2.2.2
OPTION Register
Note:
TMR0/WDT prescaler
External RA2/INT interrupt
TMR0
Weak pull-ups on PORTA
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS40039C-page 12
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
2.2.2.3
INTCON Register
Note:
REGISTER 2-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 13
PIC16F630/676
2.2.2.4
PIE1 Register
REGISTER 2-4:
Note:
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIE
ADIE
CMIE
TMR1IE
bit 7
bit 0
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
DS40039C-page 14
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
2.2.2.5
PIR1 Register
REGISTER 2-5:
Note:
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIF
ADIF
CMIF
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5-4
Unimplemented: Read as 0
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 15
PIC16F630/676
2.2.2.6
PCON Register
REGISTER 2-6:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
POR
BOD
bit 7
bit 0
bit 7-2
bit 1
bit 0
2.2.2.7
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
OSCCAL Register
REGISTER 2-7:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
bit 7-2
bit 1-0
DS40039C-page 16
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
2.3
2.3.2
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
PC
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
STACK
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
COMPUTED GOTO
DS40039C-page 17
PIC16F630/676
2.4
EXAMPLE 2-1:
FIGURE 2-4:
movlw
movwf
clrf
incf
btfss
goto
NEXT
0x20
FSR
INDF
FSR
FSR,4
NEXT
CONTINUE
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
Direct Addressing
RP1(1) RP0
INDIRECT ADDRESSING
From Opcode
Indirect Addressing
IRP(1)
Bank Select
01
10
FSR Register
Location Select
11
00h
180h
Data
Memory
Not Used
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
DS40039C-page 18
PIC16F630/676
3.0
PORTS A AND C
3.1
PORTA is an 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
The exception is RA3, which is input only and its TRIS
bit will always read as 1. Example 3-1 shows how to
initialize PORTA.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the port
data latch. RA3 reads 0 when MCLREN = 1.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
REGISTER 3-1:
EXAMPLE 3-1:
bcf
clrf
movlw
movwf
bsf
clrf
movlw
movwf
STATUS,RP0
PORTA
05h
CMCON
STATUS,RP0
ANSEL
0Ch
TRISA
bcf
STATUS,RP0
3.2
INITIALIZING PORTA
;Bank 0
;Init PORTA
;Set RA<2:0> to
;digital I/O
;Bank 1
;digital I/O
;Set RA<3:2> as inputs
;and set RA<5:4,1:0>
;as outputs
;Bank 0
3.2.1
WEAK PULL-UP
Each of the PORTA pins, except RA3, has an individually configurable weak internal pull-up. Control bits
WPUAx enable or disable each pull-up. Refer to
Register 3-3. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RAPU bit (OPTION<7>).
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as 0
bit 5-0:
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 19
PIC16F630/676
REGISTER 3-2:
U-0
R/W-x
R/W-x
R-1
R/W-x
R/W-x
R/W-x
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as 0
bit 5-0:
Legend:
REGISTER 3-3:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
WPUA5
WPUA4
WPUA2
WPUA1
WPUA0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
3.2.2
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
INTERRUPT-ON-CHANGE
DS40039C-page 20
x = Bit is unknown
PIC16F630/676
REGISTER 3-4:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
bit 7
bit 0
bit 7-6
Unimplemented: Read as 0
bit 5-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 21
PIC16F630/676
3.2.3
3.2.3.1
RA0/AN0/CIN+
FIGURE 3-1:
Data Bus
WR
WPUA
D
CK
Analog
Input Mode
VDD
Weak
RAPU
RD
WPUA
Figure 3-1 shows the diagram for this pin. The RA0 pin
is configurable to function as one of the following:
a general purpose I/O
an analog input for the A/D (PIC16F676 only)
an analog input to the comparator
3.2.3.2
WR
PORTA
CK
VDD
Q
Q
I/O pin
RA1/AN1/CIN-/VREF
Figure 3-1 shows the diagram for this pin. The RA1 pin
is configurable to function as one of the following:
D
WR
TRISA
CK
Q
Q
VSS
Analog
Input Mode
RD
TRISA
RD
PORTA
D
WR
IOCA
CK
Q
Q
D
EN
RD
IOCA
D
EN
Interrupt-on-Change
RD PORTA
To Comparator
To A/D Converter
DS40039C-page 22
PIC16F630/676
3.2.3.3
3.2.3.4
RA2/AN2/T0CKI/INT/COUT
RA3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
FIGURE 3-3:
Data Bus
FIGURE 3-2:
Data Bus
WR
WPUA
D
CK
RD
TRISA
Analog
Input Mode
VDD
D
WR
PORTA
WR
IOCA
Analog
Input
Mode
COUT
Enable
CK
WR
TRISA
CK
CK
VSS
Q
Q
D
EN
RD
IOCA
VDD
D
EN
COUT
Interrupt-on-Change
1
0
MCLRE
RAPU
RD
WPUA
I/O pin
VSS
RD
PORTA
Weak
MCLRE
RESET
I/O pin
RD PORTA
Q
Q
VSS
Analog
Input Mode
RD
TRISA
RD
PORTA
D
WR
IOCA
CK
Q
Q
D
EN
RD
IOCA
D
EN
Interrupt-on-Change
RD PORTA
To TMR0
To INT
To A/D Converter
DS40039C-page 23
PIC16F630/676
3.2.3.5
3.2.3.6
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
FIGURE 3-5:
FIGURE 3-4:
Analog
Input Mode
Data Bus
WR
WPUA
D
CK
INTOSC
Mode
CLK(1)
Modes
Data Bus
VDD
WR
WPUA
Weak
OSC1
WR
PORTA
CK
CK
WR
PORTA
VSS
INTOSC/
RC/EC(2)
CK
WR
TRISA
CK
Q
Q
VSS
INTOSC
Mode
(1)
D
WR
IOCA
Q
Q
RD
PORTA
RD
PORTA
WR
IOCA
RD
TRISA
Analog
Input Mode
CK
CK
Q
Q
Interrupt-on-Change
D
EN
RD
IOCA
EN
RD
IOCA
VDD
I/O pin
I/O pin
CLKOUT
Enable
RD
TRISA
RAPU
1
0
Weak
OSC2
VDD
VDD
Oscillator
Circuit
CLKOUT
Enable
D
WR
TRISA
CK
TMR1LPEN(1)
Oscillator
Circuit
CLKOUT
Enable
FOSC/4
RD
WPUA
RAPU
RD
WPUA
D
EN
Interrupt-on-Change
EN
RD PORTA
RD PORTA
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
DS40039C-page 24
Note
PIC16F630/676
TABLE 3-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOD
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
05h
PORTA
Value on
all
other
RESETS
--uu uuuu
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 000u
19h
CMCON
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
81h
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRISA
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
--11 1111
ANS2
ANS1
ANS0
(1)
91h
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
1111 1111
1111 1111
95h
WPUA
WPUA5
WPUA4
WPUA2
WPUA1
WPUA0
--11 -111
--11 -111
96h
IOCA
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
--00 0000
DS40039C-page 25
PIC16F630/676
3.3
3.3.2
PORTC
PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either
digital I/O or analog input to A/D converter. For specific
information about individual functions such as the
comparator or the A/D, refer to the appropriate section
in this Data Sheet.
Note:
EXAMPLE 3-2:
bcf
clrf
bsf
clrf
movlw
movwf
STATUS,RP0
PORTC
STATUS,RP0
ANSEL
0Ch
TRISC
bcf
STATUS,RP0
3.3.1
FIGURE 3-7:
Data bus
D
WR
PORTC
CK
VDD
Q
I/O Pin
INITIALIZING PORTC
;Bank 0
;Init PORTC
;Bank 1
;digital I/O
;Set RC<3:2> as inputs
;and set RC<5:4,1:0>
;as outputs
;Bank 0
WR
TRISC
CK
Q
Q
VSS
RD
TRISC
RD
PORTC
FIGURE 3-6:
BLOCK DIAGRAM OF
RC0/RC1/RC2/RC3 PINs
Data bus
D
WR
PORTC
CK
VDD
Q
Q
I/O Pin
D
WR
TRISC
CK
Q
Q
VSS
Analog Input
Mode
RD
TRISC
RD
PORTC
To A/D Converter
DS40039C-page 26
PIC16F630/676
REGISTER 3-5:
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as 0
bit 5-0:
REGISTER 3-6:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as 0
bit 5-0:
TABLE 3-2:
Address
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOD
Value on all
other
RESETS
--uu uuuu
07h
PORTC
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
87h
TRISC
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
--11 1111
--11 1111
91h
ANSEL(1)
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
DS40039C-page 27
PIC16F630/676
NOTES:
DS40039C-page 28
PIC16F630/676
4.0
TIMER0 MODULE
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Note:
4.1
4.2
Timer0 Interrupt
Timer0 Operation
FIGURE 4-1:
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0SE
T0CS
8-bit
Prescaler
PSA
PSA
TMR0
PS0 - PS2
Watchdog
Timer
WDTE
1
WDT
Time-out
0
PSA
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
DS40039C-page 29
PIC16F630/676
4.3
REGISTER 4-1:
Note:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS40039C-page 30
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
4.4
Prescaler
EXAMPLE 4-1:
bcf
STATUS,RP0
clrwdt
clrf
TMR0
bsf
SWITCHING PRESCALER
ASSIGNMENT
EXAMPLE 4-2:
Address
CHANGING PRESCALER
(WDTTIMER0)
clrwdt
bsf
STATUS,RP0
movlw
movwf
bcf
TABLE 4-1:
STATUS,RP0
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
movlw
b00101111 ;Required if desired
movwf
OPTION_REG ; PS2:PS0 is
clrwdt
; 000 or 001
;
movlw
b00101xxx ;Set postscaler to
movwf
OPTION_REG ; desired WDT rate
bcf
STATUS,RP0 ;Bank 0
4.4.1
CHANGING PRESCALER
(TIMER0WDT)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
01h
TMR0
0Bh/8Bh
INTCON
81h
OPTION_REG
85h
TRISA
Legend:
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
DS40039C-page 31
PIC16F630/676
5.0
Note:
FIGURE 5-1:
TMR1ON
TMR1GE
Synchronized
Clock Input
0
TMR1H
TMR1L
1
LP Oscillator
T1SYNC
OSC1
OSC2
INTOSC
w/o CLKOUT
T1OSCEN
1
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
0
2
T1CKPS<1:0>
SLEEP Input
TMR1CS
LP
DS40039C-page 32
PIC16F630/676
5.1
5.2
FIGURE 5-2:
Timer1 Interrupt
5.3
Timer1 Prescaler
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
DS40039C-page 33
PIC16F630/676
REGISTER 5-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
DS40039C-page 34
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
5.4
Timer1 Operation in
Asynchronous Counter Mode
5.5
Note:
5.4.1
Note:
Address
TABLE 5-1:
Name
Timer1 Oscillator
5.6
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
RESETS
Bit 0
Value on
POR, BOD
RAIF
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
EEIE
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
ADIE
CMIE
8Ch
PIE1
Legend:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
DS40039C-page 35
PIC16F630/676
NOTES:
DS40039C-page 36
PIC16F630/676
6.0
COMPARATOR MODULE
The PIC16F630/676 devices have one analog comparator. The inputs to the comparator are multiplexed with
the RA0 and RA1 pins. There is an on-chip Comparator
REGISTER 6-1:
R-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COUT
CINV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
Unimplemented: Read as 0
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 37
PIC16F630/676
6.1
Comparator Operation
TABLE 6-1:
Input Conditions
CINV
COUT
FIGURE 6-1:
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
DS40039C-page 38
PIC16F630/676
6.2
Comparator Configuration
FIGURE 6-2:
CM2:CM0 = 000
CM2:CM0 = 111
RA1/CIN-
RA0/CIN+
RA2/COUT
RA1/CIN-
RA0/CIN+
RA2/COUT
CM2:CM0 = 010
CM2:CM0 = 100
RA1/CIN-
RA0/CIN+
RA2/COUT
COUT
RA1/CIN-
RA0/CIN+
RA2/COUT
COUT
CM2:CM0 = 011
CM2:CM0 = 101
RA1/CIN-
RA0/CIN+
RA2/COUT
COUT
RA1/CIN-
RA0/CIN+
RA2/COUT
CIS = 0
CIS = 1
COUT
CM2:CM0 = 001
CM2:CM0 = 110
RA1/CIN-
RA0/CIN+
RA2/COUT
COUT
RA1/CIN-
RA0/CIN+
RA2/COUT
CIS = 0
CIS = 1
COUT
DS40039C-page 39
PIC16F630/676
6.3
FIGURE 6-3:
Rs < 10K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
Leakage
500 nA
Vss
CPIN
VT
ILEAKAGE
RIC
RS
VA
Legend:
6.4
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Comparator Output
FIGURE 6-4:
To RA2/T0CKI pin
To Data Bus
RD CMCON
CVREF
D
EN
CINV
CM2:CM0
D
RD CMCON
EN
RESET
DS40039C-page 40
PIC16F630/676
6.5
Comparator Reference
6.5.1
FIGURE 6-5:
6.5.2
VOLTAGE REFERENCE
ACCURACY/ERROR
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR3:VR0
6.6
6.7
6.8
Effects of a RESET
DS40039C-page 41
PIC16F630/676
REGISTER 6-2:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
6.9
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
Comparator Interrupts
a)
b)
TABLE 6-2:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
19h
CMCON
COUT
CINV
CIS
CM2
CM1
EEIE
ADIE
VREN
8Ch
PIE1
85h
TRISA
99h
VRCON
Legend:
x = Bit is unknown
TRISA5 TRISA4
VRR
Value on
all other
RESETS
Bit 0
Value on
POR, BOD
RAIF
CMIE
TRISA3
TRISA2
TRISA1
VR3
VR2
VR1
VR0
x = unknown, u = unchanged, - = unimplemented, read as 0. Shaded cells are not used by the comparator module.
DS40039C-page 42
PIC16F630/676
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC16F676 ONLY)
FIGURE 7-1:
VREF
VCFG = 1
RA0/AN0
RA1/AN1/VREF
ADC
RA2/AN2
10
GO/DONE
RA4/AN3
RC0/AN4
ADFM
RC1/AN5
10
ADON
RC2/AN6
ADRESH
RC3/AN7
ADRESL
VSS
CHS2:CHS0
7.1
7.1.1
7.1.2
CHANNEL SELECTION
7.1.3
VOLTAGE REFERENCE
7.1.4
CONVERSION CLOCK
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
DS40039C-page 43
PIC16F630/676
TABLE 7-1:
Device Frequency
Operation
ADCS2:ADCS0
20 MHz
5 MHz
4 MHz
1.25 MHz
000
100 ns(2)
400 ns(2)
500 ns(2)
1.6 s
2 TOSC
4 TOSC
100
200 ns(2)
800 ns(2)
1.0 s(2)
3.2 s
001
400 ns(2)
1.6 s
2.0 s
6.4 s
8 TOSC
101
800 ns(2)
3.2 s
4.0 s
12.8 s(3)
16 TOSC
(3)
32 TOSC
010
1.6 s
6.4 s
8.0 s
25.6 s(3)
(3)
(3)
64 TOSC
110
3.2 s
12.8 s
16.0 s
51.2 s(3)
A/D RC
x11
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during SLEEP.
7.1.5
STARTING A CONVERSION
Note:
7.1.6
FIGURE 7-2:
CONVERSION OUTPUT
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
Unimplemented: Read as 0
MSB
bit 7
Unimplemented: Read as 0
DS40039C-page 44
bit 0
LSB
bit 0
bit 7
bit 0
PIC16F630/676
REGISTER 7-1:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4-2
bit 1
bit 0
REGISTER 7-2:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
ADCS2
ADCS1
ADCS0
bit 7
bit 7:
bit 6-4:
Unimplemented: Read as 0.
ADCS<2:0>: A/D Conversion Clock Select bits
000 =
001 =
010 =
x11 =
100 =
101 =
110 =
bit 3-0:
bit 0
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
FOSC/4
FOSC/16
FOSC/64
Unimplemented: Read as 0.
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 45
PIC16F630/676
REGISTER 7-3:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
bit 7
bit 7-0:
bit 0
ANS<7:0>: Analog Select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit
must be set to Input mode in order to allow external control of the voltage on the pin.
Legend:
DS40039C-page 46
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
7.2
EQUATION 7-1:
TACQ
TC
TACQ
ACQUISITION TIME
TAMP + TC + TCOFF
2s + TC + [(Temperature -25C)(0.05s/C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1k + 7k + 10k) In(0.0004885)
16.47s
2s + 16.47s + [(50C -25C)(0.05s/C)
19.72s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
FIGURE 7-3:
ANx
VA
CPIN
5 pF
VT = 0.6V
VT = 0.6V
Sampling
Switch
RIC 1K SS RSS
CHOLD
= DAC capacitance
= 120 pF
I LEAKAGE
500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
DS40039C-page 47
PIC16F630/676
7.3
TABLE 7-2:
Address
PORTA
07h
PORTC
7.4
Effects of RESET
Name
05h
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOD
Value on
all other
RESETS
Bit 7
Bit 6
PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu
PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
CMIF
1Eh
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
RAIF
ADFM
VCFG
CHS2
CHS1
CHS0
GO
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
EEIE
ADIE
CMIE
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
1Fh
ADCON0
85h
TRISA
87h
TRISC
8Ch
PIE1
91h
ANSEL
ANS7
9Eh
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
9Fh
ADCON1
ADCS2
ADCS1
ADCS0
ANS0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
DS40039C-page 48
PIC16F630/676
8.0
EECON1
EECON2 (not a physically implemented register)
EEDATA
EEADR
REGISTER 8-1:
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-0
R/W-0
EEDAT2 EEDAT1
R/W-0
EEDAT0
bit 7
bit 7-0
bit 0
REGISTER 8-2:
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
bit 7
bit 6-0
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
DS40039C-page 49
PIC16F630/676
8.1
EEADR
8.2
REGISTER 8-3:
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40039C-page 50
R = Readable bit
W = Writable bit
- n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
PIC16F630/676
8.3
EXAMPLE 8-1:
bsf
movlw
movwf
bsf
movf
8.4
STATUS,RP0
CONFIG_ADDR
EEADR
EECON1,RD
EEDATA,W
;Bank 1
;
;Address to read
;EE Read
;Move data to W
8.5
EXAMPLE 8-3:
Required
Sequence
EXAMPLE 8-2:
bsf
bsf
bcf
movlw
movwf
movlw
movwf
bsf
bsf
STATUS,RP0
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
WRITE VERIFY
WRITE VERIFY
bcf
:
bsf
movf
STATUS,RP0
STATUS,RP0
EEDATA,W
bsf
EECON1,RD
xorwf EEDATA,W
btfss STATUS,Z
goto
WRITE_ERR
:
8.5.1
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
The Data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
FLASH program memory.
8.6
PROTECTION AGAINST
SPURIOUS WRITE
DS40039C-page 51
PIC16F630/676
8.7
TABLE 8-1:
Address
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EEIF
ADIF
CMIF
9Ah
EEDATA
9Bh
EEADR
9Ch
EECON1
9Dh
Bit 0
Value on all
other
RESETS
Value on
POR, BOD
WR
RD
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM module.
Note 1: EECON2 is not a physical register.
DS40039C-page 52
PIC16F630/676
9.0
DS40039C-page 53
PIC16F630/676
9.1
Configuration Bits
Note:
REGISTER 9-1:
R/P-1 R/P-1
BG1
bit 13
bit 13-12
bit 11-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
U-0
U-0
U-0
R/P-1
R/P-1
CPD
CP
BG0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
DS40039C-page 54
PIC16F630/676
9.2
Oscillator Configurations
9.2.1
LP
Low Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Oscillator (2 modes)
EC
External Clock In
Note:
Additional information on oscillator configurations is available in the PICmicroTM MidRange Reference Manual, (DS33023).
9.2.2
FIGURE 9-1:
XTAL
RF(3)
PIC16F630/676
C2(1)
1:
2:
3:
TABLE 9-1:
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
TABLE 9-2:
OSC2(C2)
LP
32 kHz
68 - 100 pF
68 - 100 pF
SLEEP
XT
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
PIC16F630/676
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
OSC2(1)
Open
OSC2
RS(2)
OSC1
Freq
To Internal
Logic
C1
Clock from
External System
Mode
OSC1
(1)
Note
OSCILLATOR TYPES
FIGURE 9-2:
DS40039C-page 55
PIC16F630/676
9.2.3
9.2.5
EXTERNAL CLOCK IN
9.2.4
RC OSCILLATOR
FIGURE 9-3:
RC OSCILLATOR MODE
VDD
REXT
9.2.5.1
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part as
specified in the PIC16F630/676 Programming specification. Microchip Development Tools maintain all calibration bits to
factory settings.
EXAMPLE 9-1:
bsf
call
movwf
bcf
CALIBRATING THE
INTERNAL OSCILLATOR
STATUS, RP0
3FFh
OSCCAL
STATUS, RP0
;Bank 1
;Get the cal value
;Calibrate
;Bank 0
PIC16F630/676
RA5/OSC1/
CLKIN
CEXT
VSS
FOSC/4
RA4/OSC2/CLKOUT
DS40039C-page 56
Internal
Clock
9.2.6
CLKOUT
PIC16F630/676
9.3
RESET
Power-on Reset
MCLR Reset
WDT Reset
WDT Reset during SLEEP
Brown-out Detect (BOD)
FIGURE 9-4:
MCLR/
VPP pin
WDT
WDT
Module
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
BODEN
OST/PWRT
OST
Chip_Reset
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note
1:
DS40039C-page 57
PIC16F630/676
9.3.1
MCLR
FIGURE 9-5:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F630/676
R1
1 k (or greater)
MCLR
C1
0.1 f
(optional, not critical)
9.3.2
9.3.3
9.3.4
The POR circuit does not produce an internal RESET when VDD declines.
DS40039C-page 58
PIC16F630/676
9.3.5
FIGURE 9-6:
Note:
BROWN-OUT SITUATIONS
VDD
Internal
RESET
VBOD
72 ms(1)
VDD
Internal
RESET
VBOD
<72 ms
72 ms(1)
VDD
Internal
RESET
VBOD
72 ms(1)
9.3.6
TIME-OUT SEQUENCE
9.3.7
register,
PCON
Bit0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0, indicating
that a brown-out has occurred. The BOD STATUS bit is
a dont care and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a 0 on Power-on
Reset and unaffected otherwise. The user must write a
1 to this bit following a Power-on Reset. On a
subsequent RESET, if POR is 0, it will indicate that a
Power-on Reset must have occurred (i.e., VDD may
have gone too low).
DS40039C-page 59
PIC16F630/676
TABLE 9-3:
Brown-out Detect
Oscillator Configuration
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT +
1024TOSC
1024TOSC
TPWRT +
1024TOSC
1024TOSC
1024TOSC
TPWRT
TPWRT
TABLE 9-4:
POR
BOD
TO
PD
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
TABLE 9-5:
Address
Value on all
other
RESETS(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
STATUS
IRP
RP1
RPO
TO
PD
DC
8Eh
PCON
POR
BOD
TABLE 9-6:
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
000h
000u uuuu
---- --uu
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 uuuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --10
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Detect
Interrupt Wake-up from SLEEP
PC +
1(1)
DS40039C-page 60
PIC16F630/676
TABLE 9-7:
Register
INDF
00h/80h
TMR0
PCL
Power-on
Reset
xxxx xxxx
MCLR Reset
WDT Reset
Brown-out Detect(1)
uuuu uuuu
uuuu uuuu
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
02h/82h
0000 0000
0000 0000
PC + 1(3)
(4)
STATUS
03h/83h
0001 1xxx
000q quuu
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
--xx xxxx
--uu uuuu
--uu uuuu
PORTC
07h
--xx xxxx
--uu uuuu
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 000u
uuuu uuqq(2)
PIR1
0Ch
00-- 0--0
00-- 0--0
qq-- q--q(2,5)
T1CON
10h
-000 0000
-uuu uuuu
-uuu uuuu
CMCON
19h
-0-0 0000
-0-0 0000
-u-u uuuu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
00-0 0000
00-0 0000
uu-u uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
--11 1111
--11 1111
--uu uuuu
TRISC
87h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
00-- 0--0
00-- 0--0
uu-- u--u
(1,6)
PCON
8Eh
---- --0x
---- --uu
---- --uu
OSCCAL
90h
1000 00--
1000 00--
uuuu uu--
ANSEL
91h
1111 1111
1111 1111
uuuu uuuu
WPUA
95h
--11 -111
--11 -111
uuuu uuuu
IOCA
96h
--00 0000
--00 0000
--uu uuuu
VRCON
99h
0-0- 0000
0-0- 0000
u-u- uuuu
EEDATA
9Ah
0000 0000
0000 0000
uuuu uuuu
EEADR
9Bh
-000 0000
-000 0000
-uuu uuuu
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
---- ----
---- ----
---- ----
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
9Fh
-000 ----
-000 ----
-uuu ----
Legend:
Note 1:
2:
3:
DS40039C-page 61
PIC16F630/676
FIGURE 9-7:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-8:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 9-9:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
DS40039C-page 62
PIC16F630/676
9.4
Interrupts
DS40039C-page 63
PIC16F630/676
FIGURE 9-10:
INTERRUPT LOGIC
IOCA-RA0
IOCA0
IOCA-RA1
IOCA1
IOCA-RA2
IOCA2
IOCA-RA3
IOCA3
IOCA-RA4
IOCA4
IOCA-RA5
IOCA5
TMR1IF
TMR1IE
CMIF
CMIE
ADIF
ADIE
T0IF
T0IE
INTF
INTE
RAIF
RAIE
Interrupt to CPU
PEIE
(1)
GIE
EEIF
EEIE
Note 1: PIC16F676 only.
DS40039C-page 64
PIC16F630/676
9.4.1
RA2/INT INTERRUPT
9.4.2
Note:
TMR0 INTERRUPT
9.4.3
PORTA INTERRUPT
9.4.4
COMPARATOR INTERRUPT
9.4.5
FIGURE 9-11:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency 2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst (PC)
Instruction
Executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
PC+1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
DS40039C-page 65
PIC16F630/676
TABLE 9-8:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
8Ch
EEIF
EEIE
ADIF
ADIE
CMIF
CMIE
PIR1
PIE1
Value on all
other
RESETS
Bit 0
Value on
POR, BOD
RAIF
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
9.5
EXAMPLE 9-2:
MOVWF
W_TEMP
SWAPF
BCF
STATUS,W
STATUS,RP0
MOVWF STATUS_TEMP
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS
;move W into STATUS register
SWAPF W_TEMP,F
;swap W_TEMP
SWAPF W_TEMP,W
;swap W_TEMP into W
DS40039C-page 66
9.6
9.6.1
WDT PERIOD
9.6.2
WDT PROGRAMMING
CONSIDERATIONS
PIC16F630/676
FIGURE 9-12:
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0CS
T0SE
TMR0
0
8-bit
Prescaler
PSA
1
8
PSA
PS0 - PS2
WDT
Time-out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
TABLE 9-9:
Address
Bit 7
Bit 6
81h
2007h
Config. bits
CP
Value on all
other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
T0CS
T0SE
PSA
PS2
PS1
PS0
F0SC2
F0SC1
F0SC0
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
DS40039C-page 67
PIC16F630/676
9.7
a peripheral interrupt.
9.7.1
FIGURE 9-13:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 3)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
DS40039C-page 68
PIC16F630/676
9.8
Code Protection
FIGURE 9-14:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
9.9
To Normal
Connections
PIC16F630/676
+5V
VDD
0V
VSS
VPP
RA3/MCLR/VPP
CLK
RA1
Data I/O
RA0
ID Locations
9.10
External
Connector
Signals
VDD
To Normal
Connections
9.11
In-Circuit Debugger
TABLE 9-10:
DEBUGGER RESOURCES
I/O pins
ICDCLK, ICDDATA
Stack
1 level
Program Memory
DS40039C-page 69
PIC16F630/676
NOTES:
DS40039C-page 70
PIC16F630/676
10.0
Byte-oriented operations
Bit-oriented operations
TABLE 10-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
10.1
READ-MODIFY-WRITE
OPERATIONS
FIGURE 10-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
OPCODE
0
k (literal)
11
OPCODE
10
0
k (literal)
DS40039C-page 71
PIC16F630/676
TABLE 10-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
k
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU
Family Reference Manual (DS33023).
DS40039C-page 72
PIC16F630/676
10.2
Instruction Descriptions
ADDLW
BCF
Bit Clear f
Syntax:
[label] ADDLW
Syntax:
[label] BCF
Operands:
0 k 255
Operands:
Operation:
(W) + k (W)
0 f 127
0b7
Status Affected:
C, DC, Z
Operation:
0 (f<b>)
Description:
Status Affected:
None
Description:
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[label] ADDWF
Operands:
f,b
Syntax:
[label] BSF
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
1 (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Description:
ANDLW
BTFSS
Syntax:
[label] ANDLW
Syntax:
Operands:
0 k 255
Operands:
0 f 127
0b<7
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
BTFSC
Syntax:
f,d
Operation:
Status Affected:
Description:
f,b
ANDWF
AND W with f
Syntax:
[label] ANDWF
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Operation:
skip if (f<b>) = 0
Status Affected:
Status Affected:
None
Description:
Description:
f,d
DS40039C-page 73
PIC16F630/676
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRF
Clear f
COMF
Complement f
Syntax:
[label] CLRF
Syntax:
[ label ] COMF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Status Affected:
Description:
Description:
CLRW
Clear W
DECF
Decrement f
f,d
Syntax:
[ label ] CLRW
Syntax:
Operands:
None
Operands:
Operation:
00h (W)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
DS40039C-page 74
PIC16F630/676
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
GOTO k
INCF f,d
INCFSZ f,d
IORWF
f,d
DS40039C-page 75
PIC16F630/676
MOVF
Move f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
MOVF f,d
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
NOP
Operation:
(f) (destination)
Status Affected:
None
Status Affected:
Description:
No operation.
Description:
MOVLW
Move Literal to W
RETFIE
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
Status Affected:
None
TOS PC,
1 GIE
Description:
Status Affected:
None
MOVWF
Move W to f
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
Operands:
0 k 255
Operation:
(W) (f)
Operation:
Status Affected:
None
k (W);
TOS PC
Description:
Status Affected:
None
Description:
DS40039C-page 76
MOVLW k
MOVWF
RETFIE
RETLW k
PIC16F630/676
RLF
SLEEP
Syntax:
[ label ] RLF
Syntax:
Operands:
0 f 127
d [0,1]
f,d
Operation:
Status Affected:
Description:
[ label ] SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
Register f
RETURN
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 k 255
Operation:
TOS PC
Operation:
k - (W) (W)
Status Affected:
None
Description:
Description:
RRF
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
C
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
Status
Affected:
C, DC, Z
Description:
Description:
RETURN
RRF f,d
Register f
DS40039C-page 77
PIC16F630/676
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
Syntax:
[label]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
XORLW
f,d
Syntax:
[label]
Operands:
0 k 255
Operation:
Status Affected:
Description:
DS40039C-page 78
XORWF
XORLW k
PIC16F630/676
11.0
DEVELOPMENT SUPPORT
11.1
11.2
MPASM Assembler
DS40039C-page 79
PIC16F630/676
11.3
11.4
11.5
DS40039C-page 80
11.6
11.7
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
11.8
PIC16F630/676
11.9
DS40039C-page 81
PIC16F630/676
11.14 PICDEM 1 PICmicro
Demonstration Board
DS40039C-page 82
PIC16F630/676
11.19 PICDEM 18R PIC18C601/801
Demonstration Board
DS40039C-page 83
PIC16F630/676
NOTES:
DS40039C-page 84
PIC16F630/676
12.0
ELECTRICAL SPECIFICATIONS
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling
this pin directly to VSS.
DS40039C-page 85
PIC16F630/676
FIGURE 12-1:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS40039C-page 86
PIC16F630/676
FIGURE 12-3:
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.2
2.0
0
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS40039C-page 87
PIC16F630/676
12.1
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Supply Voltage
D001
D001A
D001B
D001C
D001D
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
1.5*
VDR
D003
VPOR
VSS
D004
SVDD
0.05*
2.1
VBOD
2.0
2.2
2.5
3.0
4.5
D002
D005
Conditions
DS40039C-page 88
PIC16F630/676
12.2
Param
No.
D010
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
D011
D012
D013
D014
D015
D016
D017
16
2.0
18
28
3.0
35
54
5.0
110
150
2.0
190
280
3.0
330
450
5.0
220
280
2.0
370
650
3.0
0.6
1.4
mA
5.0
70
110
2.0
140
250
3.0
260
390
5.0
180
250
2.0
320
470
3.0
580
850
5.0
340
450
2.0
500
780
3.0
0.8
1.1
mA
5.0
180
250
2.0
320
450
3.0
580
800
5.0
2.1
2.95
mA
4.5
2.4
3.0
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
DS40039C-page 89
PIC16F630/676
12.3
Param
No.
D020
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
D021
0.99
700
nA
2.0
1.2
770
nA
3.0
2.9
995
nA
5.0
0.3
1.5
2.0
1.8
3.5
3.0
8.4
17
5.0
D022
58
70
3.0
109
130
5.0
D023
3.3
6.5
2.0
D024
D025
D026
6.1
8.5
3.0
11.5
16
5.0
58
70
2.0
85
100
3.0
138
160
5.0
4.0
6.5
2.0
4.6
7.0
3.0
6.0
10.5
5.0
1.2
755
nA
3.0
0.0022
1.0
5.0
Note
WDT, BOD, Comparators, VREF,
and T1OSC disabled
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
DS40039C-page 90
PIC16F630/676
12.4
Param
No.
Device Characteristics
D010E
Min
Typ
Max
Units
VDD
D011E
D012E
D013E
D014E
D015E
D016E
D017E
16
2.0
18
28
3.0
35
54
5.0
110
150
2.0
190
280
3.0
330
450
5.0
220
280
2.0
370
650
3.0
0.6
1.4
mA
5.0
70
110
2.0
140
250
3.0
260
390
5.0
180
250
2.0
320
470
3.0
580
850
5.0
340
450
2.0
500
780
3.0
0.8
1.1
mA
5.0
180
250
2.0
320
450
3.0
580
800
5.0
2.1
2.95
mA
4.5
2.4
3.0
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
DS40039C-page 91
PIC16F630/676
12.5
Param
No.
D020E
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
D021E
D022E
D023E
D024E
D025E
D026E
0.00099
3.5
2.0
0.0012
4.0
3.0
0.0029
8.0
5.0
0.3
6.0
2.0
1.8
9.0
3.0
8.4
20
5.0
58
70
3.0
109
130
5.0
3.3
10
2.0
6.1
13
3.0
11.5
24
5.0
58
70
2.0
85
100
3.0
138
165
5.0
4.0
10
2.0
4.6
12
3.0
6.0
20
5.0
0.0012
6.0
3.0
0.0022
8.5
5.0
Note
WDT, BOD, Comparators, VREF,
and T1OSC disabled
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
DS40039C-page 92
PIC16F630/676
12.6
DC CHARACTERISTICS
Param
Sym
No.
VIL
D030
D030A
D031
D032
D033
D033A
VIH
D040
D040A
D041
D042
D043
D043A
D043B
D070 IPUR
IIL
D060
D060A
D060B
D061
D063
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
Input High Voltage
I/O ports
with TTL buffer
VOL
D090
D092
VOH
Min
Typ
Max
Units
VSS
VSS
VSS
VSS
VSS
VSS
0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3
0.3 VDD
V
V
V
V
V
V
V
V
250
VDD
VDD
VDD
VDD
VDD
VDD
VDD
400*
V
V
V
V
A
0.1
0.1
0.1
0.1
0.1
1
1
5
5
A
A
A
A
0.6
0.6
V
V
VDD - 0.7
VDD - 0.7
V
V
Conditions
2.0
(0.25 VDD+0.8)
with Schmitt Trigger buffer
0.8 VDD
0.8 VDD
MCLR
OSC1 (XT and LP modes)
1.6
OSC1 (HS mode)
0.7 VDD
OSC1 (RC mode)
0.9 VDD
PORTA Weak Pull-up
50*
Current
Analog inputs
VREF
MCLR(2)
OSC1
D080
D083
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS40039C-page 93
PIC16F630/676
12.7
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Capacitive Loading Specs
on Output Pins
OSC2 pin
Min
Typ
Max
Units
Conditions
15*
pF
50*
pF
100K
10K
VMIN
1M
100K
5.5
D100
COSC2
D101
CIO
D120
D120A
D121
ED
ED
VDRW
D122
D123
40
D124
TREF
1M
10M
D130
D130A
D131
EP
ED
VPR
10K
1K
VMIN
100K
10K
5.5
D132
D133
D134
4.5
40
5.5
2.5
DS40039C-page 94
PIC16F630/676
12.8
FIGURE 12-4:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464
CL = 50 pF
15 pF
DS40039C-page 95
PIC16F630/676
12.9
FIGURE 12-5:
Q1
Q2
Q3
Q4
Q1
OSC1
1
2
CLKOUT
TABLE 12-1:
Param
No.
Sym
FOSC
Min
Typ
Max
Units
DC
DC
DC
DC
5
DC
0.1
1
37
4
20
20
37
4
4
20
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
LP Osc mode
XT mode
HS mode
EC mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
27
50
50
250
27
250
250
50
200
10,000
1,000
s
ns
ns
ns
s
ns
ns
ns
ns
LP Osc mode
HS Osc mode
EC Osc mode
XT Osc mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
Oscillator Frequency(1)
TOSC
Oscillator Period(1)
TCY
250
Conditions
200
TCY
DC
ns TCY = 4/FOSC
3
TosL,
2*
50*
ns LP oscillator
TosF
External CLKIN Fall
25*
ns XT oscillator
15*
ns HS oscillator
* These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at min values with an external
clock applied to OSC1 pin. When an external clock input is used, the max cycle time limit is DC (no clock)
for all devices.
DS40039C-page 96
PIC16F630/676
TABLE 12-2:
Param
No.
F10
F14
Sym
Freq
Min
Tolerance
Typ
Max
Units
1
2
3.96
3.92
4.00
4.00
4.04
4.08
3.80
4.00
4.20
6
4
3
8
6
5
Conditions
DS40039C-page 97
PIC16F630/676
FIGURE 12-6:
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
12
19
14
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 12-3:
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
10
75
200
ns
(Note 1)
11
75
200
ns
(Note 1)
12
TckR
35
100
ns
(Note 1)
13
TckF
35
100
ns
(Note 1)
14
TckL2ioV
20
ns
(Note 1)
15
TioV2ckH
TOSC + 200 ns
ns
(Note 1)
16
TckH2ioI
ns
(Note 1)
17
TosH2ioV
50
150 *
ns
300
ns
100
ns
18
TosH2ioI
19
ns
20
TioR
10
40
ns
21
TioF
10
40
ns
22
Tinp
25
ns
23
Trbp
TCY
ns
DS40039C-page 98
PIC16F630/676
FIGURE 12-7:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
34
31
34
I/O Pins
FIGURE 12-8:
35
72 ms time-out(1)
DS40039C-page 99
PIC16F630/676
TABLE 12-4:
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
2
11
18
24
s
ms
31
TWDT
10
10
17
17
25
30
ms
ms
32
TOST
1024TOSC
33*
TPWRT
28*
TBD
72
TBD
132*
TBD
ms
ms
34
TIOZ
2.0
BVDD
2.025
2.175
Brown-out Hysteresis
TBD
100*
35
TBOD
DS40039C-page 100
PIC16F630/676
FIGURE 12-9:
T0CKI
41
40
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 12-5:
Param
No.
40*
Sym
Tt0H
Characteristic
T0CKI High Pulse Width
No Prescaler
With Prescaler
41*
Tt0L
No Prescaler
With Prescaler
42*
Tt0P
T0CKI Period
45*
Tt1H
46*
Tt1L
Asynchronous
Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
47*
Tt1P
T1CKI Input
Period
Synchronous
Asynchronous
Ft1
48
Min
Typ
Max
Units
0.5 TCY + 20
ns
ns
ns
ns
10
0.5 TCY + 20
10
Greater of:
20 or TCY + 40
N
0.5 TCY + 20
ns
ns
15
ns
30
0.5 TCY + 20
ns
ns
15
ns
30
ns
Greater of:
30 or TCY + 40
N
ns
60
ns
DC
200*
kHz
2 TOSC*
7 TOSC*
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
DS40039C-page 101
PIC16F630/676
TABLE 12-6:
COMPARATOR SPECIFICATIONS
Comparator Specifications
Sym
Characteristics
Typ
Max
Units
VOS
5.0
10
mV
VCM
VDD - 1.5
CMRR
+55*
db
TRT
Response Time(1)
150
400*
ns
10*
Comments
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD - 1.5V.
TABLE 12-7:
Characteristics
Typ
Max
Units
Comments
Resolution
VDD/24*
VDD/32
LSb
LSb
Absolute Accuracy
1/2*
1/2*
LSb
LSb
2k*
Settling Time(1)
10*
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS40039C-page 102
PIC16F630/676
TABLE 12-8:
Param
No.
Sym
Min
Typ
Max
Units
bit
Conditions
A01
NR
Resolution
10 bits
A02
EABS
Total Absolute
Error*
A03
EIL
Integral Error
A04
EDL
Differential Error
A05
EFS
2.2*
5.5*
A06
EOFF
Offset Error
A07
EGN
Gain Error
(3)
VDD + 0.3
VDD
VSS
VREF
Recommended
Impedance of
Analog Voltage
Source
10
VREF Input
Current(2)
10
1000
10
A10
Monotonicity
A20
A20A
VREF
Reference Voltage
2.0
2.5
A21
VREF
Reference V High
(VDD or VREF)
VSS
A25
VAIN
Analog Input
Voltage
A30
ZAIN
A50
IREF
guaranteed
DS40039C-page 103
PIC16F630/676
FIGURE 12-10:
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
9
A/D DATA
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 12-9:
Param
No.
130
130
Sym
TAD
TAD
Characteristic
A/D Clock Period
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
Min
Typ
Max
Units
Conditions
1.6
3.0*
3.0*
6.0
9.0*
2.0*
4.0
6.0*
At VDD = 5.0V
11
TAD
(Note 2)
11.5
5*
TOSC/2
DS40039C-page 104
PIC16F630/676
FIGURE 12-11:
BSF ADCON0, GO
134
(TOSC/2 + TCY)(1)
1 TCY
131
Q4
130
A/D CLK
9
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
1 TCY
GO
DONE
SAMPLE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Sym
Characteristic
Min
Typ
Max
Units
1.6
VREF 3.0V
3.0*
3.0*
6.0
9.0*
2.0*
4.0
6.0*
At VDD = 5.0V
11
TAD
(Note 2)
11.5
5*
TOSC/2 + TCY
130
TAD
130
TAD
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
TGO
134
Q4 to A/D Clock
Start
Conditions
DS40039C-page 105
PIC16F630/676
NOTES:
DS40039C-page 106
PIC16F630/676
13.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 13-1:
6.0E-09
IPD (A)
5.0E-09
4.0E-09
-40
3.0E-09
0
25
2.0E-09
1.0E-09
0.0E+00
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 13-2:
3.5E-07
3.0E-07
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039C-page 107
PIC16F630/676
FIGURE 13-3:
IPD (A)
2.5E-06
125
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-4:
IPD (A)
8.0E-08
7.0E-08
6.0E-08
-40
5.0E-08
4.0E-08
25
3.0E-08
2.0E-08
1.0E-08
0.0E+00
2
2.5
3.5
4.5
5.5
VDD (V)
DS40039C-page 108
PIC16F630/676
FIGURE 13-5:
IPD (A)
7.0E-07
6.0E-07
5.0E-07
4.0E-07
85
3.0E-07
2.0E-07
1.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-6:
IPD (A)
7.0E-06
6.0E-06
5.0E-06
125
4.0E-06
3.0E-06
2.0E-06
1.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039C-page 109
PIC16F630/676
FIGURE 13-7:
TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40C TO +125C)
IPD (uA)
110
-40
100
90
25
80
85
125
70
60
50
3
3.5
4.5
5.5
VDD (V)
FIGURE 13-8:
TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40C TO +125C)
IPD (A)
1.2E-05
1.0E-05
25
8.0E-06
85
6.0E-06
125
4.0E-06
2.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039C-page 110
PIC16F630/676
FIGURE 13-9:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40C TO +25C)
IPD (A)
5.0E-09
4.5E-09
4.0E-09
3.5E-09
3.0E-09
2.5E-09
2.0E-09
1.5E-09
1.0E-09
5.0E-10
0.0E+00
-40
0
25
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 13-10:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85C)
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2
2.5
3.5
4.5
5.5
VDD (V)
DS40039C-page 111
PIC16F630/676
FIGURE 13-11:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125C)
IPD (A)
3.0E-06
2.5E-06
2.0E-06
125
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2
2.5
3.5
4.5
5.5
VDD (V)
FIGURE 13-12:
TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40C TO +125C),
32 KHZ, C1 AND C2=50 pF)
Typical T1 IPD
1.20E-05
IPD (A)
1.00E-05
-40
8.00E-06
0
25
6.00E-06
85
4.00E-06
125
2.00E-06
0.00E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039C-page 112
PIC16F630/676
FIGURE 13-13:
TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40C TO +125C)
IPD (uA)
140
-40
120
100
25
85
80
125
60
40
2
2.5
3.5
4.5
5.5
VDD (V)
TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40C TO +125C)
FIGURE 13-14:
IPD (uA)
14
12
-40
10
25
85
125
2
0
2
2.5
3.5
4.5
5.5
V DD (V)
DS40039C-page 113
PIC16F630/676
FIGURE 13-15:
MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1F AND
0.01F DECOUPLING (VDD = 3.5V)
Internal Oscillator
Frequency vs Temperature
4.20E+06
Frequency (Hz)
4.15E+06
4.10E+06
4.05E+06
-3sigma
4.00E+06
average
3.95E+06
+3sigma
3.90E+06
3.85E+06
3.80E+06
-40C
0C
25C
85C
125C
Temperature (C)
FIGURE 13-16:
MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1F AND 0.01F
DECOUPLING (+25C)
Internal Oscillator
Frequency vs VDD
Frequency (Hz)
4.20E+06
4.15E+06
4.10E+06
4.05E+06
4.00E+06
-3sigma
3.95E+06
3.90E+06
+3sigma
average
3.85E+06
3.80E+06
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
VDD (V)
DS40039C-page 114
PIC16F630/676
FIGURE 13-17:
WDT Time-out
Time (mS)
50
45
40
35
-40
30
25
20
15
10
5
85
25
125
0
2
2.5
3.5
4.5
5.5
V DD (V)
DS40039C-page 115
PIC16F630/676
NOTES:
DS40039C-page 116
PIC16F630/676
14.0
PACKAGING INFORMATION
14.1
16F630-I
0215/017
Example
14-Lead SOIC
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP
XXXXXXXX
16F630-E
0215/017
Example
16F630
YYWW
0215
NNN
017
Legend:
Note:
Example
XX...X
Y
YY
WW
NNN
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS40039C-page 117
PIC16F630/676
14.2
Package Details
E1
2
n
E
A2
c
A1
B1
eB
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
.115
.145
A2
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
.045
.058
.070
B1
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
.310
.370
.430
DS40039C-page 118
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
PIC16F630/676
14-Lead Plastic Small Outline (SL) Narrow, 150 mil (SOIC)
E
E1
2
B
h
45
c
A2
A1
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
h
L
c
B
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010 (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
DS40039C-page 119
PIC16F630/676
14-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
A
c
A1
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
Significant Characteristic
A
A2
A1
E
E1
D
L
c
B
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005 (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS40039C-page 120
PIC16F630/676
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
DEVICE
DIFFERENCES
Revision B
Added characterization graphs.
Updated specifications.
TABLE B-1:
DEVICE DIFFERENCES
Feature
PIC16F630
PIC16F676
A/D
No
Yes
DS40039C-page 121
PIC16F630/676
APPENDIX C:
DEVICE MIGRATIONS
APPENDIX D:
MIGRATING FROM
OTHER PICmicro
DEVICES
D.1
PIC12C67X to PIC12F6XX
TABLE 1:
FEATURE COMPARISON
Feature
PIC16F6XX
10 MHz
20 MHz
2048 bytes
1024 bytes
A/D Resolution
8-bit
10-bit
Data EEPROM
16 bytes
64 bytes
Oscillator Modes
Brown-out Detect
Internal Pull-ups
RA0/1/3
RA0/1/2/4/5
Interrupt-on-change
RA0/1/3
RA0/1/2/3/4/5
Comparator
Note:
DS40039C-page 122
PIC12C67X
PIC16F630/676
INDEX
A
A/D ...................................................................................... 43
Acquisition Requirements ........................................... 47
Block Diagram............................................................. 43
Calculating Acquisition Time....................................... 47
Configuration and Operation....................................... 43
Effects of a RESET ..................................................... 48
Internal Sampling Switch (Rss) Impedance ................ 47
Operation During SLEEP ............................................ 48
PIC16F675 Converter Characteristics ...................... 103
Source Impedance...................................................... 47
Summary of Registers ................................................ 48
Absolute Maximum Ratings ................................................ 85
AC Characteristics
Industrial and Extended .............................................. 96
Analog Input Connection Considerations............................ 40
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler..................................................... 79
B
Block Diagram
TMR0/WDT Prescaler................................................. 29
Block Diagrams
Analog Input Mode...................................................... 40
Analog Input Model ..................................................... 47
Comparator Output ..................................................... 40
Comparator Voltage Reference .................................. 41
On-Chip Reset Circuit ................................................. 57
RA0 and RA1 Pins ...................................................... 22
RA2 ............................................................................. 23
RA3 ............................................................................. 23
RA4 ............................................................................. 24
RA5 ............................................................................. 24
RC Oscillator Mode..................................................... 56
RC0/RC1/RC2/RC3 Pins ............................................ 26
RC4 AND RC5 Pins .................................................... 26
Timer1......................................................................... 32
Watchdog Timer.......................................................... 67
Brown-out
Associated Registers .................................................. 60
Brown-out Detect (BOD) ..................................................... 59
Brown-out Detect Timing and Characteristics..................... 99
C
C Compilers
MPLAB C17 ................................................................ 80
MPLAB C18 ................................................................ 80
MPLAB C30 ................................................................ 80
Calibrated Internal RC Frequencies.................................... 97
CLKOUT ............................................................................. 56
Code Examples
Changing Prescaler .................................................... 31
Data EEPROM Read .................................................. 51
Data EEPROM Write .................................................. 51
Initializing PORTA....................................................... 19
Initializing PORTC....................................................... 26
Saving STATUS and W Registers in RAM ................. 66
Write Verify ................................................................. 51
Code Protection .................................................................. 69
Comparator ......................................................................... 37
Associated Registers .................................................. 42
Configuration............................................................... 39
Effects of a RESET ..................................................... 41
I/O Operating Modes................................................... 39
Interrupts..................................................................... 42
Operation.................................................................... 38
Operation During SLEEP............................................ 41
Output......................................................................... 40
Reference ................................................................... 41
Response Time .......................................................... 41
Comparator Specifications................................................ 102
Comparator Voltage Reference Specifications................. 102
Configuration Bits ............................................................... 54
Configuring the Voltage Reference..................................... 41
Crystal Operation................................................................ 55
D
Data EEPROM Memory
Associated Registers/Bits........................................... 52
Code Protection.......................................................... 52
EEADR Register......................................................... 49
EECON1 Register ...................................................... 49
EECON2 Register ...................................................... 49
EEDATA Register....................................................... 49
Data Memory Organization................................................... 7
DC Characteristics
Extended and Industrial.............................................. 93
Industrial ..................................................................... 88
Debugger ............................................................................ 69
Demonstration Boards
PICDEM 1................................................................... 82
PICDEM 17................................................................. 82
PICDEM 18R PIC18C601/801 ................................... 83
PICDEM 2 Plus........................................................... 82
PICDEM 3 PIC16C92X............................................... 82
PICDEM LIN PIC16C43X ........................................... 83
PICDEM USB PIC16C7X5 ......................................... 83
PICDEM.net Internet/Ethernet.................................... 82
Development Support ......................................................... 79
Device Differences............................................................ 121
Device Migrations ............................................................. 122
Device Overview................................................................... 5
E
EEPROM Data Memory
Reading ...................................................................... 51
Spurious Write ............................................................ 51
Write Verify ................................................................. 51
Writing ........................................................................ 51
Electrical Specifications ...................................................... 85
Evaluation and Programming Tools.................................... 83
F
Firmware Instructions ......................................................... 71
G
General Purpose Register File ............................................. 7
I
ID Locations........................................................................ 69
In-Circuit Serial Programming............................................. 69
Indirect Addressing, INDF and FSR Registers ................... 18
Instruction Format............................................................... 71
Instruction Set..................................................................... 71
ADDLW....................................................................... 73
ADDWF ...................................................................... 73
ANDLW....................................................................... 73
ANDWF ...................................................................... 73
BCF ............................................................................ 73
BSF............................................................................. 73
BTFSC........................................................................ 73
BTFSS ........................................................................ 73
CALL........................................................................... 74
CLRF .......................................................................... 74
DS40039C-page 123
PIC16F630/676
CLRW ......................................................................... 74
CLRWDT..................................................................... 74
COMF ......................................................................... 74
DECF .......................................................................... 74
DECFSZ...................................................................... 75
GOTO ......................................................................... 75
INCF............................................................................ 75
INCFSZ ....................................................................... 75
IORLW ........................................................................ 75
IORWF ........................................................................ 75
MOVF.......................................................................... 76
MOVLW ...................................................................... 76
MOVWF ...................................................................... 76
NOP ............................................................................ 76
RETFIE ....................................................................... 76
RETLW ....................................................................... 76
RETURN ..................................................................... 77
RLF ............................................................................. 77
RRF............................................................................. 77
SLEEP ........................................................................ 77
SUBLW ....................................................................... 77
SUBWF ....................................................................... 77
SWAPF ....................................................................... 78
XORLW ....................................................................... 78
XORWF....................................................................... 78
Summary Table........................................................... 72
Internal 4 MHz Oscillator..................................................... 56
Internal Sampling Switch (Rss) Impedance ........................ 47
Interrupts ............................................................................. 63
A/D Converter ............................................................. 65
Comparator ................................................................. 65
Context Saving............................................................ 66
PORTA........................................................................ 65
RA2/INT ...................................................................... 65
Summary of Registers ................................................ 66
TMR0 .......................................................................... 65
M
MCLR .................................................................................. 58
Memory Organization
Data EEPROM Memory .............................................. 49
Migrating from other PICmicro Devices ............................ 122
MPLAB ASM30 Assembler, Linker, Librarian ..................... 80
MPLAB ICD 2 In-Circuit Debugger...................................... 81
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator .............................................................. 81
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator .............................................................. 81
MPLAB Integrated Development Environment Software .... 79
MPLINK Object Linker/MPLIB Object Librarian .................. 80
O
OPCODE Field Descriptions ............................................... 71
Oscillator Configurations ..................................................... 55
Oscillator Start-up Timer (OST) .......................................... 58
P
Packaging ......................................................................... 117
Details ....................................................................... 118
Marking ..................................................................... 117
PCL and PCLATH ............................................................... 17
Computed GOTO ........................................................ 17
Stack ........................................................................... 17
PICkit 1 FLASH Starter Kit .................................................. 83
PICSTART Plus Development Programmer ....................... 81
Pinout Descriptions
PIC16F630.................................................................... 6
PIC16F676.................................................................... 6
DS40039C-page 124
PORTA
Additional Pin Functions ............................................. 19
Interrupt-on-Change ........................................... 20
Weak Pull-up ...................................................... 19
Associated Registers .................................................. 25
Pin Descriptions and Diagrams .................................. 22
PORTA and TRISIO Registers ........................................... 19
PORTC ............................................................................... 26
Associated Registers .................................................. 27
Power Control/Status Register (PCON).............................. 59
Power-Down Mode (SLEEP) .............................................. 68
Power-on Reset (POR)....................................................... 58
Power-up Timer (PWRT) .................................................... 58
Prescaler............................................................................. 31
Switching Prescaler Assignment ................................ 31
PRO MATE II Universal Device Programmer ..................... 81
Program Memory Organization............................................. 7
Programming, Device Instructions...................................... 71
R
RC Oscillator....................................................................... 56
READ-MODIFY-WRITE OPERATIONS ............................. 71
Registers
ADCON0 (A/D Control)............................................... 45
ADCON1..................................................................... 45
CMCON (Comparator Control) ................................... 37
CONFIG (Configuration Word) ................................... 54
EEADR (EEPROM Address) ...................................... 49
EECON1 (EEPROM Control) ..................................... 50
EEDAT (EEPROM Data) ............................................ 49
INTCON (Interrupt Control)......................................... 13
IOCA (Interrupt-on-Change PORTA).......................... 21
Maps
PIC16F630 ........................................................... 8
PIC16F676 ........................................................... 8
OPTION_REG (Option) ........................................ 12, 30
OSCCAL (Oscillator Calibration) ................................ 16
PCON (Power Control) ............................................... 16
PIE1 (Peripheral Interrupt Enable 1)........................... 14
PIR1 (Peripheral Interrupt 1)....................................... 15
PORTC ....................................................................... 27
STATUS ..................................................................... 11
T1CON (Timer1 Control) ............................................ 34
TRISC ......................................................................... 27
VRCON (Voltage Reference Control) ......................... 42
WPUA (Weak Pull-up PORTA)................................... 20
RESET................................................................................ 57
Revision History................................................................ 121
S
Software Simulator (MPLAB SIM) ...................................... 80
Software Simulator (MPLAB SIM30) .................................. 80
Special Features of the CPU .............................................. 53
Special Function Registers ................................................... 8
T
Time-out Sequence ............................................................ 59
Timer0................................................................................. 29
Associated Registers .................................................. 31
External Clock............................................................. 30
Interrupt ...................................................................... 29
Operation .................................................................... 29
T0CKI ......................................................................... 30
Timer1
Associated Registers .................................................. 35
Asynchronous Counter Mode ..................................... 35
Reading and Writing ........................................... 35
Interrupt ...................................................................... 33
PIC16F630/676
Modes of Operations................................................... 33
Operation During SLEEP ............................................ 35
Oscillator ..................................................................... 35
Prescaler..................................................................... 33
Timer1 Module with Gate Control ....................................... 32
Timing Diagrams
CLKOUT and I/O......................................................... 98
External Clock............................................................. 96
INT Pin Interrupt.......................................................... 65
PIC16F675 A/D Conversion (Normal Mode)............. 104
PIC16F675 A/D Conversion Timing
(SLEEP Mode) .......................................................... 105
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer ......................................... 99
Time-out Sequence on Power-up (MCLR not Tied to
VDD)
Case 1 ................................................................ 62
Case 2 ................................................................ 62
Time-out Sequence on Power-up
(MCLR Tied to VDD).................................................... 62
Timer0 and Timer1 External Clock ........................... 101
Timer1 Incrementing Edge.......................................... 33
Timing Parameter Symbology............................................. 95
TRISIO Registers ................................................................ 19
V
Voltage Reference Accuracy/Error ..................................... 41
W
Watchdog Timer
Summary of Registers ................................................ 67
Watchdog Timer (WDT) ...................................................... 66
WWW, On-Line Support ....................................................... 3
DS40039C-page 125
PIC16F630/676
NOTES:
DS40039C-page 126
PIC16F630/676
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
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files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Internet Explorer. Files are also available for FTP
download from our FTP site.
092002
DS40039C-page 127
PIC16F630/676
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DS40039C-page 128
PIC16F630/676
PRODUCT IDENTIFICATION SYSTEM
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DS40039C-page 129
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DS40039C-page 130