Wa Zilog BoopVn Zilog Introduction Zilog’s Component, Board and Development System Data Book provides design engineers with detailed specifi cations of the Zilog products they will use in constructing their own micro-computer systems. Included are each of the following: 2.80 family of MOS LSI microcomputer components © Zilog memory components |= MCB series of microcomputer board products ‘= ZDS-1 series of microcomputer development systems ‘The Z-80 family of MOS LSI microcomputer components form the nucleus of this group of products. Together they ‘provide the highest performance family of §-bit components available, permitting system designers to enjoy unprecedent- ced benefits at modest costs. Typically, designers will choose ‘component level solutions to their system problems when the Volume of production for a given system merits the in- vvestment in engineering (usually S00 or more systems). In lower volume applications or in situations where problems other than microcomputer design require most Of the engineer's time and talent, the MCB series of micro computer board products permits the use of Z-80 techno- logy without large investments in PC Board design. MCB boards can get microcomputer produets in production faster and more reliably with lower frontend costs. Many designers of higher volume products also use MCB boards for early prototyping and pilot production-moving to their own PC board designs a the volume increases. ‘The ZDS-1 series of development systems provides hard- wate and software design and diagnostic tools for use in the development Z-80 based products at either the component oF the board level. Hardware tools include Z-80 CPU hard- ‘ware emulation, tracing bus cycles, stopping emulation on pre-defined bus conditions, verification of clock integrity, nnd mapping of development system memory into the space ofthe system under test. For software development, complete disk operating system, text editor, macro assem ber, and linker are provided together with comprehensive software debug tools. Optional programming languages such ssPLZ, FORTRAN, and BASIC provide additional design capability as well asa means for using the ZDS asa general purpose laboratory computer. Beyond the products in this Data Book, Zilog also man- ufactures a series of general purpose microcomputers for ‘OEM or large end customer use. These products are cur- rently described by individual specifications and brochures. ‘These will be collated to form a Microcomputer System ‘Data Book in the spring of 1979.Vs Zilog Table of Contents SECTION I: COMPONENTS 1 Z-80/Z-80A CPU 3 Z-80/Z-80A PIO 13 7-80/Z-80A CTC 2 2-80/Z-80A DMA 2 Z-80/Z-80A SIO Z-80/Z-80A SIO|9 64 26104-4096 x 1 Bit Static RAM 66 Z6114—1024 x 4 Bit Static RAM 2 26142-1024 x 4 Bit Static RAM 7 SECTION 2: BOARDS. : . 81 Z-80 MCB Microcomputer Board : So ooce . 83 Z-80 MDC Memory Disk Controller. 88 Z-80 RMB RAM/ROM Memory Board a Z-80 PPB PROM Programmer Board 94 Z-80 PPB/16 PROM Programmer Board 98 Z-80 AIO/AIB Analog Input/Output Board 101 Z-80 10B Parallel 1/O Board ‘ 105 Z-80 PMB PROM Memory Board sean 108 Z-80 SIB Serial Interface Board MW SECTION 3: DEVELOPMENT SYSTEMS 7 ZDS-1 Series - 9 SECTION 4: MISCELLANEOUS . 129Section 1 ComponentsVa Zilog Section 1 Components Zilog components fall into two categories: the Z-80 family of microprocessor eircuts and the Z6100 family of read/write memories. The Z-80 Microprocessor Family The 7-80 CPU has rapidly established itself as the most powerful, most sophisticated and most versatile Sit microprocessor. Although sourcecode compatible with the popular 8080A microprocessor, the Z-80 CPU has many ditional features that simplify hardware requirements and programming while increasing execution speed. Dual sepister st allows high-speed context switching and intesrupt processing. = Two index registers give additional memory addressing flexibility © Onchip refresh logic simplifies interfacing with dynamic RAMs ‘© Powerful block move and string manipulation as well a, bit manipulation instructions reduce programming effort, program size and execution time Four peripheral functions are generally required in mierocomputer systems: parallel input/output, serial input) output, countingtiming, and direct memory access. These basic functions are provided by four Z:80 peripheral circuits that complement the 2-80 CPU: The 2:80 PIO (Parallel Input/Output) offers two 8-it 1/0 ports with individual handshake and pattern-detection capability The 280 CTC (Counter/Timer Circuit) offers four versa tile counter/imers with individually programmable prescalers, The 280 SIO (Serial Input/Output is a powerful dual channel device that can operate as an asynchronous or synchronous recivestransmitter. The Z:80 SIO supports all popular data communications protocols including Bisyne, SDLC and HDLC. Additionally, the Z-80 SIO offers on-chip parity and CRC generationjchecking, FIFO buffering, and flag and frame detection] generation logic. © The Z-80 DMA (Direct Memory Access) isasophisticated controller that transfers data directly between any two ports (I/O and memory, for example). The Z-80 DMA can search for data patterns even when transferring ‘The normal clock rate for Z-80 components is 2.5 MHz, but all are available in a Z-80A version with a maximum clock rate of 4 MElz, A vectored priority interrupt struc ture common to all Z-80 components handles up to 128 vectored interrupts defined by loadable registers in both the peripherals and the CPU. No external interrupt controller is required. Read/Write Memories In addition to microprocessor components, Zilog offers three 4K static RAMs and a 16K dynamic RAM. All three 4K static RAMs contain on-chip address registers, activated by the Chip Enable input. Polysilicon load resistors used in the memory arrays of the static RAMS result in a very small die size. © The 26104 is organized 35 4096 addresses by one bit. = The Z6114 is organized as 1024 addresses by four bits, with four bidirectional I/O lines that make it ideal for small systems, 1 The Z6142 is identical tothe 26114, except that it offers ‘an Output Enable input and an additional Chip Enable input for greater flexibility in small microprovessor- based systems. = The Z6116 is an industry-standard 16K by one bit dynamic RAM, available in a range of access times. ‘These Zilog components are manufactured with n-chan- ‘nel depletion-load silicon-gate technology using ion-implant- ation and shallow junctions for high performance and pro- jection printing on fourinch wafers for high yield and low cost.vi Zilog Product Specification ‘The Zilog 280 product line is a complete set of micto- computer components, development systems and support software, The Z80 microcomputer component set includes all of the circuits necessary t0 build high-performance microcomputer systems with virtually no other logie and ‘minimum number of low cost standard memory elements. ‘The Z80 and Z80A CPU's are third generation single chip ‘microprocessors with unrivaled computational power. This increased computational power results in higher system ‘through-put and more efficent memory utilization when compared to second generation microprocessors. In ‘addition, the Z80 and Z80A CPU's are very easy to imple- ‘ment into a system because of their single voltage require ‘ment_plus all output signals ate fully decoded and timed t0 control standard memory or peripheral circuits. The circuit is implemented using an N-channel, ion implanted, silicon gate MOS process Figure 1 isa block diagram of the CPU, Figure 2 details the internal register configuration which contains 208 bits ‘of Read/Write memory that are accessible to the program- ‘mer. The registers include two sets of six general purpose registers that may be used individually as 8-bit registers or as 16-bit register pairs. There are also two sets of accumu- lator and flag registers. The programmer has access to either set of main or alternate registers through a group of ex change instructions. This alternate set allows foreground) background mode of operation or may be reserved for very fast Interrupt response. Each CPU also contains 2 16-bit stack pointer which permits simple implementation of COMPONENTS Z-80 CPU Z-80A CPU multiple level interrupts, unlimited subroutine nesting and simplification of many types of data handling. ‘The two 16-bit index registers allow tabular data manipu. lation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transparent refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of a pointer toa interrupt service address table, while the interrupting device supplies the lower 8 bits of the pointer. An indirect call is then made to this service address. FEATURES © Single chip, N-channel Silicon Gate CPU. ‘© 158 instructions—includes all 78 of the 8O80A instruc- tions with total software compatibility. New instruc- tions include 4-, 8-and 16-bit operations with more useful addressing modes such as indexed, bit and relative © 17 internal registers. ‘© Three modes of fast interrupt response plus @ non- wskable interrupt, ‘© Directly interfaces standard speed static or dynamic memories with virtually no external logic, © 1.0 ys instruction execution speed. Single $ VDC supply and single-phase 5 volt Clock. © Outperforms any other single chip microcomputer in 4-,8-, or 16-it applications. ‘© All pins TTL Compatible © Built-in dynamic RAM refresh circuitry. 780, 280A CPU BLOCK DIAGRAM 780, 280A CPU REGISTERSY% Z-80°CPU Z-80A CPU Z-80, Z-80A CPU Pin Description Zilog (COMPONENTS indicates that should be used to do a refresh read to all transfer. The CPU continues to enter wait ware controlled interrupt enable flip-flop ‘nterrupt request line has 2 higher priority and set interrupt to 8080A mode. During reset time, the address and data bus go (0 Input, active low. The bus request signal has a higher priority than NMI and is always ree ognized at the end of the current machine cycle and is used to request the CPU address bus, data bus and tristate output control signals to go to a high impedance state so that other devices can control these busses. tristate control bus signals have been set RFSH Output, active low. RFSTT (Refresh) the lower 7 bits ofthe address bus con- | tain a refresh address for dynamic = memories and the current MREQ signal \ dynamic memories, af as TACT Output, active low. HALT indicates that “| (Halt state) the CPU has executed a HALT software = instruetion and is awaiting ether a non- -_ maskable or a maskable interrupt (with ee the mask enabled) before operation can resume, While halted, the CPU executes sem NOP’ to maintain memory refresh activity WAIT Input, sctve low. WATT indicates to the 280, 2308 CPU PIN CONFIGURATION | ome ciee ae Ag-Ais Tristate output, ative high. Ag-Aj5 states fora longa this signal i activ. (Aadaress Bus) constitute 16-bit address bus. The address bus provides the address for = meno (ok bd ee econ ae exchanges and for I/O device data exchanges. Request) request will be honored at the end of the Cuttet instruction ithe internal sft Dy -Dp Rsateinavoupt ate ih (Bria bus) Dp-D7 constitute an 8bit bidirectional spires data bus. The data bus is used for data oie) Ct Nee nee wT Input, ative low. The non-maskable — — (Non mi Output, active low. indicates thatthe Maskable than INT andi always recognized atthe (Machine current machine eycle is the OP code Inerupt) end of the current instruction, indepen- Cycle one) fetch eycle ofan instruction execution dent of the status of the interrupt enable flip-flop. NT automaticaly forces the REQ Tristate output, active low. The memory Z-80 CPU to restart 10 location 00664, (Memory request signa indicates thatthe address Request) bus holds a valid addres for a memory RESET Input, active low. RESET initaies the read or memory write operation CPU as follows: rest interrupt enable flip-flop, clear PC and registers I and R- TORO ‘Tristate output, active low. The TORO (lnput/ signal indicates that the lower half of the Output address bus holds a valid 1/0 addres for a high impedance state and all control Request) 1/0 read or write operation, An TORQ output signals goto the inactive state Signal is alo generated when an intermpt, ‘sbeing acknowledged to indicate that an TUR interrupt response vector ean be paced (ous on the dats bus. Request) wD Tristate output, active low. RD indicates (Memory thatthe CPU wants to read data fiom Read) memory or an /0 device, The addressed YO device or memory should use this oe. _— .. — = (Bus used to indicate tothe requesting device WR ‘Teistate output, setive low. WR indicates Acknowledge) thatthe CPU address bus, data bus and (Memory thatthe CPU data bus holds valid data to Write) be stored in the addressed memory or 110 to their high impedance sate and device. external device can now control these signal:% Z-80° CPU Z-80A CPU COMPONENTS Zilog Timing Waveforms INSTRUCTION OP CODE FETCH The program counter content (PC) i placed on the address bus immediately at the start of the eyele, One half clock time later MREQ goes active. The falling edge of MREQ can be used ditectly asa chip enable to dynamic ‘memories. RD when active indicates that the memory data should be enabled onto the CPU data bus. The CPU samples data with the rising edge of the clock state T Cock states T3 and Ty ofa fetch cycle are sed to refresh dynamic memories while the CPU is internally decoding and executing the instruction, The refresh control signal FSH indicates that a refresh read ofall dynamic memories should be accomplished MEMORY READ OR WRITE CYCLES Illustrated here isthe timing of memory read or write cycles other than an OP code fetch (My cycle). The MREO and RD signals are used exactly asin the fetch eyele, In the case of a memory write cycle, the MREQ also becomes active when the address bus is table so that it can be used directly asa chip enable for dynamic memories, The WR line is active when data on the data bus is stable so that it can be used directly asa Ry/W pulse to virtually any type of semiconductor memory. INPUT OR OUTPUT CYCLES Ilustrated here i the timing for an 1/0 read or 1/0 write ‘operation. Notice that during 1/0 operations a single wait sate is automatically inserted (Tw*). The reason for this is that during 1/0 operations this extra state allows sufficient time for an 1/0 port to decode its address and activate the WATT line if a wait is required, INTERRUPT REQUEST/ACKNOWLEDGE CYCLE ‘The interrupt signal is sampled by the CPU with the rising edge ofthe last clock at the end of any instruction ‘When an interrupt is accepted, a special My cycle is generated. During this My cycle, the TORO signal becomes active (instead of MREQ) to indicate thatthe interrupting. device can place an 8-bit vector on the data bus. Two wait states (Tw*) are automatically added to this eycle so that a ripple priority interrupt scheme, such as the one used in the Z0 peripheral controllers, can be easily implemented.%Y% Z-80°CPU Z-80A CPU Zilog BIT LOADS 16BIT LOADS EXCHANGES. ‘The following isa summary of the Z80, Z80A instruction set showing the assembly language mnemonic and the sym- bolic operation performed by the instruction. A more de- tailed listing appears in the Z80-CPU technical manual, and assembly language programming manual. The instructions are divided into the following categories Shit loads Miscellaneous Group 16bit loads Rotates and Shifts Exchanges Bit Set, Reset and Test Memory Block Moves Input and Output Memory Block Searches Jumps Sit arithmetic and logic Calls 16-bit arithmetic Restarts General purpose Accumulator Returns ‘& Flag Operations In the table the following terminology is used COMPONENTS Instruction Set any 8-bit destination register or memory location any 16-bit destination register of memory location 8.it signed 2's complement displacement used in relative jumps and indexed addressing 8 special call locations in page zero, In decimal notation these are 0, 8, 16, 24, 32, 40, 48 and 56 n= any Sit binary number nn = any 16Dit binary number ' ay S-bit general purpose register (A, B,C, DE lor L) s = any 8bit source register or memory location sh = abit ina specific it register of memory location 88 any 16-bit source register or memory location subscript "L” = the low order 8 bits of a 16-bit register subscript “H” = the high order 8 bits of a L6-bit register ©) = the contents within the () are to be used asa b= abit number in any 8-hit egister or memory pointer toa memory location or 10 port number location >it registers are A, B,C,D, E,H, L, Vand R ‘ce = Mag condition code 16bit register pars are AF, BC, DE and HL NZ = non 2er0 16-bit registers are SP, PC, IX and 1Y 2. = 200 Ne = non cary ‘Addressing Modes implemented include combinations of ce ser the following: Immediate Indexed PO. = Patty odd orno overflow Immediate extended Register PE = Patty even or over flow Modified Page Zero Implied P= Positive Relative Register Indirect, M_— = Negative (minus) Extended Bit Mnemonic _| Symbolic Operation Comments Mnemonic | Symbolic Operation [ Comments Des [rvs Sei n(H). oy (DE) = (HL), DE = DET axreavee) |g HL + HL+1, BC+ Be: war | der HL). | 3] Lon | (DE)~ (aL), DE~ DEH (xte).(lvee) |Z HL ~HL+1, BC = BC-1 on loo HL), g Repeat until BC=0 (ix+e), vee) |] LD (DE) + (HL), DE + DE-1 IDAs | Acs += (BC),(DE). | % HL ~HL-1, BC + BC-1 (an), 1.R | LopR (DE) « (HL), DE = DE-1 LDda dea 7 HL ~HL-1, BC = BC-1 Repeat until BC= 0 ——$ $$ LDddvan | ddan for AH). HUTT i, sP.ixty | 2 Be = BC-1 LD dd, (nn) | dd = (on) aa=ac, de, | 2) coir AAHLHL HLH | AHL) sets HL.sP.ixty | & BC = BC-1, Repeat the Mags only. LDnm).s8 | (anys senc.pe, | until BC =O or A= (HL) | Aisnot affected HLSP.IXIY | 2 cpp AHL), HL=HL-1 Loss | spose sseHLixay | 2 BC+ Be-I Pustis | (r-p~syicsr-2y~ss,|s-0c-08, | Slop fa 3 HL), HL = HL-1 nL aFncy |Z Bee bert nasa Pordd — | aa, « (sP):ady,« (SP*1) | da = BC, DE, until BC= 0 oF A= (HL) tars | | ee ee ere EXDE,HL | DE--HL ADCs JAAss+c¥ CV isthe EX AB.AF’ | AF ~ AB? 3] suns fan a-s carry flag EXX BC\ Bc’ [secs J Aa-s-cy (HL) De ee 2] ANDs AAAS (Xe), (1¥#e) Ly NHL ors AwAVs EX (SP).55_ | (SP) 55) (SPH) ayy | Ss SHL IXY xoRs [AssesY Z-80°CPU Z-80A CPU COMPONENTS Zilog Mnemonic | Symbolic Operation | Comments Mnemonic | Symbolic Operation | Comments os ron neil) | Slates [zs Zis zero fag a ee (9,9) | 2) sere. | [3a ASSES = iis) HES ioaiecial =— 58 )| RS = ween] Serra tier so oils o (233) Sameecee as ae Sa) Soi eseams = o| Rare ESS (4 ceatgee® “ocany | Witty fom Rang ip ofGone tow Tor | oe ‘w(WRL) = [aay | Ripiemercenis ae smon| Elite pabertes eer oa eles PST | owen) | RFSH One From Roan Ed of Cock, RFSH Hoh Tp ee] 1” aan | eater arnt al Tan [ey [ ar cnn [=m a a ot oe wary [pean alee = CN a Salant Sse ee es er re | Ro rt i es TE [gn [Teer ston sc ee oe oT ina es eee “A. (Data shouldbe enabed oot the CPU data bus when RD is ctv: During interop acknowledge dats — ‘shouldbe enabled when HIT and TORTS ae borh save. eit ¢ Secon et tense ee : 6 RERESET at men oine 3ktn tam Seer ‘Aid Ona delay french Sop cent a upto masa of 20p for tabu nd 100 for ‘He sore te, teste Aino by eg, eg ae gg 20.8: mama 10ZB Y% Z-80 CPU Z-80A CPU Zilog Absolute Maximum Ratings Tempentue Under Bas Speidonersing runt. *Comment Sige Temperte Sse wise See above hoe ated under “Abate ‘atage On Any ave ‘Mom Rating’ may cau permanent with Reger Grou dime tothe deve Tha rates a owe: Disiption 1sw Sati ancl oat ee {thre ory ater ann sve tha Indeated he operation tos of hs ‘penton oot mpi Espo to. SeSticmzumam tg eonaton or ‘ended pesos ay afc dee elaihy Z-80 CPU D.C. Characteristics TARP WE VA SV COMPONENTS Capacitance Ty © 28°C, 1 Mite, unmeasured pins returned to ground alee Sie oi Sea cal ee ee Vie ext net Van enemas cx wins | 5 or eal ecto oes ole 1s ee [ale vy [en cal eallecla Sapa or Wap pepe ee Sr 7 Vora 7-80 CPU Te | oo nt Com ws [a Ordering Information ae we [on | Wartwve To [Rise opt tp or Fe 10 [on | Youetsiov Tor Tes eg Co rope [voces] tanta ae ae ae ‘wp [berber pet oan Z-80A CPUD.C. Characteristics Capacitance ee eee aaa oe a or eee eae ee alia Tine | oem a allele a ie) aires eotleliedlin ato Tar | ema eae Vou] Out Low Vos all eee mio 7 cltorssmal | 7 sua Cru ao [earn Ouiene Tio | Fer Our nag Con vo [oa [ vourteve| fl Svan come Tot taro op Govan] [9 [| Poorer (on eee Tre [om [ote nY% Z-80° CPU _Z-80A CPU COMPONENTS Zilog Package Outline a Dimensions for metric system are in parenthesesV7 COMPONENTS Zilog Product Specification ‘The Zilog Z-80 product line is a complete set of micro computer components, development systems and support software. The Z-80 microcomputer component set includes all ofthe circuits necessary to build high-performance ‘microcomputer systems with virtually no other logic and a ‘minimum number of low cost standard memory elements. ‘The Z-80 Parallel 1/0 (PIO) Interface Controller is a programmable, two port device which provides TTL com: patible interfacing between peripheral devices and the Z80-CPU. The Z80-CPU configures the Z80-PIO to inter- face with standard peripheral devices such as tape punches, printers, keyboards, etc. ‘Structure ‘© N-Channel Silicon Gate Depletion Load technology 40 Pin DIP © Single 5 volt supply ‘© Single phase 5 volt clock ‘© Two independent 8-bit bidirectional peripheral interface ports with “handshake” data transfer control Features ‘© Interrupt driven “handshake” for fast response ‘© Any one of the following modes of operation may be selected for either port Byte output Byte input Z-80 PIO Z-80A PIO Byte biditectional bus (avilable on Port A only) Bit Mode © Programmable interrupts on peripheral status conditions ‘© Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external loge. ‘© Eight ourputs are capable of driving Darlington transistors. © All inputs and outputs fully TTL compatible. PIO Architecture A block diagram of the Z80-PIO is shown in figure 1 ‘The internal structure of the Z80-PIO consists of a £Z80-CPU bus interface, internal control logic, Port AYO logic, Port B 1/0 logic, and interrupt control logic. A typical application might use Port A as the data transfer channel and Port B for the status and control monitoring, ‘The Port 1/0 logic is composed of 6 registers with “handshake” control logic as shown in figure 2. The registers include: an 8-bit input register, an 8-bit output register, a 2-bit mode control repister, an 8-bit mask register, an 8it input/output select register, and a 2-bit mask control register. The last three registers are used only when the port has been programmed to operate in the bit mode, sv cw INTERNAL CONTROL. f] esteRRUPT f] coxreon La Seay vara usa: bara OR CONTROL sot 1 Not wid ini ide PERIPHERAL INTERFACE, INTERRUPT CONTROL LINES FIGURE 1 PIO BLOCK DIAGRAM 13Yq 7-80 P10 2-804 PIO COMPONENTS Zilog Register Description Mode Control Register? bits, loaded by CPU to select the operating mode: byte output, byte input, byte bidirec~ tional bus or bit mode. Data Output Register-8 bits, permits data to be transferred from the CPU to the peripheral Data Input Register—8 bits, accepts data from the peri pheral for transfer to the CPU, Mask Control Register-2 bits, loaded by the CPU to specify the active state (high or low) of any peripheral device interface pins that are to be monitored and, if an inter- rupt should be generated when all unmasked pins are active (AND condition) or, when any unmasked pin is active (OR condition). Mask Register-8 bits, loaded by the CPU to determine ‘which peripheral device interface pins are to be moni- tored for the specified status condition Input/Output Select Register-8 bits, loaded by the CPU to allow any pin to be an output or an input during bit mode operation, Used the it mode ow gnetion of a0 Interap ifthe pergberat 10 pin gota the specid wate FIGURE 2 ATYPICAL PORT 1/0 BLOCK DIAGRAM s0rr Wo BUS, LINESYj 1-80 P10 7-80A PIO COMPONENTS Z-80 PIO Pin Description Mi Machine Cycle One Signal from CPU (input, active low) g. TORO —_ Input/Output Request from Z80-CPU (input, . active low) RD Read Cycle Status from the Z80-CPU (input, active low) Sone 1} Interrupt Enable In (input, ative high) IEO __Intereupt Enable Out (output, active high). IEI and IEO form a daisy chain connection for priority interrupt control WT Interrupt Request (output, open drain, active Sak low) Soe cum AgrAy Port A Bus (bidtectional, istte) STB Port A Strobe Pulse from Peripheral Device (input, active low) DzyDq __ Z80-CPU Data Bus (bidirectional, tristate) ARDY Register A Ready (output, active high) BJA Sel Port B or A Selet (input, active high) By) Port B Bus (idectonl, sate) Ske) ele ere eead BSTB Port B Strobe Pulse from Peripheral Device e Chip Enable (input, active low) (nut, active low) ° ‘System Clock (input) BRDY Register B Ready (output, active high) Timing Waveforms OUTPUT MODE ‘An output cycle is always started by the execution of an output instruction by the CPU. The WR pulse from the CPU latches the data from the CPU data bus into the selected port’s output register. The write pulse sets the ready flag after a low going edge of ® indicating data is available. Ready stays active until the positive edge of the strobe line is received indicating that data was taken by the peripheral. The positive edge of the strobe pulse generates an INT if the interrupt enable fip flop has been set and if this device has the highest priority INPUT MODE. ‘When STROBE goes low data is loaded into the selected port input register. The next rising edge of strobe activates INT if interrupt enable is set and thisis the highest priority requesting device. The following falling edge of resets Ready {0 an inactive state, indicating that the input register is full and cannot accept any more data until the CPU completes a read. When a read is complete the positive edge of RD will set Ready at the next low going transition of ®. AC this time new data can be loaded into the PIO. aa wn RB ce 10R0Za 2-38 0 2-008 PO COMPONENTS Timing Waveforms Bete, MODE This isa combination of modes O and 1 using all four hhandshake lines and the 8 Port A 1/0 lines. Port B must be set to the Bit Mode. The Port A handshake lines are used for output control and the Port B lines are used for input control. Data is allowed out onto the Port A bus only when ASTB is low. The rising edge of this strobe can be used to latch the dats into the peripheral BIT MODE ‘The bit mode does not utilize the handshake signals and a normal port write or port read can be executed at any time. When writing, the data will be latched into the output registers with the same timing as the output mode. When reading the PIO, the data returned to the CPU will be composed of output register data from those port data lines assigned as outputs and input register data from those port data lines assigned as inputs. The input register will contain data which was present immediately prior to the falling edge of RD. An interrupt will be generated if interrupts from the port are enabled and the data on the port data lines satisfy the logical equation defined by the bit mask and 2-bit mask control registers, INTERRUPT ACKNOWLEDGE During MI time, peripheral controllers are inhibited from changing their interrupt enable status, permitting the INT Enable signal to ripple through the datsy chain, The peri- pheral with TEI high and IEO low during INTA will place a preprogrammed 8-bit interrupt vector on the data bus at this time. IEO is held low until a return from interrupt (RET!) instruction is executed by the CPU while TET is high. The 2-byte RETI instruction is decoded internally by the PIO for this purpose. RETURN FROM INTERRUPT CYCLE I 2 780 peripheral device has no interrupt pending and is not under service, then its IEOIEI If it has an interrupt under service (ie, ithas already interrupted and received an interrupt acknowledge) then its [EO is always low, in- hibiting lower priority chips from interrupting. IF it has an interrupt pending which has not yet been acknowledged, EO will be low unless an “ED” is decoded asthe first byte of atwo byte opcode. In this case, IEO will go high until the next opcode byte is decoded, whereupon it wll again 0 low. Ifthe second byte of the opcode was “4D” then the opcode was an RET! instruction ‘After an “ED” opcode is decoded, only the peripheral device which has interrupted and iscuerently under sevice will have its TEI high and its IEO low. This device isthe highest priority device in the daisy chain which has receiv- ed an interrupt acknowledge. All other peripherals have TEIIEO. If the next opcode byte decoded is “4D”, this peripheral device will rset its “interrupt under service” condition AU ew saa } 16WA 1-80 PIO Z-80A PIO COMPONENTS Zilog PIO Programming LOAD INTERRUPT VECTOR INTERRUPT CONTROL, ‘The Z80-CPU requiresan8-bitinterrupt vectorbe supplied «BIL 7=1 interrupt enable is st-allowing by the interrupting device. The CPU forms the address for interrupt to be generated. the interrupt service routine of the port using this vector. BR7=0 indicates the enable flag is reset and During an interrupt acknowledge cycle the vector is placed ‘on the Z-80 data bus by the highest priority device request- ing service at that time. The desired interrupt vector is Toaded into the PIO by writing a control word to the desired port of the PIO with the following format bre ps pss br» w]w)yululwe]u fe Gene ts conit word a rp SELECTING AN OPERATING MODE ‘When selecting an operating mode, the -bit mode con- ‘ol register is et to one of four values. These two bits are the most significant bits of the register, bits 7 and 6; bits 5 and 4 are not used while bits 3 through O are all set to 1111 to indicate “set mode.” br be os bys boo wm | mo] x | x —— ‘mode word sgner ode word ihe rane it Mode ‘Output Input Bidirectional Bit ==. ele | Mo 0 1 o 1 MODE 0 active indicates that data is to be written from the CPU to the peripheral, MODE 1 active indicates that data isto be read from the ‘peripheral to the CPU. MODE 2 allows data to be written to or read from the ‘peripheral device. MODE 3 is intended for status and control applications. When selected, the next control word must set the 1/0 Register to indicate which lines are to be input and Which lines are to be output YO = 1 sets bit to input. YO =0 sets bit to output, bribe ps ps bs? Wo; | 104] 105 | v0, | 105 | v0, ] v0, | 1105 interrupts may not be generated Bits 6,54 are used in the bit mode interrupt operations; otherwise they are disregarded. Bits 3,2,1,0 signify that this command word isan ierrupt control word, br_be bss only gies meray Ifthe “mask follows” bit is high (D4 = 1), the next control word written to the port must be the mask br__be ps pes pr re sua; | 0, | ma, [ me, | oo, | a0, | a5, | a0, ‘nly those pct ines whowe mask bit isn Owl be monitored fr ‘roertng an imterap ‘The interrupt enable flip-flop of a port may be set or reset without modifying the rest of the interrupt control word by the following command. bibs ps tbs otto Tet Poel aZilog Z-80 PIO Z-80A PIO COMPONENTS Z-80 PIO A.C. Characteristics TA =0°C to 70°C, Vec = +5 V + $%, unless otherwise noted | omnes oo | | om 2 | Sige | Shien co fe | se | Se CEE] coven | Come Step Tne kpc? Oooo | 20 7 fe Sine Toro) | Serna am Fog a oR wo [m= far BN | Sette rtcmaeteattOmmeor | oo 7 90 one cyt tovoy | Ses Day fom ting et ID Ori TA a | mae | BF Te _| een | tren tne wren tap RD Owin Tac | 10 7 “oo, | 0 Or Ts rom ia ot we [= |e ou io) | 160 Dae om Fay Ey fH rot Osi Jt 30 | me fist” THR | wea | WRSsnetnwienomtante orm naewin | Bo = oer | wean | Westpteconimtandeoummaam | 30 7 Bee Sorc 7 | wowoy | Rens tnwionen tanto Oni tier | 20 = ore cero) | fetOmsaunroeronanytan a TRGRE moa) | 20 = ‘SEe, | Re Om uma hon fn Can ORE wo | om | tom tie BE | or | Btamreron ten ens a0 | me | cusson toro) | feeds date ton Ria RD Ova Wt a0 | mee | | wan | pomwan, SORE = = a a = mm | oun Teton io SHOE wo | om Zao | toms | Pe Reso Tem Ron TD ~l=le ee ee ae S| la 1A. 2516512) 0) * tm) “15 He) THE Bt Dt a 1 ceo meienn tana (2) none pn 0B Hom or 0 incense 6 20 ot 13) nano 19 1 Ovtput load crest 51> [51 Inara ha oy 2 er eh Yt ce inlet to 10 of ms HEE Capacitance a Parameter Ma] Un Tea Condition lock Capacitance TO | pF) Unmeased Pins Tapa Capacitance TTF] Returned to Ground | GaiparCapastance i F | 18Yp1-80 PIO Z-80A PIO COMPONENTS Zilog twinronrenoa ee uta eon aa nl tw ci eae A.C. Timing Diagram ctock 42v_ av ourur 20 av nur 20v av Float av. = +08V% Z-80 PIO Z-80A PIO COMPONENTS Zilog Z-80A PIO A.C. Characteristics TA =0° C to 70°C, Vee = 45 V+ 5%, unless otherwise noted : ious | Gock Rae with, Cot Lon ie | | a ea | eee eee li = een | moet herent aoiailer ge |Exwmare. fe [*|m ower a eeu cy | on antago =| = 1S fant ait | emwasmneroneroamierea! na = wo | aiB | te Z aoe BE | com | GRimuetannmntinavonanae Pe w" ‘ony | Wi Seedprine so Rig Edo @ Owing ITA oe 0 Borer] Bgostmwtantersbamtas va = sro | ferOmtntn tase ttn OEBTame | oe = ue, | RSI eile 1807 | seer | Siete rt sontanstapattTa | | om | ae | eyes creo) | Seber neta ten a ORS oveg et =) ie Pas twisty | Pulse Wicth, STROBE 0 mee ban, | Htcimtmonutnae Ae Tagr | ine | Mar ee eho RS 4 1 estan tne {2} tee BT rfr 80 ¢ aaen sin v20 4 ma. {3 tree tn) HOt ts 8p nce gu eo ae Ue Fea wns 9)Yj 7-80 PIO Z-80A PIO COMPONENTS Zilog Absolute Maximum Ratings “Tempentre Under Bis Specified operating rane. Stone Tenperure 65" Cea e150" ‘osape On Ay Pi Wh Respect To Ground ower Despation soavieny comment ‘Stes above thos ited under “Abe Manian ang” ay case permaren daar to the dence. ‘hie a sete ol and fusctonl operation of {he devices these my other conan above those Indoned the operational ction of his pete thn ot mpi Exponte oasolte maaan fatig sitions or extended pods ah afc, deve easy Note: AI|ACand DC character remain the se for ‘he mary sade parts exert Io Z-80 PIO and Z-80A PIO D.C. Characteristics a TA=0" C(o 10°C. Voo= SV £57 lester sete Symbol Parmeter Win [ wax [Unt [Tot Condition Vie fC par Law Vote =| a | Vine Cask ep Fiah Vane vee [ros | Vit Tepat Low Wologe arp oe Pe Ti Tapa Fak Vole Tope fe Vou] Ontpat Low Wage TEP] tor =20m Vou | Outra Hgh Vatae oH TT] ton: 25044 Toc [Peer Suppl Coe mG iT Tapat Leakage Covent T[ oa] Vie O10 Ver Thon | Fe SiateOuper atage Curent Fat Te 410 Vee Tyo, | Fr Siate Onur Lelape Cuenta Frat =a av iy Data Bs akg Cue Tp Mode FO [aA] 05 yy < Vee Ton | Deaton Dive Caren 7 aA] og 150 Por 8 On Pacl suuevauvusveseusuees "Dimensions fox metic system are in parentheses ‘kage Outline FS ~ |b sgae Ordering Information Po Paste $ Standard SV + 55.0°1070°C En Extends SV Se 0" 0 85°C Matar 59 10 55" 16 257 nan 28010 C5 (Cenic—Stndard ngs)Va COMPONENTS Zilog Product Specification ‘The Zilog 280 product line is a complete set of micro computer components, development systems and support software. The Z80 microcomputer component set includes all of the circuits necessary to build high-performance microcomputer systems with virtually no other logic and ‘a minimum number of low cost standard memory elements. ‘The Z80-Counter Timer ircuit (CTC)isa programmable, four channel device that provides counting and timing functions for the Z80-CPU. The Z80-CPU configures the Z80-CTC’s four independent channels to operate under various modes and conditions as required. Structure N-Channel Silicon Gate Depletion Load Technology 28 Pin DIP Single 5 volt supply Single phase 5 volt clock Four independent programmable 8-bit counter/16-bit timer channels Features © Each channel may be selected to operate in either a counter mode or timer mode. © Programmable interrupts on counter or timer states. Z-80 CTC Z-80A CTC © A time constant register automatically reloads the down counter at zero and the cycle is repeated. ‘@ Readable down counter indicates number of counts-to-g0 until ze. © Selectable 16 or 256 clock prescaler for each timer channel. 1 Selectable positive or negative trigger may initiate timer operation. (© Three channels have zero count/timeout outputs capable of driving Darlington transistors. ‘© Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic, © Allinputs and outputs fully TTL compatible. ‘© Outputs directly compatible with Z80-SIO. CTC Architecture ‘A block diagram of the Z80-CTC is shown in figure 1 ‘The internal structure ofthe Z80.CTC consists of a Z80-CPU_ ‘bus interface, internal control logic, four counter channels, and interrupt control logic. Each channel has an interrupt vector for automatic interrupt vectoring, and interrupt priority is determined by channel number with channel 8 ‘having the highest priority ‘The channel logic is composed of 2 registers, 2 counters and control logic as shown in figure 2. The registers include an 8-bit time constant register and an 8-bit channel control register. The counters include an 8.bit readable down counter and an 8:bit prescaler. The prescaler may be programmed to divide the system clock by either 16 or 256. INTERRUPT CONTROL UNES ZERO COUNT/TIMEOUT {CLOCK TRICCERS ZERO COUNT/TIMEOUT 1 CLOCKTRIGGER | ZERO COUNT/TINEOUT 2 FIGURE 1 CTC BLOCK DIAGRAMCh Z-80 CTC Z-80A CTC COMPONENTS Channel Counter and Register Description ‘Time Constant Register ~- 8 bits, loaded by the CPU to initialize and re-load Down Counter at a count of zero. Channel Control Register ~ 8 bits, loaded by the CPU to select the mode and conditions of channel operation. Down Counter ~ 8 bits, loaded by the Time Constant Register under program control and automatically at a ‘count of zero. At any time, the CPU can read the number ‘of counts-to-go until a zero count. This counter is de- ‘eremented by the prescaler in timer mode and CLK/TRIG in counter mode. Prescaler — 8 bit counter, divides system clock by 16 or 256 for decrementing Down Counter It is used in timer ‘mode only. EXTERNAL CLOCK TIER TRIGGER ZERO COUNT/TIMEOUT FIGURE 2 CHANNEL BLOCK DIAGRAM Z-80 CTC Pin Description » CLK/TRGg Channel 9 External Clock or Timer Trigger os (input) ne ) gums CLKJTRG1 Channel 1 External Clock or Timer Trigger o. (input) « CLKTRG2 Channel 2 External Clock or Timer Tage ong) = |e CLK/TRG3 Channel 3 External Clock or Timer Trigger pase (Input) “aah { " ZC/TO9 Channel 9 Zero Count or Timeout (output, active high)Car: 80° CTC Z-80A CTC COMPONENTS. Z-80 CTC Pin Description (continued) ZC/TO, Channel 1 Zero Count or Timeout RD Read Cycle Status from the 280-CPU (input (output, active high) active low) ZCITO —_ Channel 2 Zero Count or Timeout EL Interrupt Enable In (input, active high) output, active hi 7 . 1E0 Interrupt Enable Out (output, active high). CS} ~CSq Channel Select (input, active high). These TEL and TEO form a daisy chain connection form a 2-bit binary address ofthe channel for priority interrupt control Glee: Wi Interrupt Request (output, open drain, D7 Dp 280-CPU Data Bus (bidirectional, tistate) active low) cE Chip Enable (input, active low) RESET RESET stops all channels from counting and — resets channel interrupt enable bits in all System Clock (input) control registers. Duringreset time ZC/TOp.2 i Machine Cycle One Signal from 280-CPU and INT go to the inactive states, IEO reflects (input, active low) the state of IEI, and the data bus output drivers — 0 to the high impedance state (input, active TORO Input/Output Request from 280-CPU (input, low) active low) Goan Timing Waveforms Iystated here is the iming for losding a channel control word, time constant and interupt vector. No wait states are allowed for writing tothe CTC other than the automatically inserted (Ty*), Since the CTC doesnot receive a specific waite signal, it internally generates its own from the lack of an RDsignal CTC READ CYCLE Iustrated here isthe timing for reading a channel's Down Counter when in Counter Mode. The value read ‘onto the data bus reflects the number of external clock’s rising edges prior to the rising edge of cycle (T). No wait states are allowed for reading the CTC other than the auto- ‘matically inserted (Ty*). INTERRUPT ACKNOWLEDGE CYCLE Some time after an interrupt is requested by the CTC, the CPU will send out an interrupt acknowledge (Mi and TORO). . uring this time the interrupt logic of the CTC will determine the highest priority channel which is requesting an interrupt. To insure that the daisy chain enable lines stabilize, channels are inhibited from changing their interrupt request status when Mi is active. Ifthe CTC Interrupt Enable Input (IEI) is active, then the highest priority interrupting channel places the contents of its interrupt vector register onto the Data Bus when TORO goes active. Additional wait cycles are allowed. Ce OC aVa Z-80 CTC Z-80A CTC COMPONENTS Timing Waveforms (continued) RETURN FROM INTERRUPT CYCLE Ia Z80 peripheral device has no interrupt pending and is ay a rot under service, then its [EO = TET. If it has an interrupt, ‘under service (ie. it has already interrupted and received an interrupt acknowledge) then its [EO is always low, inhibit ing lower priority chips from interrupting. IF it hasan inter- rupt pending which has not yet been acknowledged, LEO will be low unless an “ED” is decoded as the first byte of a two byte opcode. In this case, [EO will go high until the next opcode byte is decoded, whereupon it will again go low. If the second byte of the opcode was a “4D” then the opcode was an RETI instruction. After an “ED” opcode is decoded, only the peripheral device which has interrupted and is currently under service will have its TET high and its [EO low. This device isthe high est priority device in the daisy chain which has received an interrupt acknowledge. All other peripherals have IEI = [EO. If the next opcode byte decoded is "4D", this peripheral device will reset its “interrupt under service” condition, ‘Wait cycles are allowed in the MI cycles. DAISY CHAIN INTERRUPT SERVICING. which may esr inthe CTE Tn hi seuence cha om ES interrupts and is granted service. While this channel is being io e 5 ee aL serviced, hier priority channel 1 interrupts and i granted eee ee service. The service routine for the higher priority channel : eer Sin i completed and a RETI instruction is executed to indicate fn} to the channel that its routine is complete. At this time the 2 canner SeTRETENG ERT setvice routine of lower priority channel 2is completed, fe ep fer wf fo CTC COUNTING AND TIMING In the counter mode the rising or Falling edge of the CLK. nmonmnonn, input causes the counter to be decremented. The edge is detected totally asynchronously and must have a minimum. 2... CLK pulse width. However, the counter is synchronous with ‘ therefore a setup time must be met when it is desired to sunt aa have the counter decremented by the next rising edge of ®. 7 once In the timer mode the prescaler may be enabled by a rising 2 a —— or falling edge on the TRG input. As in the counter mode, LeeLee the edge is detected totally asynchronously and must have a minimum TRG pulse width, However, when timing is to ee start with respect to the next rising edge of a setup time ust be met. The prescaler counts rising edges of vgn [orm 2sYar-s0 CIC 7-804 CIC Zilog SELECTING AN OPERATING MODE ‘When selecting a channel’s operating mode, bit is set to 1 to indicate this wordis to be stored in the channel control register. fea wom | aver | noe [ronan See D ssee Bit 7 Channel interrupts disabled, Bit7 ‘Channel interrupts enabled to occur every time Down Counter reaches a count of zero. Setting Bit 7 does not let a preceding count of zero cause an interrupt. Bit 6 ‘Timer Mode ~ Down counter is clocked by the prescaler. The period of the counter is P= prescale of 16 or 256 TC = 8 bit binary programmable time constant (256 max) Counter Mode ~ Down Counter is clocked by external clock. The prescaler is not used Bit ‘Timer Mode Only-System clock ® is divided by 16 in prescaler. Bits ‘Timer Mode Only-System clock @ is divided by 256 in prescaler Bit ‘Timer Mode ~ negative edge trigger starts timer operation. Counter Mode — negative edge decrements. the down counter. Bit ‘Timer Mode — positive edge trigger starts timer operation, Counter Mode — positive edge decrements the down counter. Bit ‘Timer Mode Only ~ Timer begins operation on the rising edge of T of the machine cyele following the one that loads the time constant, 1 Timer Mode Only ~ External trigger is valid for starting timer operation after rising edge of Tz of the machine cycle following the ‘one that loads the time constant, The Pre- sealer is decremented 2 clock cycles later if he setup time is met, otherwise 3 clock eles. Bit 6 COMPONENTS, CTC Programming Bit 2 No time constant will follow the channel control word. One time constant must be written to the channel (0 initiate operation ‘The time constant for the Down Counter will be the next word written to the selected channel, Ifa time constant is loaded while a channel is counting, the present count will be completed before the new time constant js loaded into the Down Counter. Bit 2= Bit ‘Channel continues counting Bit Stop operation. If Bit 2= 1 channel will resume operation after loading a time constant, otherwise a new control word ‘must be loaded, LOADING A TIME CONSTANT ‘An 8.bit time constant is loaded into the Time Constant register following a channel control word with bit 2 set. All zeros indicate a time constant of 256. LOADING AN INTERRUPT VECTOR, ‘The Z80-CPU requires that an 8-Dit interrupt vector be supplied by the interrupting channel. The CPU forms the address for the interrupt service routine of the channel using this vector. During an interrupt acknowledge cycle the vector is placed on the Z80 Data Bus by the highest priority channel requesting service at that time. The desired interrupt vector is loaded into the CTC by writing into channel @ with a zero in D9. D7-D3 contain the stored in tertupt vector, D2 and Dj are not used in loading the vector When the CTC responds to an interrupt acknowledge, these ‘wo bits contain the binary code of the highest priority channel which requested the interrupt and Dg contains & zero since the address of the interrupt service routine starts at an even byte, Channel Q is the highest priority channel% Z-80 CTC Z-80A CTC COMPONENTS 10g Z-80 CTC A.C. Characteristics TA=0°C 0 70°C, Voo= #5 V# 5%, unless otherwise noted Signa! | Symbot Parameter Min max | unit | comments 6 ‘ioek Period 200 Ti . tbr | Clock Pulse Weth, Clock High 17 | 2000 ty(PLl | Clock Pulse Width, Ciock Low 170 | 2000 tntt_—_| Clock Ris and Fall Times 30 i 4 ‘Any Hold Time for Specified Setup Time ° ts as ‘ts9(68) | Control Sinai Setup Time vo Rising Edge of During Acad | 160, ae or Wate Cyele TpAID) | Date Output Delay from Rising Edge oF AD During Read | 180 mf il Cycle tsp(01 | Data Setup Time to Rising Eee of @ During Write ort | 60 m cycle a tpil0) | Dota Outpur Delay fom Falling Edge of [ORC During a0 m |i INTA Cycle ‘e101 _ | eay 0 Fostng Bus (Ourpu Butter Disab Time) 200 8 i TSIEN | TEI Setup Time to Faling Edge of TOF During NTA 200) Cyate SpHIIO! | EO Delay Time from ising Ege of 1E1 720 = [ist . SOLO) | 160 Delay Time from Falling Edge of IE 190 o |a omtto | 160 Delay fom Fating Edge of MT terupt Occurring 300 om |e just Prior 0 HT) — Tsoi) | TORO Setup Time to Rising Eage of @ During Reed or 250 o Wate Cele a soit) | BT Setup Time to Rising Edge of During INTA ort | 210 7 Cycle = Te0IRO} | AD Setup Time to Rising Edge of @ During Read ori | 240 [om Cyete | = TOOKIITY | INT Delay Time fom Rising Edge of CLK/TAG Bice! + 200 Counter Mose spelt | INT Delay Time fom Rising Edge of © tle) +200 Timer Mose TICK) | Clock Period 2c) Counter Made tty | Clckand Taper ee an Fal Times 20 Us(CK) | Clock Setup Time to sing Edge of & for Immediate Count | 210 Counter Mode sg(TR) | Trigger Setup Time to ising Edge of © fox Enabling of 210 Timer Node CLKITAGo-s| Prescaleron Following Rsiog Edge of yerh | Cock and Trager High Pulse Width 200 Counter and Timer Medes | twlcTtt | clock and Trager Low Pulse Width 200 Counter ana Timer Modes TDHIzC) | ZCITO Delay Time from Rising Eage of @, 2G/TO High 190 Counter and , | Timer odes | 267700-2 | soytzcr | zcrro Delay Time trom Falling Edge of ©. 2C/TO Low 190 Counter ard lL Timer Modes Notes: (1) tg ay li) Fayy(PLl +5, 4. (2) tnereate delay by 70 nes for asch 50 pF increase in loading, 200 pF maximum for da [2] inereate delay by 2 nec for each 10 pF increase in loading, 100 BF maximum (4) ESET must be seve for a minimum of 3 clock eyes. OUTPUT LOAD CIRCUIT vesteome vee 7 ines and 100 pF for contol lines.% Z-80 CTC Z-80A CTC COMPONENTS Zilog re eux TRep-3 201709.2 A.C. Timing Diagram clock Veg 48 oureut —20v, av ieuT ov av FloaT «av 305 wr n j=-teoti—=} tonto] fe cel fio ee! + tun'0 J ————— | ro =F tott01 J [FE TR — | wwiert) > ass et 20 FeCOMPONENTS YG Z-80 CTC Z-80A CTC Zilog Z-80A CTC A.C. Characteristics € t0 70° C, Vee = 45 V+ 5%, unless otherwise noted Siarat__ | _ Symbol Parameter Min Max | unie | Comments te ‘Cock Period 250 a ns . twlPH) | Clock Pulse Wath, Clock High 105 2000 ns wll) — | Clock Pulse With, Clock Low 105 2000 ne tet | Clock Rite and Fal Times Ed ne “Any Hold Time for Spat Setup Time ° Tene | %50165) | Contr Signal Setup Time to Rising Edge of © During Reed | 60 ns of (or Write Cycle SDRIO) | Date Output Delay from Faling Edge of RIB During Read 320 ofa Oycle tgo(0) | Osta Setup Time to Rising Edge of & During Wes or MY 50 os 0-07 ye! tpi!01 | Data Output Delay trom Falling Edge of 1ORG During 160 ow ja INTA Cycle te101 _| Delay to Floating Bus (Output Buter Disable Time) 0 ne ” tgHIEN | 1E1 Setup Time to Falling Ede of [ORG During INTA 140 ne velo TOHLIO) | 1EO Dey Time rom Rising Edge of IET 160 = | co tDLl10) | 1€0 Deley Time rom Faling Edge of 1E1 130 om | 1 tomllOd | 1E0 Delay fram Falling Edge of HT (Interrupt Occurring 190 | 31 ust Prior to MT) — TsellR) | TORU Setup Time to Rising Edge of @ During Rad or ors "8 Wie Cyele im ‘golly | A Setup Time to Rising Edge of @ During INTA or Mt 90 ne velo = TeaIRD) | RB Setup Time to Rising Edge of © During Read or MT 115 oe ovela TAF TDCKIIT | INT Delay Time from Rising Edge of CLKITRG 2iglo) +140 ‘Counter Mode 109117) _| INT Delay Time trom Rising Edge of © rele) +140 Timer Mode TICK) | Clock Period ae(e ‘Counter Mode tnt | Clock and Trigger ise and Fall Times %0 1G(CK) | Clock Setun Time ta Rising Edge of & for immediate Count| 210 Counter Mode tgiTR) | Tegger Setup Time to Rising Edge of © for enabling of 210 Timer Mode CLKITAG a Presale on Following Rising Eage of © twicTH | Clock aed Trigger High Pulse width 200 Counter and Timer Modes twiCTL) | Clock and Trigger Low Pulse Width 200 Counter nd ‘Timer Modes toHI26) | ZC/TO Delay Time from Rising Edge of ©, ZC/TO High 180 ‘Counter and Timer Modes 2CMTO0-2 | 65,1201 _| ZcITO Delay Time fomFaling Edge of ©, ZCITO Low 190 Counter and Timer Modes ry CH) + ry EPL) #4, [8] nereaee delay by 2 ste for eben 10 BF increso in loading, 100 pF maximum. [4] RESET must be active for @minimum of3 clock eyes. OUTPUT LOAD CIRCUIT Qeaun oy xy By 10 nse foreach 60 pF nezease in loading, 200 pF maximum for data lines nd 100 nF for contolY% Z-80 CTC Z-80A CTC COMPONENTS Zilog Absolute Maximum Ratings comment Temperature Under Bas OF Cio 70°C _"Shemerthor the ited under “Abate Maximum StougeTompertie 68° C10 +150"C Rtg may case permanent damage tothe dence. Yoitage Or ry Pon With hitea sete ting oly sod unctinsl opeatin of Respect To Ground Porer Dsipton the devs a these any othe condition bone ose nacre she uperatinal sects of thse ‘on rnold. Expat oebsoite maxima ‘hing condition fr exended pss may sect, deve ela D.C. Characteristics 2-80 CTC Symbol coon wn [ war [one] te conson Teg | Gone apt Low Voge 2s [ev Tine [ OoEk pt Mah Vane TT Yeo=8|Voeta|v The par cae Vata a arma ie — bi Votage — Wor | Ono tow Vas Oa TV] to =2ma Ven] Oar Hit Vota 7 1] ton = 22004 Tce ave Su Carn Tae He 00 nw Se 10 [wm ] Your =24 Vee iA aa Ott Letge Curent Fast sro P oe] vour=0av ‘ond Dwtton Ore Coen 5 a vot reer =2000 (2-80 CTC Symbol _ oe a Vine | Gost ee Law Vote — Wine Gest ege High Vetoes TT eer | vere |B Wie [rout ow Vola ‘oo [es v4 Won [at to Voeoe GeV] tons 2ma Ven | Sanat Hi Vata 7a 7] ton = 22000 tee [Pow Supt Corer Ta [ot te 2 nae Tea Rte Oviut Lntgt Coren Pet 0 [sa] vour=24 Vee ita asin OtatLstgtGurentn Feet =e ‘ono | Dmteon Gre Covent 5 Capacitance TA = 25°C, f= 1 MHz Syme — | Tet conation tee Cok cnn 20 | a 3 FE] Retune rond [eaor [oer Cor i 7 30Y% Z-80 CTC Z-80A CTC components ZilogV/s COMPONENTS Zilog Product Specification The Z-80 DMA (Direct Memory Access) circuit isa pro- grammable single-channel device which provides al addres, timing and contrl signals to effec the transfer of blocks of data between two port within most microprocessor based systems. These ports may be either system main memory or any system peripheral I/O device. The DMA can also search a block of data for a particular byte (bit maskable), with or ‘without a simultaneous transfer. Structure ‘© N-channel Silicon Gate Depletion Load Technology © 40 Pin DIP 1 Single 5 volt supply ‘Single phase 5 volt clock Single channel, two port Features © Three classes of operation: Transfer Onl ~Search Only Search-Transfer Address and Block Length Registers fully buffered. Values for next operation may be loaded without dis- turbing current values. Dual addresses generated during a transfer (one for read port and one for waite port) Programmable data transfers and searches, automatic- ally incrementing or decrementing the port addresses from programmed starting addresses (they can also remain fixed). Z-80 DMA Z-80A DMA Three modes of operation: Byte-atatime: One byte transferred per request Burst: Continues as long as ports are ready Continuous: Locks out CPU until operation complete ‘Timing may be programmed (o match the speed of any port, Interrupts on Match Found, End of Block, or Ready, ‘may be programmed. ‘An entire previous operation may be repeated automat- ically or on command. (Auto restart or Load) The DMA can signal when a specified number of bytes has been transferred, without halting transfer Multiple DMA’s easily configured for rotating priority ‘The channel may be enabled, dssbled or reset under software conta Complete channel status upon program (CPU) request Up to 1.25 megubyte/second Search. Daisy-chain priority interrupt and bus acknowledge in cluded to provide automatic interrupt vectoring and bus request control, without need for additional external logic TFL compatible inputs and outputs The CPU can read current Port counters, Byte counter, or Status Register. A mask byte can beset which defines ‘which registers canbe accessed during read operations sv GND o iNT Jet 10 GUSRG BAI BRO ROY BYTEPPOLSE THT PRIORITY Bounres COMPARATOR Coste! aus PRIORITY Tat connor tosic Lanett Suse eee, TNTVEcToR ae eoxrnon TRTERNAT BUS efits REGISTERS FORTASTART ‘COMPRA DATA ‘GOMPAREWASK] | ®USCONTROL Cocie ‘COMPARATOR IURGETDEST ADDRESS MUX POORER MUN) 1 veel oo DMA internai Biock Diagram Fig.1 32Y%, Z-80 DMA Z-80A DMA Zilog DMA Architecture [A block diagram of the 280 DMA is shown in Figure 1 ‘The internal structure consists of the following circultry: ‘© Bus Interface: provides driver and receiver circuitry to Interface to the Z80-CPU Bus. © Consrol Logic and Registers: set the class, mode and other ‘basic control parameters of the DMA. © Address, Byte Count and Pulse Circuitry: generates the proper port addresses for the read and write operations, with provisions for incrementing or decrementing the address. When zero bytes remain fo be handled, the byte count circuitry sets a flag in the status register. Pulse circuitry generates a pulse each time the byte counter lower &bits equal the pulse register. © Timing Circuitry: allows the user to completely specify the read/write timing for each port. © Match Circuitry: holds the match byte and a mask byte which allows for the comparison of only certain bits within the byte. Ifa match is encountered during a Search or Transfer, this circuitry sets a flag in the status register © INT and BUSRO Circuitry: includes @ control regis ter which specifies the conditions under which the DMA, can generate an interrupt; priority encoding logic to select fetween the generation of an INT or BUSRO output under these conditions; and an interrupt vector register for automatic vectoring to the interrupt service routine. (© Status Register: holds current status of DMA. Register Description ‘The following DMA-internal registers are available to the programmer: Control Registers: Write only; 8 bits. Hold DMA control information: such as, when to initiate an interrupt or pulse, What mode or cass of operation to perform, ete. ‘Timing Registers: Write only; 8 bits. Hold read/write timing parameters for the two ports. Interrupt Vector Register: Read/write; 8 bits. Holds the Sit vector that the DMA will put onto the data bus after receiving an IORQ during an interrupt acknowledge se- quence if it is the highest priority device requesting an interrupt. (This register is readable only during interrupt acknowledge cycles.) Block Length Register: Write only; 16 bits. Contains total ‘lock length of data to be searched andjor transferred. Byte Counter: Read only; 16 bits. Counts umber of bytes transferred (or searched). On a Load or Continue the Byte Counter is reset to zero. Thereafter, each byte transfer o- peration increments it until it matches the contents of the Block Length Register, at which time End of Block is set in the status register and operation is suspended if program- med. Also if so programmed the DMA will generate an interrupt, co COMPONENTS Match Register: Write only; 8 bits. Holds the byte for ‘which « match is being sought in Search operations. Mask Register: Write only; 8 bits. Holds the 8-bit mask to determine which bits in the match register are to be ex- amined for a match. Starting Address Registers (Port A and Port B): Write only: 16 bits each. Hold the starting addresses (upper and lower 8 bits) for the two ports involved in Transfer operations. In Search Only operations, only one port address would have to be specified. Only memory starting addresses require ‘both upper and lower 8 bits; I/O ports are generally ad- ‘dressed with only the lower 8 bits, and in this case the ad- ‘dress contained in the register is a generally fixed address. ‘Address Counters (Port A and Port B): Read only; 16 bits ach. These counters are loaded with the contents of the ‘corresponding Starting Address Repisters whenever Search- ‘or Transfers are initiated with 2 Load or Continue. They are incremented, decremented or remain fixed, as pro- grammed. Pulse Control Register: Write only: & bits. The content of this register is continuously compared with the lower eight bits of the byte counter. When they become equal, the INT ‘output is activated. Since this occurs while BUSRO and BUSAK are both active, the CPU does not interpret this as ‘an interrupt request. Instead, the signal is used to commun ieate with a peripheral I/O device. When the Pulse Control Register contains a value n, the first pulse is generated after n+ 1 bytes of search or transfer. The next and all subse- ‘quent pulses oceur at 256-byte intervals. Status Register: Read only; 8 bits. Match, End of Block, Ready Active, Interrupt Pending, and DMA Cycle Occurred bits indicate these functions when set. Modes of Operation ‘The DMA may be programmed for one of four modes of operation. (See Command Register 2B.) ‘© Byte at a time: control is returned to the CPU after each one-byte cycle ‘© Burst: operation continues as long as the DMA’s RDY input is active, indicating that the relevant port is ready. Control returns to the CPU when RDY is inactive or at end of block or a match if so programmed. ‘© Continuous: the entire Search andjor Transfer of a block ‘of data is completed before control is returned to CPU.Y Z-80 DMA _Z-80A DMA Zilog Classes of Operation The DMA has three classes of operation: Transfer only, Search Only and a combined Search-Transfer. (See Com ‘mand Register 1A.) During a Transfer, data is first read from one port and then written to the other port, byte by byte. (The DMA’s two ports are termed Port A and Port B.) The ports may be programmed to be either system main memory or peripher- al 1/0 devices. Thus, a block of data might be written from a peripheral to another; or it might be written from one area in main memory to another; or from a peripheral to main memory. During a Search, datais read only, and compared byte by byte against two DMAinternal registers, one of which con- tains a match byte and the other an optional mask byte which allows only certain bits to be compared. If any byte of searched data matches, a DMA-internal status bit is set; if programmed to do so,the DMA will then suspend operation andor generate an interrupt, The third class of operation is a combined Search- ‘Transfer. In such an operation a block of data is transferred as described above until a match is found; then, as in a Search Only operation, the transfer may be suspended and/ foram interrupt generated, COMPONENTS Addressing ‘The DMA’s addressing of ports is either fixed or sequen- tial, incrementing or deerementng from a starting addres. ‘The length of the operation (number of bytes) is specified by the programmed contents of a block length register. The DMA can address block lengths of up to 64K bytes. During a transfer two separate port addrestes ae generated, one du ing the Read eycle and one during the Write cycle Operating Sequence Once the DMA has been programmed it may be “En- abled” (Command Register 2A or 2D). In the enabled con- dition when Ready goes active the DMA will request the bus by rin low. The CPU will acknowledge this with a BUSACK which will normally be attached to ‘BAL When the DMA receives BAI it will start its program- med operation releasing BUSRO to a “high” state when it is through. Z-80 DMA Pin Description Zl aa ge. ‘Ag—Ais System Address Bus. All sixteen of these pins are used by the DMA to address system main mem- ory or an 10 port (output) Dp-Dy System Data Bus. Commands from the CPU, DMA status and data from memory or peripher als are transferred on these tristate pins (input/ output) 48 Power GND Ground ® System clock (input) 34 MT Machine cycle One signal from CPU (input) TORO Input/Output Request to and from the System Bus (input/output) MREQ — Memory REQuest to the System Bus (input/ output) RD ReaD to and from the System Bus (input/output) wR WRite to and from the System Bus (input/output) CEIWATT Chip Enable; may also be programmed to be WATT during time when BATistow Gnu) BUSRQ BUS ReQuest. Requests contro! of the CPU Address Bus, Data Bus and Status/Control Bus Gnputfoutput, open drain) BAT ——_Bus Acknowledge In. Signals that the system buses have been released for DMA. control (input) BAO —_Bus Acknowledge Out. BAT and BAG form a daisy-chain connection for system-wide prior bus control (output) TNT —_NTerrupt request (output, open drain) TEL Interrupt Enable In (input) IEO Interrupt Enable Out. IEI and IEO form a daisy- ‘chain connection for system-wide priority inter. rupt control (output) RDY —_ReaDY is monitored by the DMA to determine when a peripheral device associated with a DMA port is ready for a read or write operation (input, programmable as active high or low)% Z-80 DMA Z-80A DMA Zilog DMA Command Write Cycle Ilustrated here is the timing associated with a command byte of control byte being written to the DMA which is to bbe loaded into internal registers. Z80 Output instructions satisfy this timing DMA Register Read Cycle ‘This timing is used when a read operation is performed on the DMA to access the contents of the Status Reyister, Address Counter or other readable registers. 280 Input in structions satisfy this timing STD Memory Timing ‘This timing is exactly the same as used by the Z80-CPU to access system main memory, either ina Read or Write operation. The DMA will default to this timing after a power-on reset, or when a Reset or Reset Timing command is written to it; and unless otherwise programmed, will use this timing duringall Transfer or Search operations involving system main memory. During the memory Read portion of ‘transfer cycle, data is latched in the DMA on the negative edge of during Ts and held into the following Write eycle. During the memory Write postion of a transfer cycle, data {held from the previous Read cycle and released at the end of the present cycle. NOTE: The DMA is normally programmed for a 3 T-cycle duration in memory transactions. But WAIT is sampled during the negative transition of T, and if itis low, Tz will be extended another T-cycle, during which WAIT will again be sampled. The duration of a memory transaction eycle may thus be indefinitely extended. STD Peripheral Timing ‘This timing is identical to the Z80-CPU’s Read/Write timing to I/O peripheral devices. The DMA will default to this timing after a power-on reset, or when a Reset or Reset Timing command is written to it; and unless otherwise pro- grammed, will use this timing during all Transfer or Search ‘operations involving I/O peripherals. During the I/O Read of a transfer cycle, data is latched on the negative edge of ® during Ty and is then held into the Write cycle. During an VO Write, data is held from the previous Read cycle until the end of the Write cycle NOTE: If WAIT is low during the negative transition of Tw*. then Tw* will be extended another T-cycle and WAIT will again be sampled. The duration of a peripheral transaction cycle may thusbe indefinitely extended. 35 COMPONENTS DMA Timing Waveforms TS }— | ——_{% Z-80 DMA Z-80A DMA COMPONENTS Zilog DMA Timing Waveforms (contines) Variable Cycle | od ‘The Variable feature of the DMA allows the user to program | | the DMA’s memory o peripheral transaction timing to values different than given above in the standard default diagrams. This permits the designer to tailor his timing to the particular requirements of his system components, and maximizes the data transfer rate while eliminating external signal condition- ing logic. Cycle length can be two to four T-eycles (more if WATT is used). Signal timing can be varied as shown. During atransfr, data willbe latched by the DMA con the clock edge causing the rising edge of RD and will be held on the data lines until the end of the following Write cycle. (See Timing Control Byte, page 7.) too, DMA Bus Request and Acceptance for Byte-at-a-Time, Burst, and Continuous Mode *f Ls ae is found to be active, the folowing tng edge of © senerates BUSRO. After receiving the CPU will grant a BUSAK which will be connected to BAT either directly or through the Bus Acknowledge Daisy Chain When a low is detected on BAI for two consecutive edges of &, the next rising edge of & will start an active DMA cycle. DMA Bus Release at End of Block for Burst or Continuous Mode ‘Timing for End of Block and DMA not programmed for Autosestart. DMA Bus Release with ‘Ready’ for Burst and Continuous Mode al ‘The DMA will relinquish the bus after RDY has gone inactive (Burst mode) or after an End of Block or a Match is found (Continuous mode). With RDY inactive, grag the DMA in Continuous mode is inactive but maintains control of the bus (BUSRQ low) until the cycle is re sumed when RDY goes active 36 na acrive—ela OA yg —mee-DMMA ACTIVE Eee eleYG Z-80 DMA Z-80A DMA COMPONENTS, Zilog DMA Timing Waveforms (continuea) DMA Bus Release for Byte-at-a-Time Mode In the Byte mode the DMA will release BUSRO on the rising edge of ® prior to the end of each Read cy- cle in Search Only or each Write cycle in a Transfer, re sgardless of the state of RDY. The next bus request will ‘come after both BUSRQ and BAI have returned high. DMA Bus Release with Match for Burst or Continuous Modes When a Match is found and the DMA is programmed to stop on Compare, the DMA performs an operation on the next byte and then releases bus. oS Lu mM apy A6t__ m0sm0 ee = a Reading the DMA Internal Registers ‘The CPU can read seven internal DMA registers, always in the following order: Status, lower byte of the Block Length register, upper byte of the Block Length register, Tower byte of the Port A Address, upper byte of the Port A Address, lower byte of the Port B Address and the upper byte of the Port B Adress. ‘The Read Mask register must be programmed to either include or exclude any of these seven registers by program- ming a 1 (include) or 0 (exclude) in the appropriate posi- tions of the Read Mask register. After a Reset or Load, the read sequence must be initiated through an Initiate Read Sequence command (Command Byte 2D). The sequence of reading all registers that are not excluded by the Read Mask register must be completed before new Initiate Read Se- quence or RD Status command. Programming the DMA. Previous sections of this specification have indicated the various functions and modes of the DMA. The diagrams and charts below show how the DMA is programmed to select among these functions and modes and to adapt itself to the requirements of the user system. ‘The Z80-DMA chip may be in an “enable™ state, in which it can gain control of the system buses and direct the trans fer of data between its ports or in a “disable” state, when it cannot gain control of the bus. Program commands can ‘be written to it in either state, but writing a command to it automaticaly putsit in the disable state, which is maintained uuntil an enable command is issued to the DMA. The CPU ‘must program it in advance of any data search or transfer by addressing it as an I/O port and sending it a sequence of command bytes via the system data bus using Output in- structions. When the DMA is powered up or reset by any means, the DMA is automatically placed into a disable state, in which it can initiate neither bus requests nor data ‘transfers nor interrupts. ‘The command bytes contain information to be loaded into the DMA’s control and other registers and/or informa- tion toalter the state of the chip, such as an Enable Interrupt command, The command structure is designed so that cer tain bits in some commands can be set to alert the DMA 10 expect the next byte written to it to be for a particular internal register ‘The following diagrams and charts give the function of each bit in the six different command bytes. Two of these are defined as being from Group 1, and are termed command bytes 1A and IB. These Group 1 commands contain the ‘most basic DMA set-up information. The other four are categorized as Group 2, and are termed commands 2A, 2B, 2C and 2D. Group 2 words specify more detailed set-up information|Yq 7-80 DMA Z-80A DMA COMPONENTS Zilog Command Register 1A oy 6 ps os os oot otter reans that the indicated byte wil fol ey low. Note that the sequence of bytes | sed enonts enon is absolutely rigid. Spon acron The DMA always transfersorsearch- es one byte more than the number tn ‘writen into the Block Length registers. PORT A STARTING ADORESS (LOWER BYTE) Toe ‘A-*0" in the block length register re T SSriee gules in the transfer or search of + 1 bytes. The shortest programmable FORT A STARTING ADORESS {UPPER BYTE block length is therefore two bytes long, programmed by witing a1 into T¥ the Block Length register. LOCK LENGTH LOWER BYTE) v LOCK LENGTH (UPPER BYTE) Command Register 1B Command Register 2A or 06 06 tos oz oso or oe os ot ono ooo ° o| o 1 of T T T i] @b-PorB-tanony =i Ontae 1 Orton 8-0 Some 1 Spm acto spar haus Dares ’ 4 pec aca ie MASK BYTE (= MASK 1ONORE;0= UNMASK ComPanE) 1 ¥ Tei ave cae P Loses ° toute ele tang = FORD enc Cyto Ear (0 MEG Ende Cyle Ey ORD Ende Cyn Ely = WR End yee Early For transfers, this byte is normally written twice, once for Pott A and again for Port B, 38py 7-8) DMA Z-80A DMA COMPONENTS Zilog Command Register 2B a ee ee ee PORT BSTARTING ADDRESS (LOW-ORDER HALF) EE 3 PORT STARTING ADDRESS (HIGHORDER HALF) EI ; | Inxrrp on Match * ie “tnterrupt Before Requesting Bus 1 exarups At Ed OF Back 4s selected (by a Tin Dit 6 of the In- 1 Fuse Generated terrupt Control byte), the 280 DMA 4 Stats Attcts Vector does pot request the bus until the erupt Before Reqs Bus following set of instructions has boon 1 received by the Z-80 DMA: ‘© Enable after RETI command (B7 in Command byte 2D) ee oe = Enable DMA ‘command (87 in T Command byte 2D) © A RETF instruction that resets the TUS (Intezrupt Under Service we | ve} vs} ve | va | ve} vi] vo | « ee ee eee ® Inxerupt On ROY © 3 mut 1 O=End OF Bock 1 Te aibeh End OF Bock Command Register 2C by ps 05 seo A ne ] | \ B= Ready Active Low = CE ony AI CEWAT matte = Stmp On End OF Bick 0% Z-80 DMA Z-80A DMA COMPONENTS Zilog Command Register 2D > Ret ntrup rity, table inerupt and bus request on, unore Internal eady eonatlon ible" MUXCE” ane stp auto rept 1 Load stating dares for both pos cle byte conte.” (0: Reet and able itarupt cuits ike RET! and unore the tert Bot effec operations excep intrrpts ut donot 1 nt ead sequence to the ist regex designated sable bythe (> Fare an sterol ey condo dependent of the ROY input Used formerorytomemoty opaaions where no ROY sal seeded Triscommand dove not function nthe teat time ade 1 Enabe aftr RET! 0 OMA wl eqs tur only afar resting 2 AT! me se oe x eee 2 1 eb 8 a too oo yememecemtamete et eS ae & {oo of CEaReteremsoimns & 48 8) Seem oe S i fo3 fd Semme a Ce one s $i ba sone a $3 8 8 scotia] feign v Se ee ee ® os 0 2 oedatmmnmieaanne 7 ott oekehetttheeee (ee Fas Ma 3 = esta) L— seane Byte Counter ow byte) Byte Counter gh oy) Por A ses on te) Por A aro high be Port ares (ow byt) Port B den (nh ye * Loading Port Addreses The “Load” command (CF in Com ‘mand Register 2D) leads fixed address only into a port selected 5 the source, not into a port selected as the destination. There for, the destination addess must be loaded by temporarily mis. labeling the destination asthe source The following example is a setup procedure fora transfer from Port A to Port B 1. Command byte 1A with Bas source port 2 Command byte 2D with CF ~ load 3. Command byte LA with A as source port ‘4 Command byte 2D with CF = load ‘5. Command byte 2D with 87 = Enable DMA ‘This manipulation is required only when the destination has a fixed address Status Register UA Gye Hae Not Oscar pan oz ooo O~ peasy Aste | dearer 40Y% Z-80 DMA Z-80A DMA COMPONENTS Zilog The Sample DMA Program shows how the DMA may be programmed to transfer data from memory (Port A) to peripheral device (Port B). In this example, the Port A memory starting address is 1050}{ and the Port B peripheral fixed addres is OS}. Note that the data flow is 10014 bytes—one more than specified by the block length. The table of DMA commands may be stored in consecutive memory locations and transferred to the DMA with an output instruction such as OTIR. Figure 1: Sample DMA Program o be a a = le ore | ee 7 1 Por Bate owe ° |e ° ° |e 7 ° pe ‘ine cee | tetmt | nav | neman | nov nottns | oveze ne Wawa | "Sener | peter | “ican Rags 1A Po Ase © ° 2 3 ° 3 ° |e —— ewe No RO ck Legh Bet whe | aha, rte “icamword by 1 eat OHA 7 ° 3 @ ie v pe ae | 41Ui Z-80 DMA Z.-80A DMA COMPONENTS Absolute Maximum Ratings Temperature Under Bias °C to 70°C *Comment ‘Storage Temperature 65°C to #150°C ee eae Stress above those sted under “Absolute -— Maximom Rating may cause permanent ane 1 damage tothe device This a ses ating s nly and functional operation ofthe device At ihese or any other condition above those indicated in the operational sections ofthis Speciation is not implied, Exposure to AByolute maximum rating conditions for extended periods may affect device eibtiy D.C. Characteristics oe et rene ac es oroene ve |e ape an vow 2 [es |e ealonccanen eal nase oo 1 | aes, Ton oon va [= alee oom Te [peeves Eee] | wp ma ete ail eo ea ceis ef a [sara Capacitance Tq=28F= 1 we Syntot_ | __ Panne vox [_van [| TetCondtion Ce] Sick capctunce 38 | oF] mens Fins sn | Tapatopectanee [5 | pF] Retued to Ground Cour | Output Cpcinee TO] 9 CL_=50 pF. Increase delay by 10 ns for each SO pF increase in CL, up to 200 pF maximum, 42Y% Z-80 DMA_Z-80A DMA COMPONENTS Zilog A.C. Timing Diagrams 80 and Z80A asa Peripheral Device (Inactive State) “ising measurements dt th following volar, le otherwise pein “er ourrur 20v av nur ov ogy 1 2 T3Tw Ta/T3 1 3 al FS al Fe 3 a tel |-——+ «19 —+| ele tonttor | tortor J «1p (17) int CONDITION NOTE: This diagram does not show an actual timing sequence. Refer to this diagram only for the detailed timing relationships of individual edges. Use the illustrations in the “DMA Timing Waveforms” section as an explanation of the various timing sequences. BY% Z-80 DMA Z-80A DMA COMPONENTS Zilog A.C. Characteristics Z80-DMA as a Peripheral Device (Inactive State). Ta =0°C to 70°C, Vee = +5V45%, Unless Otherwise Noted . ex Pood 0 1 20 nl ae Gan | seco 7 = v= fai ‘sio) “ 0 « ‘oH! ut ay en aig Et xo 0 my Teun) Su Tra aig Er HORE ee TA Ce 1 ww Toney) (60 naytne nom Rng cag ott 1 ae | 0 {Bley | teobay tam eg Eat of ere Oar | is | te we Toon) Sue ns oy Sago rng TAT He =| = te sehen | % Twornor | FBS Tine te Rava ra Ovo 20 5 ey ‘ein TR By Tig or Sno ang TT Ey |e [om UES) | Reo Bey to row ce | Fy foo | Moe * Z-80A DMA Timing Specifications are preliminary.% Z-80 DMA Z-80A DMA Zilog 280-DMA as a Bus Controller (Active State) Ty =0°C to 70°C, Veo = +5V45%, Unless Otherwise Noted. COMPONENTS A.C. Characteristics won| | Beocemecanes, | gg = = |S Eeey Seow = & | ESEEESRER sais = wor | te . = =a 3 = on | See 3 7 Se | Swe 5 7 oe [ES Slee = ee eet Tel 3 = m= | St | eee ae 3 = Se | BS Seeie a 8 = See | BRE eae 2 Ss mate | Barmera im rm = » | Se 3 = sas 2 o | SS RR 2 aoe | RR areca 7 Saar | SNe = ee = = we [bemoan a = = ores "© Data must be enabled onto the DMA data bus when RD is active. = All equations imply standard 2-80 CPU and Z:80A CPU timing. ‘© Z.80A DMA timing specifications are preliminary. 4s% Z-80 DMA _Z-80A DMA COMPONENTS Zilog A.C. Timing Diagrams 780 and Z80A asa Bus Controller (Activ State) Tumgmassuramonte ae made te fllowing ota, anes otarwi spect + ‘This diagram does not show an actual timing sequence. Refer to this diagram only for the detailing timing relationships of individual edges.Wp 7-85 DMA Z-80A DMA COMPONENTS Zilog Package Outline 40-Pin Ceramic Ordering Information Examples 7-80 DMA CS (ceramic package, standard range) 7-80 DMA PS (plastic package, standard range) © — Ceramic Package P — Plastic Package S_ — Standard Range (SV, +5%, 0°C to 70°C) E — Extended Range (SV, 45%, —40°C to 85°C) M — Military Range (SV, 10%, ~55°C to 125°C) a7Va COMPONENTS Zilog Product Specification General Description ‘The Z80-SIO (Serial Input/Output) is a dual-channel multi-function peripheral component designed to satisfy a wide variety of serial data communicati ments in microcomputer systems. Its basic function is a serial-to-paralle, parallel-to-serial converter/controller, but—within that role—it is configurable by systems software so its “personality” can be optimized for a ‘given serial data communications application. ‘The Z80-SIO is capable of handling asynchronous formats, synchronous byte-oriented protocols such as iw Bisync, and synchronous bit-oriented protocols ssuch as HDLC and SDLC. This versatile device can also be used to support virtually any other serial protocol for applications other than data communications (cassette or floppy disk interfaces, for example). ‘The Z80-SIO can generate and check CRC codes in any synchronous mode and can be programmed to ccheck data integrity in various modes. The device also has facilities for modem controls in both channels. In applications where these controls are not needed, the ‘modem controls can be used for general-purpose 1/0. Z-80 SIO Z-80A SIO Structure ‘@ N-channel silicon-gate depletion-load technology = 40-pin DIP le 5 V power supply m Single-phase 5 V clock @ All inputs and outputs TTL compatible Features = Two independent full-duplex channels = Data rates © 0-S00K clock rate ‘© 0-800K bits/second with 4.0 MHz system lock rate 1 Receiver data registers quadruply buffered; trans- mitter doubly buffered @ Asynchronous features: © 5,6, 7 or 8 bits/character synchronous or isosynchronous modes: its/second with 2.5 MHz system faalae =a || ae as Wy CA Oe Th ae Figure 1. Z80-S10 Block Diagram 48COMPONENTS % 7-80 SIO Z-80A SIO Zilog Z-80 SIO Pin Description 1, 14 or 2 stop bits Even, odd or no parity x1, x16, x32 and x64 clock modes Break generation and detection Parity, overrun and framing error detection ‘Binary synchronous features: ‘© Internal or external character synchronization ‘© One or two syne characters in separate registers ‘© Automatic syne character insertion/deletion ‘* crc generation and checking HDLC and spL¢ features: ‘© Abort sequence generation and detection ‘© Automatic zero insertion and deletion ‘* Automatic flag insertion between messages # Address field recognition © Support for one to eight bits/character © Valid receive messages protected from overrun ‘© crc generation and checking Interrupt features: ‘© Daisy-chain interrupt logic provides automatic interrupt vectoring with no external logic © Programmable interrupt vector « Status Affects Interrupt Vector mode for fast interrupt processing. 1 CRC-16 oF CRC-CCITT block frame check 1m Separate modem control inputs and outputs for both channels Modem status can be monitored Pin Description Do-Dy. System Data Bus (bidirectional, 3-state). The system data bus transfers data and commands between the CPU and the Z80-SIO. Dp is the least significant bit. B/A. Channel A Or B Select (input, High selects Chan- nel B). This input defines which channel is accessed during a data transfer between the CPU and the 780-SIO. Address bit Ao from the CPU is often used for the selection function. CAB. Control Or Data Select (input, High selects Con- trol). This input defines the type of information trans- fer performed between the CPU and the Z80-SIO. A High at this input during a CPU write to the Z80-SIO causes the information on the data bus to be interpreted as acommand for the channel selected by B/A. A Low at c/B means that the information on the data bus is data. ‘Address bit Ay is often used for this function. EE. Chip Enable (input, active Low). A Low level at this input enables the Z80-SIO to accept command or data input from the CPU during a write cycle, or to transmit data to the CPU during a read cycle. 4. System Clock (input). The Z80-SIO uses the stand- ard Z80 System Clock to synchronize internal signals. This is a single-phase clock. MI. Machine Cycle One (input from Z80-CPU, active Low). When Mi is active and RD is also active, the 280-CPU is fetching an instruction from memory; when Mis active while ORO is active, the Z80-SIO accepts Mi Be i¢ Figure 2. Z80-SI0/0 Pin Configuration 49 meson% Z-80 SIO Z-80A SIO Zilog and TORG as an interrupt acknowledge if the Z80-SIO is the highest priority device that has interrupted the Z80-CPU. TORQ. Input/Output Request (input from CPU, act Low). TORQ is used in conjunction with B/&, c/D, TE and RD to transfer commands and data between the CPU and the Z80-SIO. When TE, RD and {ORG are all active, the channel selected by 8/ transfers data to the CPU read operation). When CE and fORQ are active, but RD is inactive, the channel selected by B/A is written to by the (CPU with either data or control information as specified by c/D. As mentioned previously, if (ORQ and Mi are ac- tive simultaneously, the CPU is acknowledging an inter- rupt and the Z80-SiO automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. RD._Read Cycle Status. (input from cPU, active Low). If RD is active, a memory or V0 read operation is in progress. RD is used with B/A, CE and TORG to transfer data from the Z80-SIO to the CPU. RESET. Reset (input, active Low). A Low RESET di ables both receivers and transmitters, forces TxDA and ‘TxpB marking, forces the modem controls High and dis ables all interrupts. The control registers must be re- written after the Z80-SIO is reset and before data is transmitted or received, TEI. Interrupt Enable In (input, active High). This sig- nal is used with 1E0 to form a priority daisy chain when there is more than one interrupt-driven device. A High COMPONENTS Z-80 SIO Pin Description on this line indicates that no other device of higher pri rity is being serviced by a CPU interrupt service routine. HEO. Interrupt Enable Out (output, active High). 10 is High only if te is High and the cPU is not servicing an interrupt from this Z80-SIO. Thus, this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt ser- vvice routine. INT. Interrupt Request (output, open drain, active Low). When the 280-SIO is requesting an interrupt, it pulls INT Low. WARDYA, WIRDYB. Wait/Ready A, Wait/Ready B (outputs, open drain when programmed for Wait func- tion, driven High and Low when programmed for Ready function). These dual-purpose outputs may be programmed as Ready lines for a DMA controller or as Wait lines that synchronize the CPU to the Z80-SIO data rate. The reset state is open drain. (CTSA, CTSB. Clear To Send (inputs, active Low). When ‘programmed as Auto Enables, 2 Low on these inputs enables the respective transmitter. If not pro- grammed as Auto Enables, these inputs may be pro- grammed as general-purpose inputs. Both inputs are Schmitt-rigger buffered to accommodate slow-risetime signals. The Z80-SIO detects pulses on these inputs and interrupts the CPU on both logic level transitions. The Schmit-trigger buffering does not guarantee a specified noise-level margin, KOR ] ba | ‘780-S10/1 Pin Configuration so Figure 4, 280-S10/2 Pin ConfigurationY% Z-80 SIO Z-80A SIO COMPONENTS Zilog DODA, DEDB. Data Carrier Detect (inputs, act Low). These pins function as receiver enables if the Z80-SIO is programmed for Auto Enables; otherwise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow- risetime signals. The Z80-SIO detects pulses on these pins and interrupts the CPU on both logic level transi- tions, Schmitt-trigger buffering does not guarantee a specific noise level margin. RxDA, RxDB. Receive Data (inputs, active High). TxDA, TxDB. Transmit Data (outputs, active High). RxCA, RXCB. Receiver Clocks (inputs). Receive data is sampled on the rising edge of Rxc. The Receive Clocks may be 1, 16, 32 or 64 times the data rate in Asyn- cchronous modes. These clocks may be driven by the Z80-CTC Counter Timer Circuit for programmable ‘baud rate generation. Both inputs are Schmitt-trigger buffered (no noise level margin is specified). See the following section for bonding options. TRCA, TACB. Transmitter Clocks (inputs). TD changes on the falling edge of TxC. In Asynchronous modes, the Transmitter Clocks may be 1, 16, 32 or 64 times the data rate; however, the clock multiplier for the transmitter and the receiver must be the same. The ‘Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements (no noise level margin is specified). Transmitter Clocks may be driven by the Z80-CTC Counter Timer Circuit for program- ‘mable baud rate generation. See the following section for bonding options. RIGA, RISB. Request To Send (outputs, active Low). When the RTS bit is set, the RTS output goes Low. When. the RTS bit is reset in the Asynchronous mode, the out- put goes High after the transmitter is empty. In Syn- chronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs, DTRA, DTRB. Data Terminal Ready (outputs, active Low). See note on bonding options. These outputs fol- low the state programmed into the DTR bit. They can also be programmed as general-purpose outputs. SYNC A, SYNC B. Synchronization (inputs/outputs, active Low). These pins can act either as inputs or out- puts. In the Asynchronous Receive mode, they are in- puts similar to CTS and DCD. In this mode, the transi tions on these lines affect-the state of the Sync/Hunt status bits in RRo. In the External Sync mode, these lines also act as inputs. When external synchronization is achieved, SNC must be driven Low on the second rising. ‘edge of FC after that rising edge of RxC on which the last bit of the sync character was received. In other words, after the sync pattern is detected, the external logic must wait for two full Receive Clock eycles to acti- SI Z-80 SIO Bonding Options vate the SYNC input. Once SYNC is forced Low, itis wise to keep it Low until the CPU informs the external syne logic that synchronization has been lost or a new mes- sage is about to start. Character assembly begins on the rising edge of &xC that immediately precedes the falling edge of SYNC in the External Syne mode. In the Internal Synchronization mode (Monosyne and Bisyne), these pins act as outputs that are active during the part of the receive clock (x6) cycle in which syne characters are recognized. The syne condition is not latched, so these outputs are active each time a syne pattern is recognized, regardless of character bounda- ries. Bonding Options ‘The constraints of a 40-pin package make it impossible to bring out the Receive Clock, Transmit Clock, Data Terminal Ready and Syne signals for both channels. Therefore, Channel B must sacrifice a signal or have two signals bonded together. Since user requirements vary, three bonding options are offered: ‘ Z80-S10/0 has all four signals, but TCE and KCB are bonded together (Fig. 2). © Z80-SIO/I sacrifices DTRE and keeps TCH, HCE and SYNCH (Fig. 3). ‘© 280-S1O/2 sacrifices SYNCE and keeps TB, HCH ‘and DTRB (Fig. 4). Architecture ‘The device internal structure includes a Z80-CPU inter- face, internal control and interrupt logic, and two full- duplex channels. Each channel contains read and write registers, and discrete control and status logic that pro- vides the interface to modems or other external devices. ‘The read and write register group includes five 8-bit control registers, two syne-character registers and two status registers. The interrupt vector is written into an additional 8-bit register (Write Register 2) in Channel B that may be read through Read Register 2 in Channel B. ‘The registers for both channels are designated in the text as follows: WRO-WR7 — Write Registers 0 through 7 RRO-RR2 — Read Registers 0 through 2 ‘The bit assignment and functional grouping of each register is configured to simplify and organize the pro- gramming process. Table 1 lists the functions assigned to each read or write register. ro bulfor status, interrupt status and RI Special Receive Condition status RR2_ Moai omY% Z-80 SIO Z-80A SIO Zilog wrt Wr contra ‘or SDLG address Held (or SOLG fag Write Register Functions ‘Table 1. Functional Assignments of Read and Write Registers COMPONENTS Z-80 SIO Architecture The logic for both channels provides formats, syn- chronization and validation for data transferred to and from the channel interface. The modem control inputs Clear to Send (C73) and Data Carrier Detect (OCD) are monitored by the discrete control logic under program control. All the modem control signals are general pur- pose in nature and can be used for functions other than modem control. For automatic interrupt vectoring, the interrupt con- trol logic determines which channel and which device within the channel has the highest priority. Priority is fixed with Channel A assigned a higher priority than Channel B; Receive, Transmit and External/Status in- terrupts are prioritized in that order within each chan- nel. U LU : in 4 | Ll Ll a i ae i 7 tt syne oof jee. | L oe (Excor | Figure 5, Transmit and Receive Data Path 52Ui Z-80 SIO Z-80A SIO COMPONENTS Data nee th “The transmit and receive data path illustrated for Chan- nel A in Figure 5 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO ar- rangement in addition to the 8-bit receive shift register This scheme creates additional time for the CPU to ser- vice an interrupt at the beginning of a block of high- speed data. Incoming data is routed through one of several paths (data or CRc) depending on the selected mode and—in Asynchronous modes—the character length, ‘The transmitter has an 8-bit transmit data register that is loaded from the internal data bus, and a 20-bit transmit shift register that can be loaded from the syne character buffers (wR6 and WR7) or from the transmit data register. Depending on the operational mode, out- ‘going data is routed through one of four main paths before it is transmitted from the Transmit Data Output (xD). Functional Description ‘The functional capabilities of the Z80-SIO can be described from two different points of view: as a data ‘communications device, it transmits and receives serial data, and meets the requirements of various data com- munications protocols; as a Z80 family peripheral, it interacts with the Z80-CPU and other Z80 peripheral circuits, and shares the data, address and control busses, as well as being a part of the Z80 interrupt struc- ture, As a peripheral to other microprocessors, the 80-SIO offers valuable features such as non-vectored interrupts, polling and simple handshake capability. ‘The first part of the following functional description describes the interaction between the CPU and Z80-SI( the second part introduces its data communications capabilities. 1/0 Interface Capabilities ‘The Z80-S1O offers the choice of Polling, Interrupt (vectored or non-vectored) and Block Transfer modes to transfer data, status and control information to and from the CPU. The Block Transfer mode can be im- plemented under CPU or DMA control. Polling, There are no interrupts in the Polled mode. Status registers RRO and RRI are updated at appropriate times for each function being performed (for example, RC Error status valid at the end of the message). All the interrupt modes of the Z80-SIO must be disabled to ‘operate the device in a polled environment. While in its Polling sequence, the cPU examines the status contained in RRo for each channel; the RRO status bits serve as an acknowledge to the Poll inquiry. The ‘two RRO status bits Dp and D2 indicate that a data transfer is needed. The status also indicates Error or ‘other special status conditions (see “Z80-SIO Program- ming”). The Special Receive Condition status contained 53 Z-80 SIO Architecture in RR1 does not have to be read in a Polling sequence because the status bits in RRI must be accompanied by a Receive Character Available status in RRO. Interrupts. The Z80-SIO offers an elaborate interrupt scheme to provide fast interrupt response in real-time applications. Channel B registers WR2 and RR2 contain the interrupt vector that points to an interrupt service routine in the memory. To service operations in both channels and to eliminate the necessity of writing a status analysis routine, the Z80-SIO can modify the terrupt vector in RR2 so it points directly to one of eight interrupt service routines. This is done under program control by setting a program bit (WRI, D3) in Channel B called “Status Affects Vector.”” When this bit is set, the interrupt vector in WR2 is modified according to the assigned priority of the various interrupting conditions. ‘The table in the Write Register 1 description (Z80-SIO Programming section) shows the modification details. ‘Transmit interrupts, Receive interrupts and External/ Status interrupts are ‘the main sources of interrupts. Each interrupt source is enabled under program control with Channel A having a higher priority than Channel B, and with Receiver, Transmit and External/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so it can become empty.) When enabled, the receiver can interrupt the CPU in one of three ways: ‘= Interrupt on the first received character ‘© Interrupt on all received characters ‘* Interrupt on a Special Receive condition Interrupt On First Character is typically used with the Block Transfer mode, Interrupt On All Receive Char ters has the option of modifying the interrupt vector in the event of a parity error. The Special Receive Con tion interrupt can occur on a character or message basis, (End Of Frame interrupt in sDLC, for example). The Special Receive condition can cause an interrupt only if, the Interrupt On First Receive Character or Interrupt (On All Receive Characters mode is selected. In Interrupt (On First Receive Character, an interrupt can occur from conditions (except Parity Error) after the first receive character interrupt (example: Receive Overrun interrupt). ‘The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD and ‘SYNC pins; however, an External/Status interrupt is also ‘caused by a Transmit Underrun condition or by the detection of a Break (Asynchronous mode) or Abort (SDLC mode) sequence in the data stream. The interrupt ‘caused by the Break/Abort sequence has a special fea- ture that allows the Z80-SIO to interrupt when the Break/Abort sequence is detected or terminated. This, feature facilitates the proper termination of the current message, correct initialization of the next message, andVa Z-80 SIO Z-80A SIO Zilog the accurate timing of the Break/Abort condition in ex- ternal logic. CPU/DMA Block Transfer. The Z80-SIO provides a Block Transfer mode to accommodate CPU block trans- fer functions and DMA controllers (Z80-DMA or other designs). The Block Transfer mode uses the WATT/ READY output in conjunction with the Wait/Ready bits of Write Register 1. The WAFT/READY output can be defined under software control as Block Transfer mode or as a READY line in the DMA Block Transfer mode. To a DMA controller, the Z80-SIO READY output in- dicates that the Z80-SIO is ready to transfer data to or from memory. To the CPU, the WAIT output indicates that the Z80-SIO is not ready to transfer data, thereby requesting the CPU to extend the 1/0 cycle. The pro- gramming of bits 5, 6 and 7 of Write Register 1 and the logic states of the WATT7READY line are defined in the Write Register 1 description (Z80-SIO Programming section). Data Communications Capabilities In addition to the 1/0 capabilites previously discussed, the Z80-SIO provides two independent full-duplex channels that can be programmed for use in Asynchro- nous, Synchronous and SDLC (HDLC) modes. These di ferent modes are provided to facilitate the implementa tion of commonly used data communications protocols. The following is a short description of the data com- munications protocols supported by the Z80-SIO. A ‘more detailed explanation of these modes can be found in the 280-510 Technical Manual. Asynchronous Modes. The Z80-SIO offers transmission and reception of five to eight bits per character, plus op- tional even or odd parity. The transmitter can supply fone, one and a half or two stop bits per character and can provide a break output at any time. The receiver break detection logic interrupts the CPU only at the start, and end of a received break. Reception is protected from spikes by a transient spike rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the Receive Data input. If the Low does not persist—as in the case of a transient—the char- acter assembly process is not started. Framing errors and overrun errors are detected and. buffered together with the partial character on which they occurred. Vectored interrupts allow fast servicing of error conditions using dedicated routines. Further more, a built-in checking process avoids interpreting a framing error as a new start bit: a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit is begun. The Z80-SIO does not require symmetric Transmit and Receive Clock signals—a feature that allows it to be used with a Z80-CTC or any other clock source. The transmitter and receiver can handle data at a rate of 1, 1/16, 1/32 or 1/64 of the clock rate supplied to the Receive and Transmit Clock inputs. COMPONENTS Functional Description In Asynchronous modes, the SNC pin may be pro- ‘grammed for an input that can be used for functions such as monitoring a ring indicator. Synchronous Modes. The Z80-SIO supports both byte- oriented and bit-oriented synchronous communication. Synchronous byte-oriented protocols can be handled in several modes that allow character synchronization with an8-bit syne character (Monosync), any 16-bit syne pat tern (Bisyne), or with an external sync signal. Leading sync characters can be removed without interrupting the for synchronous. byte-oriented modes is delayed by one character time so the CPU may disable CRC checking on specific characters. This per- mits implementation of protocols such as 18M Bisync. Both crc-ié (X16+XI5+X241) and cciTT (X64 X12+X5+ I) error checking polynomials are sup- ported. In all non-SDLC modes, the CRC generator is in- itialized to O's; in sDLC modes, it is initialized to I's. (This means that the Z80-SIO cannot generate or check crc for 1BM-compatible soft-sectored disks.) The Z80-SIO also provides a feature that automatically transmits CRC data when no other data is available for transmission. This allows very high-speed transmissions under DMA control with no need for CPU intervention at the end of a message. When there is no data or CRC to send in Synchronous modes, the transmitter inserts 8- or 16-bit sync characters regardless of the programmed character length. Since the CPU can read status informa tion from the Z80-SIO, it can determine the type of transmission (data, CRC or syne characters) that is tak- ing place at any time. ‘The Z80-SIO supports synchronous bit-oriented pro- tocols such as SDLC and HDLC by performing automatic flag sending, zero insertion and CRC generation. A spe- cial command can be used to abort a frame in transmis- sion. The Z80-SIO automatically transmits the CRC and trailing flag when the transmit buffer becomes empty. ‘An interrupt warns the CPU of this status change so an abort may be issued if a transmitter underrun has oc- curred. One to eight bits per character can be sent, which allows transmission of a message exactly as received with no prior information about the character structure in the information field of a frame. ‘The receiver automatically synchronizes on the lead- ing flag of a frame and provides a synchronization sig- nal that can be programmed to interrupt. In addition, an interrupt on the first received character or on every character can be selected. The receiver automatically deletes all zeroes inserted by the transmitter during char- acter assembly. It also calculates and automatically checks the CRC to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. The receiver can be pro- ‘grammed to search for frames addressed to only a speci- fied user-selectable address or to a global broadcast ad- dress. In this mode, frames that do not match the user-YG Z-80 SIO Z-80A SIO Zilog sls or broadcast eres are ignored, The Adres Search mode provise fora singe ye ads recor nizable by the hardware. The number of address bytes ccan be extended under software control. ‘The Z80-SIO can be conveniently used under DMA, control to provide high-speed reception. The Z80-SIO ‘can interrupt the CPU when the first character of a mes- sage is received. The CPU then enables the DMA to trans- fer the message to memory. The Z80-SIO then issues an End Of Frame interrupt and the CPU checks the status of the received message. Thus, the CPU is freed for other service while the message is being received. A similar scheme allows message transmission under DMA con- trol. 780-SIO Programming To program the Z80-SIO, the system program first issues a series of commands that initialize the basi ‘mode of operation and then other commands that qual- ify conditions within the selected mode. For example, the Asynchronous mode, character length, clock rate, number of stop bits, even or odd party are first set, then the interrupt ‘mode and, finally, receiver or transmitter enable, The WRs parameters must be issued before any other parameters are issued in the intializa- tion routine, Both channels contain command registers that must be programmed via the system program prior to opera- tion, The Channel Select input (B/A) and the Control/ Data input (c/D) are the command structure addressing controls, and are normally controlled by the CPU ad- ‘dress bus. Figure & illustrates the timing relationships for programming the write registers, and transferring data and status. Write Registers ‘The Z80-SIO contains eight registers (wRo-WR7) in each channel that are programmed separately by the system program to configure the functional personality of the channels. With the exception of WRo, programming the write registers requires two bytes. The first byte contains three bits (Dy-D>) that point to the selected register; the second byte is the actual control word that is written into the register to configure the Z80-SIO. wro is a special case in that all the basic com- mands (CMDp-CMb2) can be accessed with a single byte. Reset (internal or external) initializes the pointer bits Dp-D2 (0 point to WRo. Read Registers ‘The Z80-SIO contains three registers, RRO-RR2 (Figure 6), that can be read to obtain the status information for ‘each channel (except for RRX — Channel B only). The COMPONENTS Z-80 SIO Programming status information includes error conditions, interrupt vector and standard communications-interface signals. To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRo in exactly the same way as a write register operation. Then, by ex- ecuting an input instruction, the contents of the addressed read register can be read by the CPU. ‘The status bits of RRO and RRI are carefully grouped to simplify status monitoring. For exam- ple, when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the appropriate error bits can be read from a single register (RR, ‘READ REGISTER 0 fe | | ee | —frecany Doo) wrt hose pas ars sedi iathaes 3 : | | | a | ‘ | pay amon fe ORRIN enon oraaws ROR Li ora 5) * peso oara on cut RESREARAETEs Peocrunnco usc wr SecA RecN ConaON MODE ‘READ REGISTER *. i "eR Soe Figure 6. Read Register Bit Funct%Y% Z-80 SIO Z-80A SIO COMPONENTS Zilog Z-80 SIO Programming WRITE REGISTER 0 WRITE REGISTER 4 a 2 gu cone $f MBA cae 1b RST ae ceeaton 12 Rr Godino aren WRITE REGISTER 1 WRITE REGISTER 5 or 16. aT 85, ae [oe) (or Los [os [oe | os [02 [or T 00) | | rrr ae ] | | re | Fee ne | Pi) LL ae i} 4 J Se } | |i Fg) nem geuspeusenn (fo Tee pteemmcrer (yD Tee = : WRITE REGISTER 6 WRITE REGISTER 2 (CHANNEL B ONLY) irs [os [oe] 03 [02] ot [ 00 CATS reT eee) | Pry tte Le = aso Sou ADDRES FLO - (WRITE REGISTER 3 (WRITE REGISTER 7 oe > feta bute fe § arscunacren Hsien 1d) Regrscaamacres fn so.c must o¢paognanen 9 RERISEMMGTER Saari" FORA AECDOMTION Figure 7. Write Register Bit Functions 56Z-80 SIO Z-80A SIO COMPONENTS Zilog Z-80 SIO Timing Timing Read Cycle, The timing signals generated by a Write Cycle. Figure 8b illustrates the timing and data Z80-CPU input instruction to read a Data orStatus byte signals generated by a Z80-CPU output instruction to from the 280-SIO are illustrated in Figure 8a. write a Data or Control byte into the Z80-SIO. yh = 3 y y nh iw 3 th ’ eee 4 fl l @ ‘Gwanwet aooness & =X] canner aooness YX ® cy ei co om Soe eee reece eae Figure Ba, Read Cycle Figure ab, Waite Cycle Interrupt Acknowledge Cycle. After receiving an Return From Interrupt Cycle. Normally, the Interrupt Request signal (INT pulled Low), the Z80-CPU issues a RET! (RETurn from interrupt) in- Z80-CPU_sends an Interrupt Acknowledge signal struction at the end of an interrupt service routine. (i and TOR both Low). The daisy-chained inter- RET is @ 2-byte opcode (D-4D) that resets the rupt circuits determine the highest priority inter- interrupt-under-service latch to terminate the in- rupt requestor. The 161 of the highest priority terrupt that has just been processed. This is ac- peripheral is terminated High. For any peripheral complished by manipulating the daisy chain in the that has mo interrupt pending or under service, following way. 1g0=1eI. Any peripheral that does have an interrupt pending or under service forces its 1EO Low. The normal daisy chain operation can be used t0 detect a pending interrupt; however, it cannot distin- To insure stable conditions in the daisy chai ‘guish between an interrupt under service and a pending all interrupt status signals are prevented from unacknowledged interrupt of a higher priority. When- changing while Mi is Low. When ORO is Low, the ever “ED" is decoded, the daisy chain is modified by highest priority interrupt requestor (the one ‘with forcing High the IE0 of any interrupt that has not yet 161 High) places its interrupt vector on the data bus been acknowledged. Thus the daisy chain identifies the and sets its internal interrupt-under-service latch device presently under service as the only one with an 1E1, Figure 8c. Interrupt Acknowledge Cycle Figure 8d. Return from Interrupt Cycle 57COMPONENTS Y% Z-80 SIO Z-80A SIO Zilog Z-80 SIO Timing High and an 160 Low. If the next opcode byte is the interrupt-under-service latch is reset. ‘The ripple time of the interrupt daisy chain (both the High-to-Low and the Low-to-High transitions) limits the number of devices that can be placed in the daisy chain. Ripple time can be improved with carry-look- ahead, or by extending the interrupt acknowledge cycle. For further information about techniques for inereasing the number of daisy-chained devices, refer to Zilog Application Note 03-0041-01 (The Z80 Family Program Interrupt Structure). Daisy Chain Interrupt Nesting Figure 9 illustrates the daisy chain configuration of interrupt circuits and their behavior with nested inter- rupts (an interrupt that is interrupted by another with a higher priority). Each box in the illustration could be a separate exter- nal Z80 peripheral circuit with a user-defined order of interrupt priorities. However, a similar daisy chain structure also exists inside the Z80-SIO, which has six interrupt levels with a fixed order of priorities. ‘The case illustrated occurs when the transmitter of Channel B interrupts and is granted service. While this interrupt is being serviced, it is interrupted by a higher priority interrupt from Channel A. The second interrupt is serviced and—upon completion—a RET instruct executed or a RET! command is written Z80-SIO, resetting the interrupt-under-service latch of the Channel A interrupt. At this time, the service rotine for Channel B is resumed. When’it is completed, another RET! instruction is executed to complete the in- terrupt service. 1. PRIORITY INTERRUPT DAISY CHAIN ‘BEFORE ANY INTERRUPT OCCURS. 2, CHANNEL B TRANSMITTER INTERRUPTS AND, Is ACKNOWLEDGED. ‘TRANSMITTER. 3. EXTERNALISTATUS OF CHANNEL A INTERRUPTS SUSPENDING SERVICE OF CHANNEL @ ‘TRANSMITTER SERVICE RESUMED. 4. CHANNEL A EXTERNAL/STATUS ROUTINE COMPLETE. RETI ISSUED, CHANNEL B 5, CHANNEL B TRANSMITTER SERVICE ROUTINE COMPLETE, SECOND RET! ISSUED. Figure 9. Typlel Interrupt Sequence 58i Z-80 SIO Z-80A SIO COMPONENTS Electrical Characteristics AC Characteristics Ta=0°C, Voc= +5V, 5% ett . | Slee : ‘ : | ei ‘Wi6S) Com Sp Say Tne wnat = = Saeeg ato en Sen Si Beene ta mga are Ey ae an SEES oer eocenssce: 0 » * 101 ___Gemynreei ee nt re = 0 = ‘W)——Se Tw weg a D ~~ 7 ence SO Oe Tema ea v= = Skee neo en = om MC Seip irene atngne at omeg NTA 0 ” = cee ® IO) A See te ora oe ry = oor Figure 9. Typical Interrupt Sequence 59Ch Z-80 SIO Z-80A SIO COMPONENTS Electrical Characteristics AC Characteristics jw 5a rt =n —e of =r 2 = - cl S ee as TS ne SERC input nt nt ee on compen al hye te a i phere St symet Penner Meee ear = um oy eo a SH RENgberiwimamaiewE TT Am Slot Senn YeKTRe une) ging a _.. s ASS Ry eer a nea cen ot annem Re trimer ars ra, — Ye, Sect ac nae PF ae Cdr cnmcnctocccmieeseede 60Y, Z-80 SIO Z-80A SIO Zilog Electrical Characteristics COMPONENTS: ‘AC Characteristics n | ma fr ween ol ete ol pen aman 7 : =e torreon etre 4 “oo a Gat Woo Tow meno ooeeesnen 0) ETRE nen RG a 00 an) HERB tetanic ” oo TATE rom ADDI iotooraain RE 1 me iuesncy lr nou BERET Tmetonomerstimmt 5858 Ses ewes BAITRERDY buy to arg pe 1 mm Warnesor (on naoyiase DC Characteristics '=0°C to 70°C, Voc= +5V, +5% gh vote 6 fa mensYh Z-80 SIO Z-80A SIO COMPONENTS Package Information |~% eeeeuetees ueeeataeas Package Outlines a% Z-80 SIO_Z-80A SIO COMPONENTS Zilog Ordering Information Bonding, Package and Temperature Identification 0 — Type 0 Bonding Examples: “A — Type 1 Bonding /2 — Type 2 Bonding Z80-SIO/1 CS (Type 1 bonding, ceramic package, standard range) © — Ceramic Package i aaa Cries ae PS (Type 2 bonding, plastic package, standard SS — Standard Range (SV, +5%, 0°C to 70°C) E — Extended Range (SV, #5%, ~40°C to 85°C) M — Military Range (SV, + 10%, ~55°C to 125°C) rtVs COMPONENTS Zilog Product Specification General Description ‘The 280-S1O (Serial Input/Output) is a single-channel ‘multi-function peripheral component designed to satisfy a wide variety of serial data communications require- ments in microcomputer systems. Its basic function is a serial-to-parallel, parallel-to-serial converter/controller, bbut—within that role—it is configurable by systems software so its “personality” can be optimized for a given serial data communications application. The Z80-SI0 is capable of handling asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and SDLC. This versatile device can also be used to support virtually any other serial protocol for applications other than data communications (cassette or floppy disk interfaces, for example). ‘The Z80-SIO can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The device also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose 1/0. Z-80 SIO/9 Z-80A SIO/9 Structure N-channel silicon-gate depletion-load technology 40-pin DIP Single SV power supply Single-phase SV clock All inputs and outputs TTL compatible Features ‘= One full-duplex channel = Data rates in synchronous or isosynchronous modes: ‘© 0-SO0K bits/second with 2.5 MHz system clock rate © 0-800K bits/second with 4.0 MHz system clock rate = Receiver data registers quadruply buffered; trans- mitter doubly buffered. = Asynchronous features: © 5,6, 7 o 8 bits/character © 1, 1% or 2 stop bits ¢ Even, odd or no parity ed manne enmsner c1oens — swe 7-80 SIO/9 BLOCK DIAGRAM IM 64Y% Z-80°SIO/9 Z-80A SIO/9 COMPONENTS Zilog © x1, x16, x32 and x64 clock modes ‘© Break generation and detection Parity, overrun and framing error detection = Binary synchronous features: ¢ Internal or external character synchronization ‘@ One or two syne characters in separate registers ‘© Automatic syne character insertion/deletion ‘© CRC generation and checking = HDLC and SDLC featur ‘@ Abort sequence generation and detection ‘@ Automatic zero insertion and deletion ‘@ Automatic flag insertion between messages ‘© Address field recognition © Support for one to eight bits/character Valid receive messages protected from overrun ‘© CRC generation and checking Interrupt features: ‘¢ Daisy-chain interrupt logic provides automatic interrupt vectoring with no external logic ‘¢ Programmable interrupt vector fe Status Affects Interrupt Vector mode for fast interrupt processing. 1 CRC.I6 or CRC-CCITT block frame check ‘= Modem control inputs and outputs ‘= Modem status can be monitored Refer to the 280-S10 Product Specification (August 1978) and the Z80-SI0 Technical Manual (August 1978) for detailed functional and electrical descriptions. All functional and electrical descriptions in these pub- lications are applicable to the Z80-SIO, except that Channel B cannot be used for data input or output and pins 22 to 30 must not be connected. Write Register 2 (interrupt vector) and the Status Affects Vector bit in Write Register 1 are, however, still programmed by selecting Channel B with the B/A select input. All other bits in Write Register 1 or Channel B ‘must be programmed to 0. THF 8 BaD GREEEE a ¥ et B HE — FUNCTIONAL PIN CONFIGURATION JAANE BERNE sense es ale foe PACKAGE CONFIGURATION Ordering Information Z2808-S10/9 CS MHz maximum clock rate, 780-S10/9 CS 2.5 MHz maximum clock rate, ceramic package, 0°C to +70°C ceramic package, 0°C to +70°C temperature range temperature range Z80A-S10/9 PS MHz maximum clock rate, 280-S10/9 PS 2.5 MHz maximum clock rate, plastic package, 0°C to +70°C temperature range plastic package, 0°C to +70°C temperature rangeVn COMPONENTS. Zilog Product Specification Description ‘The Zilog Z6104 and Z6104L high-performance 4096-bit static read/write random access memories are organized as 4096 I -bit words. Data storage is static; however, addresses are clocked in by the leading edge of Chip Enable. ‘The 26104 is fabricated with n-channel slicon-gate eprom — | STRAP vouTace | oPTion ROM hCrCs ROM 8K BYTE ai-a1is ——>| PAGE ROM/ DECODER PROM/EPROM 2-80 RMB BLOCK DIAGRAM 93 INTERNAL DATA BusVY, BOARDS aes Z-80 PPB Product Specification PROM Programmer ‘The Zilog PROM Programmer Board (PPB) provides the capability to program 16 and 24-pin bipolar PROMS and 24-pin EPROMS. The board incorporates zero insertion force sockets and power conversion to permit a single +5 volt power supply operation. System bus interface is implemented by the Z-80 PIO and is simply addressed as 1/O with the device address of EO}. The compatible software utility ZPROG provides the capability to program from a disk file and verify PROM contents from the disk file, to list the PROM con- tents onto a terminal or printer, and to duplicate a PROM. 94Y/, Z-80 PPB Zilog BOARDS. Operation ‘The 1/0 address EQ is decoded by the ADDRESS DE- CODE to enable the PIO. The two Least Significant Bits of the ADDRESS BUS are used to select port A or B and configure the PIO for control or data transmission. Port A is set in the ‘bidirectional’ mode for reading and writing PROM data in the VERIFY and PROGRAMMING mode respectively. Port Bisset in the ‘output’ mode to control the ADDRESS COUNTER, CHIP SELECT / BUS CON- ‘TROL and PROGRAM PULSE circuitry. The ADDRESS COUNTER is cleared and clocked by PIO lines Bg and By respectively, and produces ten address lines to the program- ‘ming socket. The CHIP SELECT and PROGRAM PULSE: EPROM are controlled by PIO lines By and By. The pro- ramming pulse width is a function of the ZPROG utility and is set in software for the EPROM device being program- ‘med. The BUS CONTROL circuitry accomodates the read- ing of PROM contents ot writing to PROM via PIO Port A and is controlled by PIO line Bg Bipolar devices are pro- grammed by enabling the high Voltage drives on the data ‘us with the chip select (CE) controlled by PIO line By and generating the PROGRAM PULSE: BIPOLAR from the PIO line Bs, This pulse width is also a function ofthe ‘ZPROG uility. Features Specifications 4 Programs 16 and 24pin bipolar PROMs: 7610, 611, 1620, 7621, 1640, 7641, and 24pin EPROM: 2704, farneee | |G voc ee 2708 1.5 Amps (standby) 4 Programs 7603 PROMS using supplied adapter. 25 amps (programming ‘© Program from a disk file © Verify PROM contents from a disk file hoeedbes tee eee ee size: Length: 7.7" (© List PROM contents to teminal ae te © Duplicate a PROM Specing: 05" centers © Zero insertion force sockets ENVIRONMENTAL: o- So Up to 80% humility © Compatible with all MCB based systems and Develop iment system, Pin Assignment ZDS DEVELOPMENT SYSTEM VERSION MCZ VERSION 9 ADDRESS BIT 47 paTABITA 4 1ORG 73 DATABIT? 10 ADDRESS 6IT 7 43 DATABITS 5 DATABITS 7 DATABIT 18 ADDRESS BIT O 51 DATABITS 8 DATABIT3 73 INT 17 ADDRESS BIT 1 52 DATABIT7 12 DATABITS 88 ADDRESS BIT 4 18 ADDRESS BIT 2 4 DATABITO 13 DATABITO 99 8 19 ADDRESS BIT 3 55 DATABIT! 26 ADDRESS BIT 7 100 ADDRESS BIT 3 20. ADDRESS BIT 4 5 DATABITS —«-29_ADDRESS BITS Tor ADDRESS BIT 2 21 ADDRESS BITS 57 DATABIT2 «30. ADDRESSBIT6 102 ADDRESS BIT 1 a Bee 8 el 50 Tel 103 ADDRESS BIT 23 OM 109 INT 51 TEO 150 Mi 30, TOR 12 reo 68 DATABIT4 116 RD 45 FD 95 71 DATABIT2% Z-80 PPB BOARDS Zilog CONTROL DATA ADDRESS BUS BUS BUS +5 POWER ADDRESS SUPPLY ADDRESS +28-+1245 -5 CHIP SELECT BUS CONTROL &| PROGRAM PULSE CKTRY BIPOLAR PROM SOCKET PIN ELECTRO- Nics CHIP SELECT & (ADDRESS PROGRAM RSE COUNTER CKTRY ‘SN@ VLVG TWNOILOSYI PPB Block Diagram 96Y% Z-80 PPB Zilog Zilog PROM Programmer Utility ‘The ZILOG PROM Programmer Utility (ZPROG), operates with the ZDS-PPB, MCZ-PPB, ZDS-PPB/16, MCZ-PPB/16 ‘or PROLOG Interface (CIB) boards. ZPROG provides an environment in which the user can: “Duplicate PROMS of the same type “Duplicate PROMS of different types Write the contents of one or more PROMS to @ disk file Program PROMS from a disk file -List the contents of a PROM on the console “Display and modify any byte of a PROM ZPROG COMMANDS ‘The following parameter definitions apply to the ZPROG commands: pname begadr a PROM name from the applicable PROMs. specifies the address at which the command should begin reading or programming. specifies the number of bytes to read or pro- gram. specifies which nibble (upper or lower) is to be read ot programmed. M specifies that the user wishes to enter modify mode to modify the buffer after reading from the source PROM, and before programming the destination. v specifies that the contents of the destination is verified against the source and the programming step skipped. specifies the entry address of the file to be created (File command only). specifies the record length of the file to be created (File command only). numbytes UL entadr reclen ” Summary of Commands ‘The following notation is used in the command description. | isused to denote ‘or’, e., pnamel* means either 1 pname or an asterisk "™ may be used. [1] isused to denote an optional parameter, ¢g., [M] means °M’ may be included in the command line or left out. {All commands can be abbreviated by giving the first letter only. Commands and options can be entered in either upper or lower case except in the PROM names which must be entered as listed. AGAIN The AGAIN command is used to repeat the previous command. pname|* The BYTE command is used to read or program one byte of a PROM in the ‘same manner in which the buffer is displayed in modify mode. ': pname|* [Bebegadsl] [Nenumbytes} (UIL] 1D: pname|* [Bebegadr2} [N=numbytes2] (UiL] [M) [Vv] ‘The COPY command is used to copy (or ver: ify) the contents of one PROM to another PROM which may have different attributes. pname|* [B-begadr] (N=numbytes} [M] [V] ‘The DUPLICATE command is used to copy (er verify) the contents of one PROM to another PROM of the same type. pnamel* filename (B-begadr] [N=numbytes] [UIL] [Brentadr) [RL=reclen] ‘The FILE command is used to copy the con- tents of a PROM to a RIO file. pname|* [Bebegadr] [N=numbytes] ‘The LIST command is used to list the con- tents of a PROM to CONOUT (Logical Unit for console output). ‘The NEXT command is used to repeat the previous command (with begadr adjusted for the program command). filename pnamel* [Bebegadr] [N=numbytes} {uiL] [tv] ‘The PROGRAM command is used to copy the contents of a RIO procedure type file toa PROM. ‘The QUIT command is used to exit the ‘ZPROG environment and return to the RIO executive. Any open files are closed, BYTE copy DUPLICATE FILE NEXT PROGRAM quitY% BOARDS aes 780° PPB/16 Product Specification PROM Programmer Board The Z-80 PPB/16 provides the ZDS and MCZ systems with PROM programming capability for the following PROMs: 2716 828126 828129 828130828131 825140 828141 828180 828181 8282708GF 7 % Z-80 PPB/16 BOARDS Zilog Edge Connector Pin Assignments Description (MCZ Systems) ‘The PPB/16 incorporates three zero insertion force PIN DESCRIPTION sockets that aze mounted atthe top ofthe card. The eard a is inserted into the appropriate system and extends beyond 3, the end ofthe card cage to allow easy access tothe sockets ‘ One 2-pin socket is used forthe 2K x 8 EPROM (2716). ; ‘Another 24pin socket is used for the IK x 8 PROMSs and c a T6pin socket for IK x 4 PROMs. PROMs not listed above B ‘may also be programmed provided their pinout and pro- 2 gramming procedure matches that forthe above EPROMs 4 and PROMS. a ach cardi completly selicontained unit requiring 50 TEI -PPB-PIO nly a #5 vot supply. An on-board converter transforms 31 1O- FPB- PIO the #5 vols tothe vllage required by the PROMS and 62-64, 120-122 GND EPROMs. All communication wit the Z-80 CPU is done 6 DBs through the Z-80 PO perigheral interface vin a 122-pin n DB2 edge connecter. B DB? 5 DBI PROM Programmer Utility (PROG) 2 ie 99 4. (System Clock) ‘The Zilog PROM Programmer Software Utility (ZPROG) 100 ABS is provided on the RIO operating system utilities diskette. 101 ABD ZPROG enables the user to: 12 4B 1 Duplicate PROMS of the same type us Mi 1 Wit the contents of one of more PROMS to 2 disk file 16 RD- & Progam PROMS from a disk fle 4 Lis the contents of a PROM onthe console . Display and modity any byte of PROM. Edge Connector Pin Assignments (ZDS Systems) Features PIN DESCRIPTION = Two board versions—the MCZ-PPB/16 and ZDS-PPB/16 1-3, 59-61 oy ‘© 2.80 control for microprocessor flexibility oe a6 © Quick load, zero insertion force, PROM sockets ie al : Ao 1 Power from singe +5 volt power supply utility o in 1 ZPROG included with RIO operating system 18 2 « Usigne Program User interface wth promot statements » 8 READY TO READ a a READY TO PROGRAM? READY TO VERIFY? a (seamnae) 1 Program, List Duplicate and Verify modes of operation 30 1oRo- 45 RD- a De 48 Ds si D6 32 Dr 54 bo 53 Di 56 BB ” be 62-64,120-122 GND 38 1 109 INT mm Io 99w °, UY z-30 Pepe ee Zilog PPB/16 Specifications PROM TYPES: CONNECTOR: 24-pin EPROM 122-pin edge (100 mil spacing) available from: VENDOR PARTNO. Garry Mig. Co. 40002 PROM TYPES: ange a 14005-19P1 (512x 8) PHYSICAL CHARACTERISTICS: peo EE) ‘Width: 7.7 inches (19.6 om) $2180 (1028x8) + 7.7 inches (19.6 cx) 828181 (1024x 8) Height: 9.0 inches (22.9 em) 8282708 (1024 x 8) 1G-pin Bipolar 828126 (256 x 4) 828129 (256x 4) 828130 (12x 4) 828131 (5124) CONTROL INTERFACE: TTL interface with MCZ series data, address, and controt signals. ELECTRICAL SPECIFICATIONS: 45. VDC # 5% ‘Maximum Current~-2.5 AMPS during programming 1.5 AMPS during read 100 Thickness: 0.062 inches (0.16 cm) Spacing between cards: 1.0 inches (2.54 cm) centers Maximum component height: 0.9 inches (2.29 cm) Etch layers: two ENVIRONMENT: 0° to 50° C ambient operatingVa BOARDS maid Z,-80° AIOAIB Product Specification Analog Input/Output The Z-80 AIO is a completely compatible 12-bit analog input/output system for the Z-80 Microcomputer Board Series or any system composed of these boards. The analog to digital portion has 16 differential or 32 single-ended channels with input voltages ranging from 2.5mV full scale to LOV full scale. The digital to analog portion provides two 12-bit D/A converters with doub- le buffering to minimize output switching transients. The output voltage is selectible for bipolar or unipolar operation ranging from 2.5mV full scale to 10V full scale. This analog system is interfaced as 1/O to the CPU and ‘may operate in a polling or interrupt mode. The system's I/O addressing may be changed by on-board jumper selections 101Uh 7-80 Alas Zilog BOARDS. Features Z-80 AIO © 16 differential or 32 single-ended analog channels, © Input voltage range: 2.SmV full scale to 10V full scale ‘© High gain instrumentation amplifier ‘© Sample and hold amplifier © 12-bit converter © Maximum throughput: 45 per channel © Two 12-bit converters © Double buffered output © Single +5V power supply Z-80 AIB © 16 differential or 32 single-ended analog channels © Input voltage range: 2.SmV full scale to 10V full scale (© High gain instrumentation amplifier ‘© Sample and hold amplifier © 12-bit converter © Single +5V power supply Operat Interfacing the AIO or AIB to the system bus is accom- ‘modated by the on-board PIO which is simply addressed as 1/0. The ADDRESS DECODER (block disgram) uses ten addresses to direct all board operations. Five addresses are used in conjunction with the system control lines and data ‘bus to program the PIO operating mode, select the analog ‘input channel and read the 12-bit A/D conversion result. ‘One address is used to read the status register. The remaining four addresses ae characteristic to the AIO board and are used in conjunction with the data bus to operate the two 12-bit DIA converters By selecting the PIO port A or B control addresses, the PIO may be programmed to interrupt the CPU system and ‘supply an interrupt vector address upon completion of an A/D conversion. The selection of an analog input channel automatically requests an A/D conversion. The CONTROL and TIMING will gate the requested analog input channel to the ANALOG MULTIPLEXER, strobe the SAMPLE and HOLD AMPLIFIER and request conversion of the A/D CONVERTER. Upon completing the conversion, the A/D CONVERTER will respond to the PIO through the CON- ‘TROL and TIMING that the converted data is ready. At this time, the PIO may interrupt the system or the system may read the status register to find that the conversion data is ready and the results have not previously been read. The two 12-bit D/A converters on the AIO have separate YO addresses forthe upper and lower bytes of the dats word. ‘A word is formed by loading the eight least significant bits into the D/A converter where they are latched and buf: fered from the D/A inputs until the final four bits of the data word are received. The combined 12 bits of data are then gated and latched simultaneously to the D/A inputs. This double buffering scheme prevents conversion of part- ial words, and therefore, eliminates spiking in the output signal. Specifications Analog Input Section INPUT CHARACTERISTICS ‘TRANSFER CHARACTERISTICS Number of Channels 32 single-ended/16 differential Resolution 12bits ‘ADC Gain Ranges (Jumper 0~SV, 0-10, #25, 25, Throughput Time (max.) 45 usee/channel Selectable) HOV, G1 Amplifier Gain Ranges 1 to 1000 (Resistor Programmable) ACCURACY Maximum Input Voltage #26 volts System Accuracy at +25°C 40,025%FSR@ without Damage (max.) 0) Input Impedance 100 m®, 10 pF OFF Channel Linearity +1/2 LSB 100 m2, 100 pF ON Channel Differential Linearity 41/2 LSB Bias Current 200A Quantizing Error +172 ISB Differential Biss Current 10 Monotonicity Guaranteed 0°C to +70°C 102VY, Z-80° AIOAIB BOARDS Zilog Specifications (Cont'd) Analog Output Section ‘OUTPUT CHARACTERISTICS STABILITY OVER TEMPERATURE Number of Channels 2 System Accuracy Drift 30 ppm of FSR/°C ‘Output Voltage Ranges #10V, 0 t0 10V, #5V, 010 SV, (mnax.) G= 1 (Girap Selectable) #2/5V at SmA Output impedance 19 DYNAMIC ACCURACY ‘TRANSFER CHARACTERISTICS ere ae Resolution 12bits Aperture Time Uncertainty 5 ns Output Settling Time (max.) 10 psee Differential Amplifier CMR 74 dB (DC to | kHz) Channel Crosstalk 80 4B down at | kHz, for OFF ACCURACY channel to ON channel Output Accuracy 10.0125 FSR ‘Temperature Coefficient of #30 ppm of FSR/*C POWER REQUIREMENTS ‘Accuracy +5V 25% at 1.5 amp Dede! CONNECTOR 1, Includes offet errors, gain errors, linearity errors at ee a fain= 1. “Ansley: socket... P/N 609-258 2. FSR mean Full Scale Range. 3. No missing codes guaranteed. Ree a 7 a Operating Temperature O°C 0 #70°C eet ee ee ‘Storage Temperature 25°C 10 #85°C ‘Typical at 25°C and rated power supplies unless otherwise noted. Relative Humidity 95% noncondensing apo ‘AOR Janavoc WALOG aus oe as Tine MUX INPUTS. conrrot (4 i t INES | sawpceeno.o | f] instROMENTATION ‘AMPLIFIED | aweuirter LT} fore un ver | Paarzey ‘aa | conv ANALOG oureurs sree, | ver pata Da, aus conv AIO BLOCK DIAGRAM 103% Z-80 AIOAIB BOARDS Zilog System Bus Connections PINNO. DESCRIPTION PINNO. DESCRIPTION PINNO. DESCRIPTION PINNO. DESCRIPTION 1 sv rr ve9 6 enp 100 aga 2 45v 23 WR 64 GND 101 aB2 3 +8 2% AB? ee Des 102 AB 4 TORO 28 85 n bee 103 Ago 5 085 30 86. 2 087 115 mi 6 10 50 Sv 6 oat ne RD ? tel 60 isv 7 INT 120 GND 8 oes 61 av 98 ABs 121 GND 2 Be e Np 28 3 122 6No ‘Analog Interconnections BOARD BOARD SIGNAL P2 SIGNAL P3 (CH23, or CH7 ATN 1.2 Remote Common 12 cH 22, or CHG RTN 3 15V 3 H21, or CHS RTN 4 sisv 4 (CH 20, oF CH 4 RTN 5 ‘Analog Common 5 (CH 19, or CH3 RTN 8 ‘Analog Common 6 CH 18, or CH2 RTN 7 ‘Analog Common 7 (CHAT, or CH 1 RTN 8 ‘Analog Common 8 ANALOG | GH 16, or CHO RTN 9 ‘Analog Common 9 INPUTS | cH? 10 Analog Common 10 ons " eoea ian i oe a CH 31, or CH 15 RTN 12 aie : CH 28, or CH 12 RIN 3 cia “ CH 20, or CH 13 ATN 4 Ge . CCH 26, or CH 10 RIN 15 on ne GH 27, or CH 11 ATN 16 CH 24, or CHB RTN 17 [ oac-cno 18 ANALOG | CH 25, or CH 9 RTN 18 DAC-FB 19 INPUTS | cH 14 19 ANALOG | Analog Common 20 cuits 2 OuTPUTS| DAC-GND 2 cui 2 DAC-OUT 2 cua 2 DAC-oUT 2 cHi0 2 DAC-FB 24 cuit Py voLtace [~15v 28 cue 25 wns : as : 104Y% BOARDS aes Z-80 10B Product Specification Parallel I/O Board ‘The Z-80 IOB Parallel 1/O Board is part of the Zilog Microcomputer Board Series which provides a modular approach to a complete computing and processing system. The IOB is bus compatible and directly interfaces to all other cards in the MCB Series. It provides eight additional programmable 8-bit parallel I/O ports to aug- ment the two contained on the Z-80 MCB Microcomputer Board. The IOB features the use of the Z-80 PIO device that has become the standard of the microcomputer industry. eno reer ee i TEELECRrRCCcercee ret (eonnennnne Ree losZ-80 1OB BOARDS Features Pin Assignments © 64 programmable I/O lines IOB—PIN OUT(COMPONENT SIDE) 1 Handshake lines for byte mode control and fat 1 +5yolt 13 DATABITO interrupt response 2 +yolts 26 ADDRESS BIT 7 fue ce, 3 #8 volts 29 ADDRESS BITS 4 TORG 30 ADDRESS BIT 6 2 ines with Darlington drive capabiit oe ee ee 5 DATABITS 56 INT ENABLE IN, PIO2 f Selectable daisy chain priority interrupt structure 6 INT ENABLE OUT, PlO0 58 INT ENABLE OUT, PIO3 1 Automatic interrupt vectoring with 128 posible vectors 7 INTENABLE IN, P10 59 +5,olts © Single #5 volt power suppl 8 DATABITS 60 +5 volts vie : cine 12 DATABITG6 61 +5 volts 1 Open space provided for ser supplied interface hardware NOTE: PINS 9-11, 14-25, 27,28, 31-54: UNIVERSAL POINTERERCE Specifications IOB—PIN OUT (SOLDER SIDE) 62 GND 100 ADDRESS BIT 3 POWER SUPPLY: +5 VDC +5% 63 GND 101 ADDRESS BIT 2 Supports up to 10 Wats total 64 GNO 102 ADDRESS 8IT 1 power dissipation. 65 INT ENABLE OUT PIO1 103 ADDRESS BIT 0 CONNECTOR: 122-pin edge (100 mil spacing) 66 INTENABLE IN, PIO1 115 MT eae eee 68 DATABITA 116 RD Dee 71 DATABIT2 118 INT ENABLE IN, P1O3 Spacing, 0.5” centers. 73 DATABIT7 119 INTENA@LE OUT, PiOz ENVIRONMENTAL: 0° ~ 50°C temperature range. 76 DATA BIT 1 120 GNO ‘Up to 90% humidity without 79 INTERRUP" 121 GND condensation 98 ADDRESSBIT4 122. GND \/0 CHANNELS: Eight 8-bit parallel 1/0 channels can 9 F be programmed for byte or bit NOTE: PINS 56, 57, 67, 69, 70, 72, 74, 76-78, 80-97, 104-114, transfer in ether direction. ir: UNIVERSAL PO INTERFACE INPUTJOUTPUT BOARD - | BLOCK DIAGRAM B | ieee ll my! 106Y% 7-80 108 Zilog 7-80 PIO ARCHITECTURE ‘Ablock diagram of the Z-80 PIO is shown in Figure 1 ‘The intemal structure of the Z-80 PIO consists of a 7-80 CPU bus interface, internal control logic, Port A 1/0 logic, Port B I/O logic, and interrupt control logic. A typical application might use Port Aas the data transfer ‘channel and Port B for the status and control monitoring. ‘The Port 1/0 logic is composed of 6 registers with Figure 1 BOARDS 1OB Applications “handshake” control logic as shown in Figure 2. The registers include: an 8-bit input register, an Sit output register, a 2-bit mode control register, an &-it mask re ister, an Sit input/output select register, and a 2bit sask control register. The lst three registers are used only ‘when the port as been programmed to operate in the bit mode. PIO Block Diagram 7 =) ee REGISTER DESCRIPTION Mode Control Register~2 bits, laded by CPU to select the ‘operating mode: byte output, byte input, byte bidirec- tional bus or bit mode. Data Output Register—8 bits, permits data to be transferred from the CPU to the peripheral. Data Input Register-8 bits, accepts data from the peripher- al for transfer to the CPU. Mask Control Register? bits, loaded by the CPU to spec- ify the active state (high or low) of any peripheral device interface pins that are to be monitored and, if an interrupt should be generated when all unmasked pins are active (AND condition), or when any unmasked pin is active (OR condition), ‘Mask Register—8 bits, loaded by the CPU to determine which peripheral device interface pins are to be moni- tored for the specified status condition. Input/Output Select Register—8 bits, loaded by the CPU to ‘allow any pin to be an output of an input during bit mode operation. Figure 2 =a | A Typical Port ee KS 1/0 Block Diagram 3] 107Va BOARDS a Z-80° PMB Product Specification PROM Memory Board ‘The Z-80 PMB provides the Zilog Microcomputer Board Series with additional memory and I/O capacity. It consists of sockets for up to 32K bytes of PROM memory using ROM, PROM or EPROM, a Z-80 PIO dual port parallel 1/O device, and a Z-80 CTC providing four 8-bit counter timers. ie ountensYaz-s0' PMB Zilog type PROMs, BOARDS Features Specifications 16K bytes per board utilizing 2708 EPROMSs or 6381 POWER SUPPLY: 45 £5% With With With 32K bytes per board utilizing 2716 type EPROMs of Without 2708 2716 6381 2316 type ROMs. Memory Max Max Max Program memory addressing is implemented by using a SV 060A 28A 228A 3.40A PROM:based memory address decoder, sv Bea 5 volt operation when using $ volt ROMS or 5 volt 2716 wy = 138A EPROMs, NOTE: For certain EPROM an external ~5 CONNECTOR: 122-pin ed ‘and +12 volt power supply is required. (100 mil. spacing) (On board PIO provides sixteen parallel 1/0 lines. Oa size. an board CTC provides four Sit counterstimers. Dente 73 Accepts al industry standard ROM, PROMs and EPROMs, Spacing: centers both bipolar and NMOS2708, 2716 5 volt only), ae ee 828181, 2708, 7640, 7641, 2516, 2316, 2758. eee eee eran MEMORY Up to 16K 0° 32K bytes of CAPACITY: memory depending on which NON-VOLATILE type of ROM, EPROM or PROM used. Each 2K page may be assigned any one of 32 pos- sible starting addresses. ec] [ew 109Y% Z-80° PMB BOARDS Zilog Pinout for PROM Memory Board PINNUMBER SIGNALNAME PINNUMBER —SIGNALNAME PINNUMBER SIGNAL NAME 001 +5V 047 093 002 +5Vv 048 094 ABI 003 By 049 : 095 : os TORO 050 igo. Pup. Pio 096 00s Das 31 : 097 ‘apie to 032 098 ABs 07 iEL. PMB. PIO 053 099 (System Clock) 08 DBs 054 100 ‘ABS 09 P10.0.A0 055 rol be o10 P10.0. Al 056 102 ABI ou PIO.0. 42 037 103 ‘ABO 012 DBs O38 igo.rMp.ctc 104 ; 013 Bo 039 45 10s O14 PIO.0.A3 050 4sv 106 os PIO.0.A4 061 BV 107 016 PIO.0. AS 062 GND 108 07 PI0.0. a6 063 GND 108 O18. PIO.0.A7 064 GND 110 CK/TO 019 PIO.0.A.RDY 065 wL CK/TI 020 PIO.0. A. STRB— 066 cad 112 CK/T2 021 PIO.0.B.RDY 067, =v 113 CK/T3 022 PIO.0.B.STRB— 068 DB4 14 ZC/TOO 023 089 Dv us Mi 024 PIO.0. BO 070 +12 116 RD- 025 PIO.0. BI onl DB2 7 ROM . DISABLE~. (IN) 026 AB? on : us zc/t02 027 ABS 073 DBT 119 ZC/TOL 028, PIO.0. B2 074 120 GND 029, ABS 075, DBI 121 GND 030 ABs 076 : 2 GND 031 PIO.0. B3 077 032, ABIS: 078. 033 PIO.0. B4 079 INT— 034 PIO.0. BS 080 - 035 . 081 036 ABI3 082 037 ABIL 083 038 PIO.0. BG 084 . 039 PIO.0.B7 08s MRQ- 040 . 086 oti 087 oe oss oe 039 ‘apo ou 090 : 045, O91 ABIO 046 002 : 10a BOARDS aes Z-80 SIB Product Specification Serial Interface Board The Z-80 SIB contains four software controlled serial channels for handling most synchronous and asynchronous communication protocol BunaresntiVY 7-016 Zilog Description ‘The Z-80 Serial Interface Board (SIB) provides a pro ¢grammable serial input/output interface for the MCB OEM board series. The SIB contains four programmable, bi-direc- tional serial communication channels (USARTS), which support both synchronous and asynchronous data formats Each USART is programmable by means of a control byte loaded by the Z-80 microprocessor. The USART accepts data characters from the 7-80 ina parallel format and con- ver's them into a continuous serial data stream for trans mission. The USART can simultaneously receive serial data streams and convert them into parallel dats characters for the 7-80 CPU. All four channels are RS-232-buffered, and one channel will accomodate a 20 ma-TTY currentoop interface. An ‘on-board DC/DC converter generates the RS-232 voltage levels, allowing the SIB to be powered by a single +5 volt supply. Three Z-80 CTC (Counter Timer Cireuit) devices ae on the SIB. One CTC is dedicated to establishing one of 14 baud rates foreach of the four USARTS. Two CTCs are used to accomodate Z-80 interrupt capability for receive and transmit operation for each USART. Environment 0° to S0°C ambient operating temperature Interrupt Configuration Interrupt interface to Z-80 CPU via two Z-80 CTCs. Request generated for transmitter or receiver ready (TXRDY— RXRDY), Edge Connector Pin Assignments PIN DESCRIPTION 1,3,59-61 +5vPS, 4 ioRd- 5 Des 8 DBS. 9 MASTER RESET 2 DB B DBO B WR 26 ABT 2» ABS 30 AABG 62-64,120-122 GND 6 DBs 1 DB? 2B DB? 35 DB 9 INT- 98 AB 99 ‘—. (SYSTEM CLOCK~) 100 ABS 101 AB 102 ABI 103 ‘ABO us Mie 16 RD- 112 BOARDS Features © Bus compatible with MCB series of boards "= Four programmable, bi-directional serial communication channels, ‘© Half or full duplex data transfer '= Synchronous or asynchronous operation Four RS-232 interfaces, one 20 ma current-loop inter- face "= Three Z-80 CTCs, one for baud rate generation, two for interrupt control, Baud rates from 50 to 9600 (asynchronous) and DC to S6K baud (synchronous) "= Three clocking options: on-board clock, system clock, extemal clock ‘© Programmable 1/0 address selection SIB Specifications SERIAL 1/0: Four serial input and four serial output channels configured with 8251 USARTS. ‘SERIAL MODES: Synchronous or asynchronous using virtually any serial protocol. SERIAL INTERFACE: CHANNEL INTERFACE 0 RS232 1 8232 2 8232 3 RS232 or 20ma current loop CONTROL INTERFACE: TTL interface with MCZ series data, address, and conteol signals VO PORT ADDRESSING: 20 jumper selectable 1/0 ports. BAUD RATE: Programmable from 50 to 9600. ELECTRICAL SPECIFICATIONS: 45. VDC + 5% ‘Maximum current = 1.5 amps ‘CONNECTOR: 122-pin edge (100 mil spacing), AUGAT PN 14005-19P1 PHYSICAL CHARACTERISTICS: Length: 7.7" (19.7 em) Depth: 7.5"(19.1 cm) Thickness: .062" (0.16 em) Etch Layers: TwoY 7-80 SIB BOARDS Zilog Block Diagram TARDY TOSELECT, VO SELECT vo ADDRESS. DecoveR FIA Thx CLOORS SouTROL BUSSection 3 Development SystemsV7 Zilog Section 3 Development Systems For Hardware Development ‘The ZDS-I Series provide the tools necessary for the designer to easily debug and test 280 and Z80A Micro- processor-based hardware. Functions normally supplied by many pieces of special purpose design equipment are integrated in by the ZDS-I Series Development Systems. As an Emulator the Development System connects. directly to the prototype system and behaves like the Z80 ‘or Z80A Microprocessor, only under direct control of the user, to enable’ Setting or resetting ofall registers and RAM memory locations. Setting or resetting of interrupt controls Single or multiple instruction stepping. Setting or displaying of I/O Port information Start/Stop control of program execution. ‘Asa Logic Analyzer the Development System mon- itors and stores pertinent CPU bus activity and terminates program execution in an orderly manner when user defined events occur. Some examples are: © Storage of address, data and contro! bus information ‘during each bus transaction. © Storage of only user defined bus transactions; Memory read, I/O write. ‘© Suspension of program execution on occurance of a user defined event. ‘© Display a history of the lst n bus events, where n equals from one through 256 events. As a ROM/RAM Simulator the Development System Inds its memory to the user's prototype system with the memory mapping features. ‘© Memory Mapping allows the user to describe the phys: {cal nature of the memory to be used by the proto- type system. A memory map is defined by the user to specify which addresses exist in the prototype and Which address locations are to be “borrowed” from the Development System, © The ZDS-1/40 Development System also permits mem ory address to be declared write protected or non- existent so that if any access is attempted a break in program execution will occur. Asa PROM/EPROM Programmer the Development System provides the functions necessary to write, ead, ver- ity and duplicate PROMS. This is an optional feature pro- vided by the ZDS/PPB and ZDS/PPB/16 PROM Programmer Option, or ZDS/CIB Printer ané Prolog PROM Programmer Interface, For Software Development ZDS-1 Series Development Systems provide a standalone microcomputer system utilizing the versatile RIO Operating System for the creation, editing, assembly and debug of the software for the powerful Z80 Micro- processor, The RIO Operating System with relocatable modules and 1/O management is a general purpose computing system with an architecture that is designed to facilitate the development process, provide straight-forward linkage to various systems routines, and enable expansion of system features to meet the particular needs of individual users 7Vn Zilog Features © OS EXECUTIVE 12 Map requests for operations on logical units to specific device handling programs. © Commands may be issued to OS from the console or by an executing program. © Any number of user defined commands may be added to the system. © Command sequences may be recorded in files and ex: ‘ecuted as group, = ADVANCED ASSEMBLER 1 Relocatable or absolute object code format © External Symbol references. © Global Symbol definitions, 1D Macros and conditional Assembly. 1 Paged symbol table permits assembly of arbitrarily large programs in standard memory © Include directive permits additional files to be merged into the source program at assembly time. = LINKER 10 Astigns absolute addresses to program modules. © Resolves External references. © Permits overlays or memory gaps. © Produces memory map and Global address table. ‘TEXT EDITOR © aged work space permits any size of file to be edited. 1 Automatic backup file creation for protection. © Access to other files during edit session. © All edit operations for locating and modifying lines Within a file are based on character string matching, PROM MONITOR © Low lovel device handlers for system console and floppy disc © Bootstrap loader for ease in system initialization. 1D Machine language Debug package. ‘ZDOSII DISC FILE HANDLING PACKAGE. 1 Allocates all dise space automatically on an “as needed basis. 1 Supports sequential access to file or direct access to any specific disc address. TABBING © Supported throughout the system. © Compact storage of tabbed text on disc Utilization of a standalone microcomputer permits all program preparation and verification to take place in the same environ- ment. Smooth and rapid transition from program input, to assembly and linkage to execution and debug provide a rapid and in- expensive solution for software development. Optional software languages include a BASIC interpreter, Fortran compiler and Zilog’s own powerful PLZ family of system programming language processors All software is supplied on floppy diskette media. Each package comes complete with object software, technical and user documentation, and instructions for use with the ZDS.1 System. usY% ZDS-1Series SYSTEMS Zilog Product Specification ZDS-1Series ZDS-1/40 4MHz Development System The ZDS-1/40 provides a powerful standalone development system for use with the Z80 or Z80A Micropro- cessor and associated 4MHz peripheral components. Precise emulation is provided by using two microprocessors, a Z80A-CPU which is inserted into the prototype system and a second Z80-CPU which is internal to the devel- ‘opment system. This method allows precise emulation up to clock frequencies of 4MHz, While similar in functional capability to the ZDS-1/: features, shown below '5 Development System the ZDS-1/40 provide special © External Z80A.CPU for direct connection to the user’s prototype system. ‘Precise emulation for systems employing clock rates to 4MHz, '* Memory mapping and protection in blocks of 1024 bytes. © User memory refresh, even witen an emulation i suspend: of © Verification of user clock integrity Memory address translation, Detection of memory accesses to write protected or non- existent blocks. New powerful dise-based debug software. Features ‘= Z80A.CPU—The 4MHz version of the powerful 280 = Memory Mapper—Enables the user to describe the phys- ‘micro-processor. ical nature of the memory to be used. The user may util ize the memory in the Development System, his own sys- tem or a combination of both in blocks of 1024 bytes. In addition each block may be assigned properties of be ing non-existent or write protected to aid in the debug ‘= Floppy Dise Drives—Each providing for the storage of up and development of the prototype system. to 300,000 bytes on an inexpensive, removable diskette, = Main Memory—Capacity of up to 60K bytes on a single board, allowing more room for 1/0 options. Standard system includes 32K bytes. = Memory Address Translator—Is an additional feature RIO Operating System—With Relocating Assembler, Link- provided with the Memory Mapper. It enables a block er, Text Editor and Logical File Structure. (1024 bytes) of memory in the user system to be phys Se ically located ata different address in the Development specific adres, data and contol bus ins during selected System. ‘operations, e.g. Memory Read, Memory Write, 1/0 Read, 1 User Clock Integrity—is verified to insure the clock sup VO Write plied by the user doos not fall below 256K Hz. * Breakpoint Module—Enables the monitoring and testing ‘= Refreshwil always occur even when emulation is sus of specific address, data and control bus states to stop. pended, to maintain data integrity if dynamic RAM’s program execution of to create a scope sync dre employed. = 1/0 Ports—The user may have access to all I/O Ports when. in User Mode and User Clock is selected. 19Up 10s-1Series Zilog SYSTEMS. ‘ZDS-1/40 Debug Command Package ‘The ZDS-1/40 Debug Command Package provides powerful disc based software to support the Z80A-CPU Emulator module, The command repertoire not only includes debug commands for monitoring and analyzing execution of programs under test, but also includes initialization commands to describe the nature of the mem- ory storage being utilized. Once the memory configuration has been established, it may be saved on disc and reloaded as required, thereby eliminating the need to define the memory configuration prior to each emulation session. The following list describes the available commands: MAP DMAP WRITE BREAK DISPLAY MEMORY FILL GET HISTORY INTERRUPT MODE Creates a map that describes the physical na- ture of the user’s memory address space. This enables the user to define memory in blocks of 1024 bytes to exist in either the user sys- tem or the Development System. In addition, the properties of each block may be specified as either non-existent or write protected. (Display Map) — Allows the user to display 2 single entry, range of entries or the entire map and allows the user to edit the map. Determines whether a break occurs when a ‘memory write is attempted to an address which has the property of being write protected. Is used to specify when the Real-Time execu- tion of a user’s program will be terminated. ‘The option fields of the command may estab- lish a break to occur on any combination of the following events: ~Address Compare —Data Compare or Compare with Mask Memory Read or Write —Port Read or Write Is used to display the contents of a memory location or group of locations. If single bytes are displayed the user may change the con- tents of each byte, ‘Causes a given data string to be stored in all locations specified by the command. Loads a memory image file from dise and loads its entry address into the program counter. Begins execution of the user’s program. An ad- dress may be specified from which program ‘execution will begin. Ifthe program had pre- Viously terminated execution due to a break, then the GO command will estore EMULAT- OR status and resume execution. Enables the display of the last n events stored in the Real-Time Storage Module, where n equals from I through 256. Data displayed will be: Address Bus (16 bits) Data Bus (8 bits) —Control Bus (7 bits) Provides for the display, setting and resetting of the interrupt mode of the emulator (mode 0, 1,2 or disable). NEXT os PORT PROM PULSE quit REGISTER SAVE SET status TRACE 120 Provides a means to single step from 1 to n in- structions. All CPU registers ae displayed af- ter the selected number of instructions has been executed. Is used to exit the Debug environment and cause the operating system to be loaded and initialized. Enables a single character to be input from any selected port and displayed. The user may then enter a data byte to output to the spec- ified port. ‘Transfers program control to the resident De- bug software contained in the Development, System PROM’. Is similar to the BREAK command except ‘that program execution is nat suspended. In- stead a Syne pulse is generated. This pulse is available asa sync for external test equipment. Is used to enable return from current pro- gram to the calling program. Enables the examination and modification of any or all CPU registers. Enables the contents of memory to be copied ‘onto dise along with the entry address. These files may then be retrieved using GET com- mand. The contents are assigned a file name to permit each of location on the dise. Enables the sequential storage of data bytes into memory at the address specified by the Displays the emulation status, e.g. interrupt ‘mode, clock source, break and trace argu: ‘ments, Allows the user to specify which types of bus transactions will be stored in the Real-Time ‘Storage Module. The user may specify any ‘one or a combination of the following types of operations: ~Memory Reads Memory Writes —Port Reads —Port WritesSYSTEMS ZDS-1/25 2.5 MHz Development System The ZDS-1/25 Development System is a low cost standalone development system used with the Z80 CPU for prototype development of systems employing clock rates not exceeding 2.5MHz. This system provides a standalone microcomputer with dual floppy discs, optional peripherals and interfaces to assist the user in the software and hardware development activity of a Z80-based system. Two modes of operation are provided to accomplish this: User Mode and Monitor Mode. In Monitor Mode the system enables the user to utilize the RIO operating system to develop, edit and modify his software. In User Mode, the system memory and peri- pheral devices may partially or totally be allocated to the prototype system, with the exception of 1/O ports EQH through EFH. This enables the user to execute his program ina real time environment, Features © 69K bytes of RAM memory = 3K PROM Monitor Program with 1K of ded: icated Monitor Scratch pad area. = Programmable Hardware Breakpoint Module ‘enabling the suspension of instruction ex ecution at a given address or activity (Mem ‘ory of 1/0), Programmable Real Time Stor- age Module to store CPU activity (address, data and control bus), for up to 256 events, to monitor memory or I/O Port activity ‘= Inccircuit emulator with three foot connec- ‘= Memory mapping to describe the nature of the memory used, either user or ZDS mem- ory. Mapping occurs using blocks contain- bytes each, * Dual Floppy lise drives having a combined storage cap- acity of 600,000 bytes RIO operating system providing a combination of a Text Editor, Assembler, Linker and ZDOSII File Men- agement System,Y% ZDS-1Series Zilog SYSTEMS ZDS-1/25 Debug Command Package ‘The ZDS-1/25 Debug Command Package provides the capability to control, analyze and debug programs whic may reside in internal or external prototype memory, or a combination of both. Debug commands are contained in 3K of PROM and use 1K of RAM fora “scratchpad” area. The following is a list of the debug commands and their functions: BREAK Sets an automatic hardware breakpoint into the real-time debug module. This break can be on a memory read, memory write, 1/0 port read, or I/O port write. Addresses, data ‘and data masks can also be specified. A break from the user program can also be caused by pressing the Monitor button on the front pan- al. In either case, a break causes the state of, the user's CPU to be stored so that execution ‘can be resumed later, Control returns to the debug level. PORT PULSE quit COMPARE Allows the user to compare blocks of mem ory. REGISTER DISPLAY Provides access to memory locations. These ‘memory locations may be displayed asa block ‘or observed one ata time for examination and ‘modification. SAVE FILL Allows the user to store a specified data byte ‘throughout a range of memory addresses. GET ‘Transfersfile images formed by the SAVE SET command into system memory, ready 0 be executed by the GO Command. TRACE Go Begins execution of the user’s program. Ex: ecution can begin at any specified address, or it can continue from a previous breakpoint. A programmed or manual break is required to return control back to the debug level. INTERRUPT STATUS Allows the user to display and modify the state of the interrupt enable flip-flop. HISTORY Is normally issued after a break from a user program. This instruction lists on the term- ina the state of the address, data and control busses of the CPU during the execution of up to 255 bus transactions that occurred in the user's program just prior to a break. JUMP Transfers control toa starting address of pro- gram, but the system remains in the Monitor Mode MOVE Allows the user to transfer a block of mem- ‘ory of any size from any location to any o- ther location, NEXT Executes one or “N” instructions and prints th f the CPU registers after each 12 Peimits examination and/or modification of, VO port data. Is identical to Break except that a pulse is provided, via a BNC connector, each time the specified condition occurs, and the pro- ‘gram continues to execute. Pulse can be used to synchronize external test equipment. Returns control to the OS level. Provides access to the Z80-CPU registers. ‘They may be displayed in their entirety or ‘opened one ata time for examination and change. The register command also allows the user to display and modify the address flag and interrupt mode. Stores the RAM image of linked programs and subroutines on the user's disk. ‘Stores data entered from the terminal into specified or memory locations. Specifies if memory read, memory write, port read and/or port write conditions are to be stored in the Real-Time Debug Module during execution of the user's program.Y% ZDS-1Series SYSTEMS Zilog Peripheral Equipment Zilog provides peripheral equipment to enhance the performance of the ZDS systems to get the job done. ZDS/CRT Terminal ‘The CRT Terminal provides an alphanumeric display con- taining 1920 (80 charactersline x 24 lines) with attached keyboard to serve as the system console. Communication between the terminal and the ZDS-1 Series System occurs ina character-by-character mode at transfer rates of 110, 300, 1200, 2400, 4800 or 9600 bau. ‘SCREEN FORMAT ‘Characters per line 80 Lines per display Py Character set 96 character ASCII Character format 5x 7 dot matrix MECHANICAL ‘TERMINAL Size 12” high, 17” wide, 15” deep Weight 35 pounds KEYBOARD Size 3” high, 17” wide, 8° deep Weight 5 pounds ENVIRONMENTAL Operating Temperature 0° to 50°C, Storage Temperature —30°to 70°C. Humidity 0 to 95% non-condensing ELECTRICAL Power Consumption 150 watts Domestic Power 105~130 volts; 60 Hz Export Power 105-130, 210-260 volts; 50 HzWy 1vs-1series Zilog ZDS/Printer Terminal SYSTEMS Peripheral Equipment ‘The ZDS/Printer provides a low cost, highly reliable character printer for use with the ZDS-1 Series Development Systems. ‘This printer features excellent print quality with sharply defi ‘make it well suited to the laboratory or office environment. Both upper and lower case character are impact printed within a 9x 7 dot m speed of 120 characters per second. Bidirectional printing allows the printer to develop the shortest printing path. A read/write memory stores up to 132 printable characters that will comprise the next line, allowing “look ahead” for the next print position, The result is faster through- put and increased reliability Specifications Print Speed Characters/Inch (Characters/Line Lines/Inch Vertical Paper Width (Maximum) Character Set Forms Length Selector Forms Specification: Type Width Copies Weight Thickness Ribbon od characters. Its small size, mobility and attractive appearance f the full 96-character set ix to maintain a printing 120 character/second (bidirectional) 55 lines/min. (132 char- actersfline) 250 lines/min. (10 char acters/line) 10 132 6 15 inches 96 USASCHL 2Channel VEU Continuous fanfold, edge per forated 4 variable 4 inches to 15 inches Original and 5 copies 15 Ib. single part, 121. with 7b, carbon multipart 0.003 to 0.020 inches Cartridge with continuous loop (0.25" x 15 yés,) la% ZDS-1Series SYSTEMS Zilog Hardware Expansion Options Zilog Offers 2 variety of hardware expansion features to tailor ZDS-1 Series Development Systems to best suit the users’ microprocessor development needs, A standard bus interface structure allows the use of modu- lar boards, each packaged with very high density LSI components for maximum reliability and performance In addition, software is provided with standard interface to enable immediate use the interface. ZDS/PIB PARALLEL INTERFACE BOARD ‘The PIB provides a basic parallel interface between the ZDS-1 Series Development System and external devices pro- vided by the user. Two Z80-PIO components are provided with supporting logic to give the user 32 bidirectional I/O bits, The card also contains plated through holes for insertion of a Z80-CTC to provide four counter-timer channels. The ‘uncommitted PIO’s and/or user supplied CTC can be inter- faced with the system’s daisy-chain priority interrupt struc- ture. Unused space is provided with 16-pin dip locations (Vee on pin 16, and GND on pin 8) to allow the addition of Togic at the user's discretion. A four-bit dip switch enables YO port address selection while additional control logic dr. ceets port transaction with the system bus. ‘The flexability of the PIB is demonstrated by Zilog in using it to design our own family of interface boards; ASPIO, CIB and RXB. ZDS/ASPIO AUXILIARY SERIAL 1/0 BOARD The ASPIO board provides one auxiliary parallel com- ‘munications interface and one auxiliary serial communics tions interface for the ZDS-1. A parallel interface is designed for communications with the printer supplied by Zilog. Also «printer employing the interface characteristics of the Cen- tronies Model 306C may he used (e.g. Tally Model 1202 or 1602, Wang 200W). A serial interface, utilizing a Universal Asynchronous, Receiver/ Transmitter, is provided to enable synchronous or asynchronous, full duplex communication with external devices employing RS-232C interface charac- teristics. Uulity software is provided for the parallel printer interface and diagnostic (exerciser) software is provided for the serial interface. ZDS/CIB CENTRONICS INTERFACE BOARD ‘Two specialized parallel interfaces are provided, one dedicated to interface with a Protog 90 Series Prom Program ‘mer and the other for a parallel printer interface previously described under ASPIO. Utility software is provided for each interface eliminating the need for the user to develop his own utilities. ZDS/PPB PROM Programmer Board ZDS/PPB/16 PROM Programmer Board aa hshs degned ohne postage ‘The PPBY16 is functional equivalent of the PPB, pre- ing, duplication and verification of the following: viously described, except it is designed to accomodate the EPROM’s— 2704 and 2708 following types: BIPOLAR 7610, 7611, 7620, 7621, 7640 and 7641 EPROM's- 2716 Al programming activity is under direct control of the BIPOLAR 82827, 825181, $2131 software uility program provided nsY% ZDS-1Series Zilog SYSTEMS Software Expansion In addition to the RIO Operating System Zilog provides a broad range of higher level languages to simplify and accelerate microprocessor software development activity BASIC Zilog’s newest Extended BASIC Interpreter sets a new standard in precision and speed performance for the most popular microcomputer language. Two versions of the sys: tema version of business BASIC with a 13-digit BDC data type—and a scientific version with the conventional 32-bit floating binary data type-guarantee the optimal mix of speed and precision for any application from professional quality business data processing to extensive scientific ca culations. In both of these versions, a 16-bit integer data type provides compact storage and rapid computation for status and control variables. Finally, the string data type per- mits manipulation of variable length text in a uniquely pow- erful subscripted notation. Both interpreters have extensive access to disk files through Zilog's ZDOSIHI disk operating system. Internally, the Zilog BASIC Interpreter has advanced the state of the art in microcomputer language both in its math- ematical packages and in its method of variable reference. Transcendental functions supplied in the Zilog BASIC pack- age use the powerful technique of rational approximations to limit the number of arithmetic operations performed in their evaluation while guaranteeing accuracy. The fundamen- {al arithmetic operations all use rounding of results rather than truncation to further enhance system accuracy. The Interpreter itself maintains all variable references in an en: ‘coded form to eliminate the need for execution time sym- bol table searches. As a result of these advances, BASIC pro- vides the convenience of an interpretive environment, speed normally not found in an interpreter and random access to disk files through a sophisticated disk operating system. FORTRAN IV FORTRAN has long been accepted as the standard for scientific programming and isthe “native” language of many part-time programmers. Zilog supports FORTRAN with a compiler conforming to the ANSI 1966 specification. This level of FORTRAN is commonly referred to as FORTRAN Nv. Full conformance, with the exception of COMPLEX data types, to the generally accepted ANSI standard insures that accumulated libraries of FORTRAN programs willbe im- ‘mediately usable in the ZDS-1 environment. There is no need to translate to a special microcomputer language. Zilog FORTRAN opens the door to the richest traditions fof scientific programming in a small, inexpensive environ- ment PLZ PLZ is Zilog’s own family of system implementation lang. uages. Designed specifically with the system programmer in mind, PLZ provides an extremely sophisticated structured programming environment. Implemented at two separate language levels and in distinct translator packages, PLZ of- fers a complete solution to microcomputer system program- ming problems. In its highest level, PLZ isa fully block structured lang- age with an IF-THEN-ELSE clause, a case selector (actual- ly implemented in the syntax of the IF statement), block REPEAT and EXIT statements, procedure references and, ‘of course, RETURN’s. Data types include BYTE, WORD, INTEGER, SHORT INTEGER and POINTER as well as, ARRAYS of any type and RECORD’s composed of group- ings of the various basic types, arrays, or even other records. At this language level, both an Interpreter and a Compiler are available. The interpreter provides a fast and convenient ‘means of program development and debugging, while the highly efficient Compiler generates Z80 Object code. For applications requiring total control of hardware re- sources, a second level of PLZ provides all the block struc- turing and control conventions of the full compiler, but uses assembly language statements rather than compiler level expressions and assignments. Thus, it acts as a PLZ. compat ible structured assembler and produces code which ean be linked directly to modules translated by the compiler. Regardless of the scope or complexity of a systems pro- gramming problem, PLZ. will provide a simple, elegant, and complete environment for its solutionSection 4 MiscellaneousVs Zilog Section 4 Miscellaneous WE WANT YOU TO KNOW MORE . ‘To assist you in selecting the right Zilog products for your application and to keep you abreast of the latest developments in our technology, each Zilog field office has one or more Field Applications Engineers. They can be reached at the locations below for quick and ac EASTERN Sales and Technical Center Zilog, ine. 76 Treble Cove Road North Billerica, MA 01862 ‘Telephone: (617) 667-2179 TWX 710-347-6660 SOUTHWESTERN Sales and Technical Center Zilog, Ine. Regional Offices MIDATLANTIC ‘Technical Center, Zilog, Inc. P.O. Box 92 Bergentield, NJ 07621 ‘Telephone: (201) 385-9158 TWX 710.991.9771 NORTHWESTERN Sales and Technical Center Zilog, Ine. 18001 Sky Park Blvd, Suite K 10340 Bubb Road Inine, CA 92714 ‘Telephone: (714) $49-2891 ‘TWX 910-595-2803 Cupertino, CA 95014 Telephone: (408) 446-4666 Additional Zilog Literature rate information about Zilog products: MIDWESTERN Sales and Technical Center Zilog, Inc. 1830 East Higgins, Suite 114 Schaumburg, IL 60195 ‘Telephone: (312) 885-8080 TWX 910-291-1064 For information on products not covered in this Data Book or for more detailed information than provided here, you may order additional literature direct from Zilog by filling out the literature order form which ap- pears on the next page and sending it to: Zilog, Inc. 10460 Bubb Road Cupertino, California 95014 ‘Telephone: (408) 446-4666 ‘TWX 910-338-7621CUT ALONG boTTED LINE eo Zilog ORDER LIST en ‘TO ORDER ZILOG LITERATURE: 1 Give fullname, title, company name and address, and telephone at the top of ths literature order list. = For items requiring payment: Manusl orders totaling less than $100.00 must be accompanied by a check or money order. Orders exceeding $100.00 will be processed if accompanied by a purchase order number. ‘= Large orders ie., more than five manuals, ae shipped via UPS and cannot be shipped to a P.O. Box. UPS delivery time takes from 3—7 working days. ‘= Small orders are sent Third Class via U.S. Mal. Delivery time for Third Class mail takes from 1014 days. 1 International/ Overseas orders are sent Air Mail Printed Matter via U.S. Mail. Delivery time takes up to three weeks. cary. SEND BACKORDER QTY. SEND BACK ORDER, APPLICATION NOTES ‘SOFTWARE (CONT'D) 2.80 Ap Note (interrupt). . D280 Pz Spec Sheet Q =D 2.80 Ap Note (Dynamic RAM). DB = 280 COBOL Spec Sheet a BOARDS = 8 280 Fortran Spec Sheet a 1 2-80 Microcomputer Board Catalog, o 2-800 SYSTEMS 12-8000 Architectural Overview... a 0 2.80201 series Brochure. D8 28000 Brochure = a == 2280 mez-1 Series Brochure Q MISCELLANEOUS =D 2-80 MCz 1105 Spec Sheet 1 ____ Do Us. & Canada Rep & Dist. List o D280 Mcz 1/36 Spec Sheet DQ OD Price List... o 1 2.80 RIO Spec Sheet OQ DB otter o _ Z80 Basic Spec Sheet. a (Orders for these items will not be processed prior to receipt of check or money order. No P.O. numbers please. ary. sen BACK ORDER QTY. SEND BACK ORDER ——G Zilog Data Book 500 0 ‘SYSTEMS (CONT) ‘COMPONENTS: 0 2-80 Moz 1/20, 1/25 HW Manual. 4.60 0 D280 CPU Technical Manual 7900 =O Z20 Mcz 1/30 HAW Manual 450 0 = B_2.80 Program Reference Card 198) 0 280. MCz_1/35 HAW Manual 4500 =F 2.8010 Technical Manual 450 0 SOFTWARE = Z80 Te Technical Manual 4500 ___ 0 2-80 McB SW Manust 4500 == 280 S10 Technical Manual 7500 = ____ 0) 2.800821 SW Manual 10.00 0 BOARDS = G20 208 PROM User Manual 200 0 0 2.80 nce Hw Manual . 4800 © Dy *2-80 Mcz PROM User Manual 200 =O 280 MoCIE HW Manual 4500 9 2-80 Assy Lang. Prog. Manual 750 0 Z-80RMB/E HW Manual 4500) = 2-80 Basic Inerpreter User Manual . 10.00 C1 0 280 108 HW Manu: 2800 2:80 RIO SIW User's Manual =O 22018 Hew Manu 2500 (Grpiece packages) = 2:80 S18 HAW Manual « 450 = __ D1) Operating System User Manual . 15.00 C1 8 *2.80 Pua HW Manual 4500 = 002) Assembler Linker User Manual . . 7.50 C1 2-80 PPs HW Manual 450 0 3) Text Editor User Marual...... 7-60 1 D280 A10/a18 H/W Manual 450 0 D280 PLZ Language Report 750 O = 8 +280 6P8/16 HW Manual 4500 = 02.80 PLZ Version User Guide 250 0 C0 °2-80 Moz 1/05 HAW Manual 4500 — ____ D280 Mcz COBOL Language Report 16.00 1 = Gi Z-80 mez coBOL User Guide 500 0 COMMENTS *Not available at this time. Will not back ord$5.00 Printed in US.A. Zilog, Inc. 10340 Bubb Road Cupertino, Califomia 95014 Telephone (408) 446.4666 TWX 910.338.7621