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    MICRO ELECTRONICS FABRICATION

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    MICRO ELECTRONICS FABRICATION

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    5 views290 pages

    Microelectronics Fabrication

    Uploaded by

    Adithya Chandra
    MICRO ELECTRONICS FABRICATION

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 290
    ‘THE OXFORD SERIES IN ELECTRICAL AND COMPUTER ENGINEERING [AneL S. Sepa Seis Eaitor, Electrical Engineving The Science ee ane ee d Engi . eee een ae oy ecupaee mon ars and Engineering ee eceeieeece ee a ee peney eerie, : : Seuiae meena: of Microelectronic Se ecdacncas Cee Ss Mey Daag ot Ed Fabricati eae eat Comer Dig Let and State Mechine Design, 3d Ea abrication Ce aia ica ted nd Sem Ande, SE ectearcer me au Dimiutiev. Understanding Seiconducir Devices SECOND EDITION Reena pee alae eenecnaeeens Cel aimee cache Laney & termes nt Seems mene mec oe oe Jee ction Oc Fe Conmmioion tens Stephen A. Campbell Kuo, Digital Control Systems, 3rd Ed. Lancet) of Mnestta) ties te iid log Comma Sems St Ek Se Dita mete Creat Des Carer Syl en fran dnb EEL nan aa Eecronepene Pilar bopes ‘Warner and Grung, Semiconductor Device Electronics New York Oxford Oxfnd University Pree Oxo New York Atboge Abelard — Bangkok Boge Bocnge Aes Caleta Cape Towa. Chena Darep Solas Deli rene Hong Kong Ital Karachy Kola Compur Madi Meitgimne "Merce Giy Mba Natt Pass St Paulo Shanghah Sigapore Tape Tatjy Teron Wow sed oat compas in Beip ean Copy © 200 by Oxford Universi Press Publi by Oxford Univers Pes, ne. 13 Aan acu New Yok New York 10016. nfo segs une ofOnford Univers Pest All ight reserved. No prof hie publication maybe repodced, red ina eal syst, o ante, 12am or by any nears elecons, mesic, prcoping. econ. robe, without Pt emai of Oxo Unive Pes Lincary of Congress Cataloging in Publication Data Campoat, ups A 15 Tf science a coginecing of mises fabcaowStephen A, Campbell — ‘cm. — (The Onesies ia lactic and computer einen) jcade ibigrpacl elec and index fewerssimas | Sonoita Desi adigstcon Tie Sess Spacer S ooesen2 £ ; Aa ad Mare “* Prinng angst 33798 6B ‘ing in the United Stas Arsen oni re pager Contents Preface — xii Part I Overview and Materials 1 Chapter 1 An Introduction to Microelectronic Fabrication 1.1 Microelectronic Technologies: A Simple Example 5S 1.2 UnitProcesses and Technologies 7 13 ARoadmapforthe Course 8 14 Summary 9 Chapter 2 Semiconductor Substrates 10 2.1 Phase Diagrams and Solid Solubility” 10 22 Ceystallography and Crystal Stoeture® 13 23 Crystal Defects 16 2.4 Caochralski Growth 24 25 Bridgman Growh ofGaas 29 26 Float Zone Growth 30 27 Wafer Preparation and Specifications 31 28 Summary and Fuure Trends 33 Problems 33 References 34 Part I Unit Process |: Hot Processing and lon Implantation 37 Chapter 3 Diffusion 39 ‘31 Fick's Diffusion Equation in One Dimension 39 3.2. Atomistic Models of Diffusion 47 Thin seion roid tack me 3.3. Analytic Solutions of Fick's Law 45 ‘34 Corrections to Simple Theory 47 ‘33. Diffusion Coefiicients for Common Dopants 48 36 Analysis of Diffused Profiles 52 37 Diffusion in SiO, $9. 3.8 Diffusion Systems 60 3.9 SUPREM Simulations of Diffusion Profs 61 310 Summary 64 Problems 64 References 65 Chapter 4 Thermal Oxidation 68 "iL The Detl-Grove Model of Oxidation 68 42 The Linar and Parsboic Rae Coeficients 71 43° The nial Oxidation Regime 75 44 TheSinctueof SO. 76 43 Oniecharnseioaion "7 46 The Efe of Dopunts ring Oxidation and Poysiison Ouation 447. Oridton-Inducd Stacking Fats 86 48 Alleratve Gate Isolators? 88 43 Ouidaion Systems 50 4410 SUPREM Onidaions* 92 401 Summary 93 Problems 96 References 95 Chapter 5 lon implantation 98 ‘5.1 Ideatized fn implantation Systems 99 52 Coulomb Seattering® 104 53 Vertical Projected Range 105 5.4 Channing and Lateral Projected Range 110 55 Implantation Damage 112 5.6 Shallow Junction Formation’ 116 3.7 Buried Dielectrics” 118 ‘5.8 Ton Implancaion Systems: Problems and Concerns 120 5.9 Implanted Profiles Using SUPREM* 122 5.410 Summary 123, Problems 128, References 124 a genet Chapter 6 61 62 Rapid Thermal Processing 127 ness Gray Body Radiation, Heat Exchange, and Optical Absorption” High-Intensity Optical Sources and Chamber Design 130) ‘Temperature Measurement 133 ‘Thermoplastic Suess" 137 Rapid Thermal Activation of Impurities 138 Rapid Thermal Processing of Dielectrics 140 Silicidation and Contact Formation 141 Alternative Rapid Thermal Processing Systems 142 Summary M43 Problems 143 References 144 Unit Processes 2: Pattern Transfer Optical Lithography = 151 Lithography Overview 1ST Diffraction” 155 ‘The Modulation Transfer Function and Optical Exposures Source Systems and Spatial Coherence 159 ContacuProximity Printers 165 Projection Printers 167 ‘Advanced Mask Concepts" 172 Surface Reflections and Standing Waves 176 Alignment 178 Summary 179 Problems 180 References 180 149 Photoresists 183 Photoresist Types 183 Organic Materials and Polymers? 184 ‘Typical Reactions of DQN Positive Photoresist_ 186 Contrast Curves 187 ‘The Critical Modulation Transfer Function 190 Applying and Developing Phtoresist 191 Second-Order Exposure Effects 195 Ademcd Peed ire Ps” gs 158 128 89 Chapter 10 101 102 103 104 103 106 107 108 Chapter 11 na na 03 us us us uz us Summary 200 Problems 200 References 202 Nonoptical Lithographic Techniques” 205 Interactions of High-Energy Beams with Mater” 205 Direc Weite Electron Beam Lithograpty Systems 208 Direct Write Electron Beam Lithography Summary and Outlook 214 X-Ray Sources? 216 Proximity X-Ray Exposure Systems 219) Membrane Masks 221 Projection X-Ray Lithography 224 Projection Electon-Beam Lithography (SCALPEL) 225 E-Beam and X-Ray Resists 227 Radiation Damage in MOS Devices 228 Sommary 230 Problems 231 References 231 Vacuum Science and Plasmas 9 236 ‘The Kinetic Theory of Gasses*™ 236, Gas Flow and Conductance 239 Pressure Ranges and Vacuum Pumps 240 ‘Vacuum Seals and Presure Measurement 267 ‘The DC Glow Discharge” 249 RF Discharges 251 High-Density Plasmas 252 Summary 255 Problems 255 References 256 Etching 258 Wetting "259 Chemica Mechanical Polishing 264 Base Regimes of lama Ecing. 265 Tigi Pessore Plasma ching 257 teeing 274 Rewtve lu Biching 27 Damage in Reactive on ihing® 281 Tigh Denity Plasma (HDP) Etching. 282 ns m0 Part IV Chapter 12 ma 122 123 2s 23 126 a7 ae Be 210 ru y212 113 as Chapter 13 13 B2 53 bs Bs 136 7 138 139 cots ix Liftrt 283, Summary 285 Problems 285 References 286 Unit Processes 3: Thin Films 293 Physical Deposition: Evaporation and Sputtering 295 Phase Diagrams: Sublimation and Evaporation’ 296 Deposition Racs 297 Sepeoverge 301 Evaporator Systems: Crile Heating Tesniqnes 302 Malicomponet Fins 30¢ Antnvoduston to Spuceing 305 Pyne of Spring” 306 Deposition Rat: Sputer Yield 308 igh Densiy lama Spotering 310 Moricogy and StepCoverge 312 Sputesng Methods. 315 Spoteringof Specific Maeals 317 Stress in Beposted Layers 319 Summary 320 Prien 321 References 322 Chemical Vapor Deposition 326 [A Simple CVD System forthe Deposition of Silicon 326, Chemical Equilibrium and the Law of Mass Action” — 328 Gas Flow and Boundary Layers? 331 Evaluation ofthe Simple CVD System 336 ‘Atmospheric CVD of Disecrics 337 Low-Pressute CVD of Dielectrics and Semiconductors in Ht Wall Systems 339 lastna-Enhanced CVD of Dielectrics 343, Metal CVD" 347 Summary 350 Problems 350 References 351 eres Chapter 14 14 42 43 14 15 46 a7 48 9 110 10 112 wn “i Part V Chapter 15 1st 132 B3 159 15.10 1a Chapter 16 164 162 163 164 Epitaxial Growth = 355 ‘Wafer Cleaning and Native Oxide Removal 356 ‘The Thermodynamics of Vapor-Phase Growth 360 Surface Reactions 364 Dopant Incorporation 365 Defecs in Epitaxial Growth 366 Selective Growth” 368. Halide Transport GaAs Vapor-Phase Epitaxy 369) Incommensurate and Strained Layer Heteroepitaxy 370 Metal Organic Chemical Vapor Deposition (MOCVD) 373 ‘Advanced Silicon Vapor-Phase Epitaxial Growth Techniques 378. Molecular Beam Epitaxy Technology 381 BCF Theory? 386 Gas Source MBE and Chemical Beam Fpitaxy* 391 Summary 392 Problems 392 References 393 Process Integration 399 Device Isolation, Contacts, and Metallization 401 Sanetion and Oxide Isolation 401 LOCOS Methods 404 Trench lolaion 407 Silicon on Insulator Ioation Techniques 411 Semi-insulating Substrates 412 Schottky Contacts 41d Implanted Ohmic Contacts 418 Alloyed Contacts 421 Mulilevel Metlizaion 423, Planarizaton and Advanced Interconnect 428 Summary 432 Problems 433 References 434 CMOS Technologies 439 Basic Long Channel Device Behavior 39 Eaty MOS Technolgies 441 “The Base Sum Tecnology 442 Device Sing 437 165 166 167 168 169 Chapter 17 in 2 3 14 a3 176 i Chapter 18 iat 2 183 184 185 186 187 188 189 Chapter 19 ist 192 193 198 133 135 197 98 coe Hot Cari Efects and Drain Engineering 455 Processing for Robust Oxides 458 Latehup 459 _ Shallow Source/Drains and Tailored Channel Doping 461 Summary 464 Problems 464 References 466 GaAs Technologies 471 Basic MESFET Operation 471 Basic MESFET Technology 472 Digital Technologies 474 MMIC Technologies 478 MODFETs 480 Optoelectronic Devices 482 Summary 484 Problems 484 References 485 Silicon Bipolar Technologies 488 Review of Bipolar Devices: Ideal and Quasideal Behavior 488, Second-Oxder Elects 489 Performance of BITs 491 Early Bipolar Processes 494 ‘Advanced Bipolar Processes 495 Hot Electro Effects in Bipolar Transistors S04 BICMOS 508 Analog Bipolar Technologies $07 Summary 508 Problems 508 References 510 MEMS = 514 Fundamentals of Mechanics SIS Stress in Thin Fits 517 Mechanical to Blectical Transduction S18 ‘Mechanies of Common MEMS Devices 523 Bulk Micromachining Eching Techniques $27 Bulk Micromachining Process Flow 535, Surface Micromachining Basics $40 Surface Micromachining Process Plow S44 MEMs Actuators 546 High Aspect Raton Microsystems Technology (HARMST) 551 Summary Problems 554 References 557 Chapter 20. Integrated Circuit Manufacturing 559 Fo Yrliteticconand Yield Tracking 60 32 Paaleceel 505 5 Sst! Press Conta 209 Salta Cxptments and ANOVA 569 25 Deumoreeenmen 57 sae ConpuerincgtetMenfatsing 578 any carey gor Prniers 578 otecnss 578 Appendix I. Acronyms and Common Symbols | 580 Appendix I. Properties of Selected ™ Semiconductor Materials 585 Appendix 111, Physical Constants 586 ‘Appendix 1V. Conversion Factors 588 Appendix V. Some Properties of the Error Function 591 Appendix VI. FValues 595 Appendix Vit. SUPREM Commands 597 Index 599 —<$—$——_—_—_—_—_—_—_[___=—=_=_—————— Preface “The inet of his book is stroducemicroclectnicprocesicg to & wile audience wrote it asa textbook for senior andor firet-year graduate student Dut i may also be used asa ference for provtcing professionals The goal hasbeen to provide a took hati ety to fed and understand Bath sion and GaAs procestes and wchaolgis are covered, although the emphasis on ilicon: thsedtecologies. The took assumes ove yar of physic, one year of mathematics (Owough simple ‘erential equation) and one cure in chemistry. Most sade with electrical engineering bck founds wil lo have ad at est one course in semiconductor physics and devices including pe Jnctons and MOS transistors. This material extremely wel forthe lst Bie chapters an Te ‘iced inthe fst sections of Capers 16,17, nd 8 for sodens who havent seen it before or Rnd that bey area bit uty. One course in Bak attics also encourage bit ist require fo this ‘Microeectonice textbooks neces vie the fabrication sequence into a mer of unit cones ae pate to frm be nega sit The ffs five the book a ervey ‘or a numberof loosely related opce cach wit is owa background mate. Most sont have “dtc ecaling al of te Dackground materia. They have ten it once, two oF thee year and ‘mary fil exan ago ts iporian that his flamer matralbe reestablished before stdying ‘ew materia, Dnrtated through each caper of ths Book are reviews ofthe sence that underies the engincrng. These sections marked with an", so hep maketh dsinction between the i Imuable scat lews andthe ppton of those Inv, with all he aendant approximations and ‘aveatsothetecialogy at and Optical lidoraphy, fr iestance, aay have sited Wie, bat i Fedee wil always be with us. "A secon cen dh rises in teaching tis type ofcourse thatthe solution of he eustons describing the proves often cannot te done anlyicl’. Comer difsion as an example. Fick's Ts hav analyte solutions, bot hey ae only vali in very rested parameter space. Predepos hom dffixons ee done a igh concentrations at which tne smplifyig ssumpsion used in he Sld- hom eivaton ae snply not vali. In the ares of iograpey even the simpiest solutions ofthe Fas fel equations are beyond the scope ofthe bok. I thi text a widely wed simulation program ced 'SUPREM I's been used fo provide more meaningful exipls ofthe sot of real-word dopant ‘edistibution problems tat he mirolectone fabrication engineer might ace. The sofware {ended to agen nt eplace, leaning the frdsoentalequaans tht describe microelectronic po ‘coving. pie instalatons inhale VAX-, SUN, Apollo, and DOS-bsed microcomputers. The ‘ook lve niches the bare teri with aditonl seins and chapters on proces iniepration fr ‘avlou tecnologie ad on ware danced processes. This dional material cin sections atk with 1" tie doce mat poi covering these restos, hey my be omited without loss of the isi coment of te cour “The econ edion ax aed ari of opt keep itcanent. Most otably ew chaps ten ad orf! new aplatons fr microfabrication roses. Called ecelecroretanial eee syst (MEMS), his etiting ea promise to oem p many rew ares fr microfabrication. The new ‘Chop 19 was wine by Br Gregory Cnc fo fanages he Mirtehnology Laboratory athe ‘versity of Minna and has worked on MEMS fr a mor of yeas. If yo have questions oom ‘moms on hi aren you can contact Gog rectly at hurr @ece un ial, os has to acknowedge tht omar how man ines this materials eviews i cannot be ptameed o be fe ofall the Caopetlly) nina eos. othe past, pulses have pro- “ied rata when eror were sucienly numerous or egresios. Even when eala ae published. They ave ver fc to gto the people who have already bought the book. This means the he trope ears often unaware of mt ofthe cores url anew or revised eon ofthe bok is ‘elwsed. Ths book wll hve an ema ha anyone can aces at any ime. We wll ao provide ‘rior adios to the book Bat were not vba press me. You ean cess the fe by going 0 the Oxford University Presa web ste forth Book, pr cap-esa cr/sbo0 9536085 nh ‘Rs me goes on {wil be adding other minor updates new topics on this site as wel I youd ‘Cenehng tat you fecl nods cerecton or clnctinn in he bo, | eve yout ny me ay ‘mal ediess,Campbellece unm ed, Please be suet lace yeu jutifeaton ching publishes telerences Minneapolis sac. The Science and Engineering of Microelectronic Fabrication Part I Overview and Materials scours is enlike many tat you my have lake nth the mater that wil be covered is [Pmsily x mumber of Unit processes th ae ute distinct or each ler. The bok then [eth fave ofa survey of topes hat wil Be covered rae than a linear progression, This pat ut he bak wil ay the foundations Hat il be unde Ine etn he various abc Son process. “The fist chaper wil provide a roadmap of the cour aan ineoduction to intgrate crit fabcaion. The process that are Grove giveth and Gates ies asaya he sigan taketh away. Semiconductor technology, the fabocation of imegsed esisrs, is teed to demonstrate a flow of tes poceses which we wil ella \echnology. Extensions of the tehnalogy to inte capacitors an MOSFETe ae also discos. The secon chapter wil nroce the opie of eystal growth and wafer radon, The chap ter contain base mars information ikst will be used thoughout the rest of the book, Tas Incldes erst siete and erste defen, phase diagrams, andthe concept of sla slut ‘Unt he eer uit processes hat wil be covered ia te ltr chapirs, very few imegrae cic Tabcabon faites actualy grow their own wafers, The lope of wafer producion, Nowever. ‘emonsates some of the important properties of semicondctor ails that wl be portant both Shoring he fabrication proce and to the evel yee and performance ofthe seated eit. The ‘ferences nthe production of siiconand GaAs waters are dscessed, Chapter 1 An Introduction to Microelectronic Fabrication “The eens industry has gon rp inthe pst four dead. This growth has ben ven y 2 ‘volun in rotten sry 1D puting moe than oe tei on ie of Sei ‘Coocer wis considered outing edge: Iga circuits (1s) contain eso devies were unheard ‘ST Dipl computes were large slow and exer coy Bell Lab, which had invent ihe tas {eea decade ear rected the concept of ICs, They reasood ta in ert schiewe working ecu ‘Slate descr mut work Therefore thave a SU pohly of uncon for 20 asso ce ‘isthe probably of device funtonaliy mst be (5) = 0966, or 9666. This was considered to betidiculusy optimistic tthe me, ye ay integrated cuits are ult wih ions of sists Bary tanitors were made fem grnaiom, bt most reais ae now made on sion si strates. We wl therefore emphasize silicon nis book. The second most popular material for bul ing 1s i alm arvenige(OuAs). Where appropriate, the book wil cus the processes rouired (Or GaAsiC. Aldwugh GaAs ha higher electron mobil than sco, it als has several seve {Dnitatons including low hole mobility, las sabi daring thermal pocesing, poor thermal ‘hide, high cost an perhaps most ioral, much higher defect dense, Silom bas therefore fecsse the material choice fr bphly imtgrted cea, and GaAs is teserved for ccs that pea avery high spends bt wid low to moderate levels of iteration. Curent he most om ‘on appa of GuAs i analog seats operving ot speeds in excess ofa gigabers (10 Hr). ‘Moe seventy mietoelectone farcaon fests have because 1 bull a vary of sorts Incloing micromagntics, optical devies, and micromechanical scares, Insane cases these ‘Hévure hve ap been imegrted into chipe conainingelcronic crit. A poplar nonlec- tronic splcation, sicromecharical (MEMS) swactures wil be introduced ater nhs book. “Tohart the proper of slcon microelectronics it i easiest follow one typeof chip. Mem cory cigs ave hd essen he se fonction fox mary years, aking his eype of says mean Sect Hentermore they ar extremely regula a can be soldi age volumes, making technology seteaaion forthe ep esgn eco, Ar x esl memory chips have te highest densi of [Svea Fae shows te enaiyoféymamicandom access memories (DRAMS) a8 faztin of tine. Toe vetcal axis logan, The density ofthese circus increase by increments of 4. Ech of tose ierements takes aprons thee years. One ofthe most fundameatal changes the fbrcaion proces that allow this techology evlutin iste mii fete size hat canbe 3 ____e@ FO Vineet icctonc ron « fawess fund acd son more printed on the chip. Not only does thi increase IC dem lassim iy the shorter distances that eactons and oles have sem jo avel improve the Uansstor speed. Part of the IC Performance improvement comes om this increased asso perortance and part of come ro: being Sic pack the tansisors closer togter, decessing the pars capacitance, The ipicand side of Figure Ti shows te Is have progressed frm 10 microns Gm pm = 10°" fowl bode I pm. Forse sim © etme, Fee 12 shows an ecto mien em nalcon tad 1 along wth + Raman it The eon eral and hoon Ise metal es ed 1 seats Scot he ante. The amis sles eed {feet ihe nal and emt vl in he mi ‘rap At this ale of feopress gait chips wid ery sn nica feces for 025m features wl be Seen by he dime you ea his geet, Song ccm mg SE as mi 8 Teves $< — TT ‘ode Ttalpes ASige Barge 5 [A fest glance, these incredible denies and the ascii design compleity wotk! seem exterely daming. This book, howeve, wl focus on how he cies are bil ier thin bow they tte dine or how the sire pert. The fabian oes sna no water how many tra ‘Stor a oo be chip. The Bat alo the bok wil cover tetas peations eis to build an I ‘ring mechanical constucion a analog, these wool incl eps sch forging cating, bende {nding and welding, These reps wil called wit procenesin is ext Ione knows bow todo Ch ofthese spe for contain materal (© sed, andi te machines and materia eed are sie “ihe they could be ted to make ladder, igh presen. cr smal ship. There mam ‘rand onr of he ep wil leary depo on wats being bull bu the basic uni processes erin {hc sane: Furthermore. eae sequence tat produces & foo sip has ben worked ou ther sips of ‘lar esgn could yrbubly be bik wth ese proces. The design ofthe ship tha is, what pos ‘whore sa separate sk. The ship is banded ae of apis to whch eo ste mus blk "The collection and ordering ofthese wit procestes for making wal product wil be cll 2 eclnology, Put ofthe book will cover some o he baie Ebicaion technologies. Whether the tcehooogy is wed to make microprocessors, UO cones, oF ay oer digital fanction is Trgey {mur ote fabicain process. Even nay analog design canbe Dull using a ecology very ‘Sra oned to bild most ital eeu. An TC, ben, stars with a eed for some sor of ee tronic device. A designe group of designers wanssizs he regurements ino a eit design; Cat in bow many tanistors, resistors, and capacitors mus be wed, what valves hey must have, sod {Siping example, te blueprints must srnchow reflect he eatin tha te shipbuilder cannot ut ves over Weld joints ore small vets al expoct er wo bold very high pressures. The ides man cere pve the designer a document hat sys what can and cannot be done. In miso ‘ovr thn document called the desig rales r layout rales. They specy tow smal or age ozs fetes can be how lose we diferent tues an be the desig conFerms o hese is the chip canbe Pll withthe given technology 1.1 Microelectronic Technologies: A Simple Example Testead of baci, the cult designer hands the IC fabricator a set of photomasks. The pho mais are apical represenaton of the design tat has ben produced in acconéance with he Tayout es, Asan example ofthis interface, assume that a nod exists fran IC consisting f sine le volge divider shown in Figure The ecology to bail his desi is shown fn Fgae| $iticon water wil be usd a the substrate since they are at, reasonably inexpensive, and most IC procesng equipment ist upto bande tern. The prediction ofthese sobsvates willbe discussed Fr cuapcr 2 Ste the wafer i at Teast somewhat conductive an insulating Iyer mist fat be ‘cpontal to proven leakage betwoen njacert eestor. alternatively. «thermal oxide of slicon (SIU be grown, snc it an excellent instr. The heal oxidation of silicon is covered in ‘Ghupcr 4 Nex a conducting layer deponted tha wl be used forthe esis, Several techniques fordepsing bot ulting snd conduetag layers wil be diseussed in Chapters 12-14 ‘Tis conducting layer must be dvi op into inividul resistors. This an be done by rev sng portions ofthe contin layer, lestng rectangles of he flim tht ae isolated rom each ates, ‘Theres values given by k= ‘where pithe maser esitvity isthe resin length, W sth esitor wid nis the chess Uribe layer The designer can therfore sek different values of resistors by choosing the width © Figun 13 A single estroge vier At ‘croutons soe oot, “Tpelpe shown st ght arc us conast an ——$—$— $e readin Miconeonc Faves An (sige (2 ote ie (2) Deen eterna) (4) Patera ta s49 (5 bee e {6 Pte nt (pest wt risen w o gee 14 The technology flow or vcning te resistor (toma a gare 13. length mo, subject vo the Hits specified by the layout rls. The technologist chooses the film ‘hicknes and the material (and therefore p) 0 give the designe an appropriate range of esses witout forcing him to resort 1 extreme goametes, Since p andr are determined ring the aie ‘ton and are apreoimately constant arom wafer, the rao pr more often specified than pot £ Individually. This ra ie called the sheet resistance, I bas units of 1 where the umber of squares isthe ratio of the length width of the resistor ie "The reir ifeeatin rom he desig, namely Land W fr each resistor, must be transfered fom the photomask to the wer, This done using «process called phototherapy. The men ‘commonly used type af phoolthoprapby is epiallihopraphy. In this process, a photosensitive layer elle photoresist ie rt spread on the wafer (Figure 13). Light shiiag hough the mask expose the eit in he eon othe wafer where some of the etal esis ayer mus be removed. Tes exposed epons, «photochemical action ocr he eit hat causes it 10 be esl s- saved ina developer soltion. After the develop sep dhe photoresist remains only nthe ass where {resistor sds. De wale then inumese in a ci tht solves the exposed metal layer but ‘oes ot sgniartly tack the resi. When the etch compl the wafes are eroved ff the cid bath, rinsd, sd the potoreit is removed. The photltogmphic proces wl be covered in CChapers7 through 9. Chaper 1 wilteover etching. "Athlouph he rssors have now been formed they still eed to Be interconnected and metal lines must be broagh tthe edge ofthe chip, where they can ter be attached meal wires for com. facto the external weld. Thi later operation, called pachging, wil nt be covered inthis text. If the metal ines have t cos over the resistors, another ining Iayer must be depose. To make ‘lecal contact he resistors one can ope up holes inthe insula ayer using the sabe pho tolthographic and ech processes we ad ued foe ptteriog de ress, although the composition ‘fhe ac bath ny be dee aly, the fabistion sequence can be competed by depositing (1)Srtng trate) Canth pee {unt retusa Teesipes 7 ighly condectve metal ayer, applying third mas, ad etching this metal intercones ye “The technology coms of four yes: the ower aor nate aoe eet tn =e S3388 Ul Boom em eeetecoreee as Tattup Except or edpsof the pater th ik ea ali) es can he ih Novice that he comparon ih ship Tremere ttaas nee creel ieee photomasks, ane that defines only a few resistors and tively remove some of thes layers in ceria regions. (tate eros (ener sy ness OF these ins is constant. The technology uses ing breaks owe none eal effon Dimmens epedwale (EB ie busing breaks down, a pet Th Fae 15 Sic sie orp ese sg Md be anf). Infact front ste of cessing (TP) A numberof prceses hit allow the growth of thin lsyers of semiconductor on op ofthe wafer wile discussed, These process ae Eales cpa growth. They alow the podaton of Fareed dpan repons below the suc ofthe wafer The book wil et disse ere ade oa! extgurs of towing slicon on icon and gllom sere on gallium arene (bomoe thy rl en cover nore advanced tgs hat allow te prowth extremely his yes ar the aban of advanced device suces "Tae un posers canbe scaled ito fonctions cess males, These mous ate esigged eat ont specie tanks sac te eel lation of aacent assis, fw resis {ence contacto transistors, and mip ayes of high desl inereouect. AM of tee aes ave Int cai ahances over eps few years. Clear aeoffs exist mor the vaso odes in {ems of proces complex, cat dros, planar. and performance, These modols od the Feel iy Ht ii i i Fie 1.7 soadmp fre coun inating he easy Between the chaps tank ani faction re semble in ectrnopes, Te f te mos popula eons ‘cen caen bea they ae poplar and beste ey are erste of many ober coeunon thn repent resonable cos secon ofthe mioeleonis inst wil be Feviwed Fly, ‘Stoop As you mig ine om previo dacs te sane nit process cone ed ‘ess equa for high-volome marcia of Cs wl be dacussed te fice sh neon cbrg coupled device (CCDs), ner solar cell, ad gemiing Gioes (LEDS). The only ieee ae the number, ype, a sone of te process wel © 1.3 A Roadmap for the Course fer he echclgy, Yo ae encore ok i 0 fest or Fabrcon teens ter you complete coare to ee Sos ofthe other ways tht hese ui prcesses ae epi “The vats unit processes for fbition ae fil independent. Bach ofthe next 13 bape will, a a cover a differen unit process To kes the Boo fo a manageable size, each proces can be only tril inroduced. many ese, he chiple aenseses canbe expan into books. The materia 1.4 Summary step wil ieee a ila You tr ep ch pie ve Imeprtd sir ave developed with increible level of comple. excesting 1000.00.00 tan eat Trea fis ach sonnei ne coe Sistrs pe chip. Transistor damsiy, as measured by dynam random access memes (DRAM), ere 1.7 shows amp oh coure hp shat yourinsractoy chooses flo junrpies about every 3 yeas, at has since T968, This book wl Inreduce the tehrologes used ee {o fab the ICs The bling blacks of these technologies ce the wn processes of phatlithog. sections are marked with 2°. The shapers and secons marked with * ae atonal materi ‘ag. orton isa, ion pletion etching, hn ln deposition ns eit growth, The ‘omewhat beyond the bac process needed wo describe simple semiconductor temoogies. ti process canbe anembled infect orer and umber, depending onthe ici to be al, “The lat ix chapters ofthe book are dented to sscondvctr technologie. The base unit process dacs earlier ae bre sogsthe 9 fom. Cs mede frm silicon CMOS, bipols a Sistorn GaAs fel fic wants, and micromecheic! devices. Tes ecology exarpes have TT Chapter 2 Semiconductor Substrates “Tis section of the took will deal with nit roesss that depend strongly on the properties ofthe Fa arse wales themslves.Diffsion for example, depends on te crysaiae perfection nthe cance in aay unpens on the proces tmmperstre We wil hepin wit a eseiton of phase Thabane Tis murals paricolrty weft for understanding the formation of alloys that wil be eg crn book Ts top lio leeds naturally it a discussion of sali solubility ad the do. caret scumonductrcrysiai: Following tat the chapter wil oncentrae oo crt stutres sh Ha semeevaline woes. The secon Palo he chapter wil discuss the echniqus wed 2 finned eogeonductor wafer These wafer, wbich ¥ry in ianeter fom i for some compound eetconductors upto 300m fr some licon wafers athe asc slaing pint for device faba Tee ihugh ee oneaton felis sill wake her Owe wafers, the tidy of he semicondctoe ante mess good place to bint develop a uadersanding of senicoaducor processing, FOr ‘Tore complete review of i topic se Malan and ara (1 The teri toed for efclectonies can Be dived im the casications depending 08 the anvunt of Homie oder they poses. In singe crystal materials, almost al of the atoms i the (Mosul ooupy wel defied and regaar portions Iaown as late ites, Mis ofthe eemicondctor SEeeaee tien the acne devices ae actly made ae single crystal. Arogpous mats Sen SiOy teat he apposite exreme Theses in a amorphous mil have o Tong ange ‘Sher Instead the chemical bonds have a aage of legis ad orestations, The tid ls of mae Sits polrtilin, These meters area coleston of stall single crystals randomly oisted ‘Bin eopect to cach eer. The size and orientation of ese crysas often change during pressing Und somedines even ding cect operation. 2.4. Phase Diagrams and Solid Solubility” Most ofthe ates of interest to ws in tis text ae ao elementa: rater they are mixtres of mae ae Bren ein no very wscfl ina pure state, ned, tis mixed with impure hat affect ‘Grecia pope. A wey convent way 10 pesat the properties of mintres of maeil is & ‘Shas dafom Binary pate dagams canbe Wovpht of aps that show the eegion of stability Cartan of two materials a function of percent composition and terpeatre, Phase digrans (Riya have a resmure dependence but al ofthe diagrams of neem semiconductor device fb ‘ston wl bea 1 atm 21 Fes aye eS tity "18 Figure 21 shows he tase dara for eS noe B21 Somat se dan Gian xp fe sie ef 9s [2 Deca cn he graph The upper lie, ce deserts the enperatire tiven mitre wil bein completly Ilsa Tee ove or sls curve dees ie tempera which te mtr wil empl feu. Betwcen es no crves eon ch ig hi di me, Th comonomer ‘ix weg som concerto of ad Ge bdr 0 temperate ch mate! wil pow wa a 1106. — eet 2 OSC, Aspe Bat he bei sto rath ht te ema nan euro e eo ec he fd inline cn oe ne wih emiey he cnpaon x hehe ah ie est pra Free I'S opin of ma il 32 omc pec is, The seein fhe a an ead off he pr as coment ih esis ie engeriepe he euing vie ae pce i Noe a hac ht mobi i ea tempest is inne, he compo of he mel ves Wed coal val, ‘ithe nti alt mvs de wp io ene ener ehe is ine te ene hare en Fr 7 ating ae res TC Cpe Wei pen co ea ‘mera i Figure 21 Pease sr cf Ge Si The doles eres he "hemodynamic lib cures ASM eration. e of 12 2Seakordc Sus cooing, the ste processes osu. In either pees, maining thermodycamic equ in he Solid muck ore fic han isin th me ‘ample 24 Forth example jas cused, calculate the faction of the SO charge tat is molten at ise. Solton: Let bethe fraction ofthe charge thats mate, Then | ~-cshe fri of he charge hati sli Tre faction of sion in the melt plus te fraction of ico i he sid tak 10.5, he otal fation of iis the charge 05 = 022 + 0581 ~ 9) Solving for 036 = 008 r= 02 22% of th charge is nolan and 78% i sll Figure 22 shows the ps diagram for GaAs (3. Material stems lke GaAs tat ave 10 solid pases tat melt form a single ligud phase recalled intermetlics. To examine the phase ‘Sagres in he lower igthand corer, Ts asi pve, snc it i below the solids fi. ‘The venice! line a the center of the dagrra indates at tbe compound Gx wil for i hs Tiara sytem The lower lft region ea solid mine of GaAs snd Ga, while th region ia he {bwer gt hse nature of GaAs and As, I this Azsch solid is heated 1 10°C, te soation tuitepn to mel Beeween tis frperafute andthe Kgudus line, the concentration ofthe mel ca te detrmited as beiore. For Orch charge, th mixed state Begins at about 30°C, only lghty howe tom trperstre Ths gives ise 1 problems associated withthe growth of GaAs lye tht stb esc both nein hs ape z well ta ater chiper on pital govt “svi exile consider Figure 23, which shows the pase dagra forthe AS-Si sytem ls), White the suctre looks quite complicated wit Several diferent sold phases mapped ot, ‘mcroletronic apis ae primaiyilerested inthe low arsenic concentration fim. Even try bevily ope sco is normal Tes than 58 arsenie. Novice at there sony very small Tezlon in which As will disole ln slicon at» dopat without forming a compound. The maxima Concetrion of an nary tat an be dsolved a anther material under exuibvium conditions is ited the soi solubility. Notice tht the wold solabliy increases athe temperature approsches {OTC whore it is aut & atc percent, soa that inthis eon a vera! ine will actully ine cree curves The poton of te lne hat goes frm © omic peremt As at SOC Yo 4 fomnic Perce Asa 1OS7C is ead the solas cure, represents soubliy. Te remaing two ies The whe sls and ligula esesively. The sod solubility of Asin St is comparatively Ize rer, and i means tat As i be ued 0 form very heavy dope and therefore ow resistance ‘elon such at source sd din contacts for MOS transistor (Chapter 16) and emit and colesoe ‘onars wotpolrvarsisors (Chapter 18. Since tn the sid slubiity rom the phe dag hat {sot primary ineest for dapat impor, and he soli obit varies by des of mages ur fernt mgs in icon, he poe diagram nforeatin for amber of common dopants in siicon have been combined (5} on aserilog pet is Figure 24 220,soganhy Cal Sesse 13 en caarreve Figure 2.2. Phase ng fc Gah (carn of ASM ernst Consider what happens inthe elongata, A sicon Wafers heed to 105°C and dps 0 3.5% atomic with As Doping msthade wil begin to be doused in the next chapter. puny co ‘ttrton ar normally expreued in camber permit volune.A 3.8% ame Coneencation asic. ‘comespons 01.75% 10" cm The ps diagram indicts tht asthe wate is ook twill eve: tually exceed th maximim cogceation tha can be in Slat ora thermodyasic ‘iri, the excess Asta condense ot, cite by coming ob ofthe sre oso ely. by forming sl preiptats in he sioun esta Fr thi to happen the Assos must be mie ine {ys the wafers cooked apd enowgh he precipitates cana orm, and a higher conceniaion ‘of pris dan ter ynaiclly lowes ca be omen in. Metallurg efer tos proces as (qunching. Tis an impertantconsieration oe in mind. Doping concentrations ean sod fen {Ec cece the sol sclutay, This is doe by beating & wafer with excess dopant sews and hen ‘oolng pid Prakconeetaton can exceed Ce sold slit by a actor of 10 oF mar. 2.2 Crystallography and Crystal Structure” ‘Cras re described by their most bese stratrl element the ont cll. crystal is simply 80 fy ofthese cel, repeated in very reguor manner over tve dimesios. The unit el merest —<—<$<—<— <<< —<—<—<—————————— rr wt ecactanee ae swe a lave i a a a a a a onic eet ste os Figure 23. Pine singrm for Ar SL (cours of ASM Internatio Ive cai prety with each ee ofthe unit el Being the same length, Figce 2S sbows thee Simson per of cuiceqysals. The sirection ina crystal re etd sing Cran coordinate Suen a [ea For eae cys the fares ofthe cel form plans that are perpecalar othe rer or he condinate sysea The symbol (xy) used to denote «patil plane that is pspe: ‘Ecutr wo te vector bat points rom he ogi long the [2] ection, Figur 2.5B shows several Gonmue cya icin, The sctof cubes and ¢ at reused 10 dese planes i this : (tanner ur called the Miler indices ofa plane. They are found fora sven plane by taking the [Dvr of te points a which te pla a guesion crosses the three coorinae axes, hen mii ing by the smalet pousbl facioro wake x,y aod ziteger. The notation (x2) i so wed 10 ‘epreen rysal planes, This presentation i meant include not ony the given plane, bu also lt ‘Caisson planes, For example in a rstal with ub symmetry, the (100) plane wil ave exactly ‘Sotume properties the (O10) and (01) plans. The ony eifference i an abitray choice of coor: inate syste, The notation {10} refers tal te. “Ficon and germanium are bod Groep TV elements. They have for valence electons and cod four more to complete thelr vlene shall. In ry, hs i done by forming covalent bonds 1 four acuest eighbor toms, None ofthe bse cube tates in Figure 2.5 would therefore {eppprine. The simple cubl cys has sx newest meighbors, the body centred cubic (BCC) as eg nd the fee entered cube (PCC) has 12. Instead, Group TV xemiconducos fom in the 22oysaicgpy ad Cyl Sree 15 ce 1" Concannon) Figure 24 Sclid slit of somo sco mpi (al igh reseed erin wh permision. ©1960 AT & 7, 40 Tel Be ‘ipiete Sayeeda Fare cent te o » Figre 25 (9) Gomme ct ig i Tice cer and aceenor case) Cy ‘orientations in the evbie sytem, ae Fue 28 Te cinmoat cite Fue 27. singe aa LO (Deen ond 2am Sees Gamoad strctte shown in Figure 25 The ont cll can be consruced by starting with an FCC cel and ‘ding four dion some Ite length ofeach ie fn. the Foor addins ste ae load ta, 12/9), al, 3, a), (alo a) and a, eld Sal), Tis cyst stetare ce alo e though of 2 ‘wo ftesoeking FCC latioes. Gas ao formes inthis sine arzagemeat, however, when (elements ae prose theerystal has veced lel of syne. ‘The secure ten called chiens. 2.3 Crystal Defects Semicondocior wafers are highly pefoct single on tus, Nevers, est detects ply an import tole in semiconductor fatvicaton. Semiconditor fects of imperfections, can be divided ito four 'ypes depending on thir ieasionality. Point defects do nc extend any ection, Line defects extend in ‘one sitecton “rough the crystal. Ane sd volume defects are 2 and -D defect, epectively. Each ‘ype fart ute diferent arent of Be favieation pce, Pint defects are cxtemey impor sotto the understanding of doping ad diftosion. The prevention of ine defects important to ay ‘heal procesig, paula in pid heal processing. Vola deft a play wef le in YeKlenginerag, Figure 27 shows afew ofthe mot important semiconductor deft ‘One ofthe most canon pes of pin defect lie site without an som Tis defects 3 ‘vacancy. A chely related point defect i at ao du resides wot on alatic it, bi the spces betwen the atic poston. [rele fo as an inka the inertial atom oof he Same smatril asth los inte lace it a seltteri n sore cate, the neal comes om 4 ‘eary vacancy. Such a vacacy interstitial combination i elle Fen eect might also migra tote surface ofthe wer wher nist ‘Vacancies and e'neesials are ininsie defects Just ab one tls shout inc caries in sericondsctors, at none tempest inns ‘defects wll tend to ocurin an otherwise perfect cyst Thermal excitation ° ‘reas a very sal percentage of electrons at hoes na semiconductor. Wil also remove a Small ner of atoms from their lic ies, eaving o fect. Te ners or vacancy may nt remain lhe site at which was Feet ecg mek Bahonsol ics an move trek te eal pry ote SS SSS te cee ons il ie meetin fatto te * 3233 behind vacancies Gover. the vacancy conceotaion is given by a8 Anis uncon which fs egeton of the fre. enerr en there she number density of stom inthe ryt ace (5.02% 10

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