Introduction to

CMOS VLSI
Design

Lecture 5:
Logical Effort
David Harris

Harvey Mudd College

Spring 2004

Outline
q
q
q
q
q
q

Introduction
Delay in a Logic Gate
Multistage Logic Networks
Choosing the Best Number of Stages
Example
Summary

5: Logical Effort

CMOS VLSI Design

Slide 2

Introduction
q Chip designers face a bewildering array of choices
What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?

???

q Logical effort is a method to make these decisions

Uses a simple model of delay
Allows back-of-the-envelope calculations
Helps make rapid comparisons between alternatives
Emphasizes remarkable symmetries

5: Logical Effort

CMOS VLSI Design

Slide 3

Example
q Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]

32 bits

5: Logical Effort

CMOS VLSI Design

16 words

4:16 Decoder

q Decoder specifications:
16 word register file
Each word is 32 bits wide
Each bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors
q Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?
16

Register File

Slide 4

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

5: Logical Effort

12 ps in 180 nm process
40 ps in 0.6 m process

CMOS VLSI Design

Slide 5

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

q Delay has two components

d= f +p

5: Logical Effort

CMOS VLSI Design

Slide 6

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

q Delay has two components

d= f +p
q Effort delay f = gh (a.k.a. stage effort)
Again has two components

5: Logical Effort

CMOS VLSI Design

Slide 7

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

q Delay has two components

d= f +p
q Effort delay f = gh (a.k.a. stage effort)
Again has two components
q g: logical effort
Measures relative ability of gate to deliver current
g 1 for inverter
5: Logical Effort

CMOS VLSI Design

Slide 8

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

q Delay has two components

d= f +p
q Effort delay f = gh (a.k.a. stage effort)
Again has two components
q h: electrical effort = Cout / Cin
Ratio of output to input capacitance
Sometimes called fanout
5: Logical Effort

CMOS VLSI Design

Slide 9

Delay in a Logic Gate

q Express delays in process-independent unit

d abs
d=

q Delay has two components

d= f +p
q Parasitic delay p
Represents delay of gate driving no load
Set by internal parasitic capacitance

5: Logical Effort

CMOS VLSI Design

Slide 10

Delay Plots
d =f+p
= gh + p

2-input
NAND

NormalizedDelay:d

Inverter
g=
p=
d=

g=
p=
d=

4
3
2
1
0
0

ElectricalEffort:
h = Cout / Cin
5: Logical Effort

CMOS VLSI Design

Slide 11

Delay Plots
d =f+p
= gh + p

NormalizedDelay:d

q What about
NOR2?

2-input
NAND

Inverter

g=1
p=1
d= h+1

EffortDelay:f

g = 4/3
p=2
d = (4/3)h + 2

Parasitic Delay: p
0
0

ElectricalEffort:
h = Cout / Cin
5: Logical Effort

CMOS VLSI Design

Slide 12

Computing Logical Effort

q DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
q Measure from delay vs. fanout plots
q Or estimate by counting transistor widths
2

2
A

Y
1
Cin = 3
g = 3/3

5: Logical Effort

2
Cin = 4
g = 4/3
CMOS VLSI Design

4
Y
1

Cin = 5
g = 5/3
Slide 13

Catalog of Gates
q Logical effort of common gates
Gate type

Number of inputs
1

NAND

4/3

5/3

6/3

(n+2)/3

NOR

5/3

7/3

9/3

(2n+1)/3

4, 4

6, 12, 6 8, 16, 16, 8

Inverter

Tristate / mux
XOR, XNOR

5: Logical Effort

CMOS VLSI Design

Slide 14

Catalog of Gates
q Parasitic delay of common gates
In multiples of pinv (1)
Gate type

Number of inputs
1

NAND

NOR

2n

Inverter

Tristate / mux
XOR, XNOR

5: Logical Effort

CMOS VLSI Design

Slide 15

Example: Ring Oscillator

q Estimate the frequency of an N-stage ring oscillator

Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
Frequency:
5: Logical Effort

g=
h=
p=
d=
fosc =
CMOS VLSI Design

Slide 16

Example: Ring Oscillator

q Estimate the frequency of an N-stage ring oscillator

Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
Frequency:
5: Logical Effort

31 stage ring oscillator in

g=1
0.6 m process has
h=1
frequency of ~ 200 MHz
p=1
d=2
fosc = 1/(2*N*d) = 1/4N
CMOS VLSI Design

Slide 17

Example: FO4 Inverter

q Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:

5: Logical Effort

g=
h=
p=
d=

CMOS VLSI Design

Slide 18

Example: FO4 Inverter

q Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:

g=1
h=4
p=1
d=5

The FO4 delay is about

200 ps in 0.6 m process
60 ps in a 180 nm process
f/3 ns in an f m process

5: Logical Effort

CMOS VLSI Design

Slide 19

Multistage Logic Networks

q Logical effort generalizes to multistage networks
q Path Logical Effort
G=
gi

Cout-path

q Path Electrical Effort

H=

q Path Effort

F = f i = gi hi

10
g1 = 1
h1 = x/10
5: Logical Effort

x
g2 = 5/3
h2 = y/x

Cin-path

y
g3 = 4/3
h3 = z/y
CMOS VLSI Design

z
g4 = 1
h4 = 20/z

20

Slide 20

Multistage Logic Networks

q Logical effort generalizes to multistage networks
q Path Logical Effort
G=
gi

Cout path

q Path Electrical Effort

H=

q Path Effort

F = f i = gi hi

Cin path

q Can we write F = GH?

5: Logical Effort

CMOS VLSI Design

Slide 21

Paths that Branch

q No! Consider paths that branch:
15

G
H
GH
h1
h2
F

=
=
=
=
=
= GH?

5: Logical Effort

90

5
15

CMOS VLSI Design

90

Slide 22

Paths that Branch

q No! Consider paths that branch:
15

G
H
GH
h1
h2
F

=1
5
= 90 / 5 = 18
= 18
= (15 +15) / 5 = 6
= 90 / 15 = 6
= g1g2h1h2 = 36 = 2GH

5: Logical Effort

CMOS VLSI Design

15

90

90

Slide 23

Branching Effort
q Introduce branching effort
Accounts for branching between stages in path

b=

Con path + Coff path

Con path

B = bi

Note:

h = BH
i

q Now we compute the path effort

F = GBH

5: Logical Effort

CMOS VLSI Design

Slide 24

Multistage Delays
q Path Effort Delay

DF = f i

q Path Parasitic Delay

P = pi

q Path Delay

D = d i = DF + P

5: Logical Effort

CMOS VLSI Design

Slide 25

Designing Fast Circuits

D = d i = DF + P
q Delay is smallest when each stage bears same effort

f = gi hi = F

1
N

q Thus minimum delay of N stage path is

1
N

D = NF + P
q This is a key result of logical effort
Find fastest possible delay
Doesnt require calculating gate sizes
5: Logical Effort

CMOS VLSI Design

Slide 26

Gate Sizes
q How wide should the gates be for least delay?

f = gh = g CCoutin
giCouti
Cini =
f
q Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
q Check work by verifying input cap spec is met.
5: Logical Effort

CMOS VLSI Design

Slide 27

Example: 3-stage path

q Select gate sizes x and y for least delay from A to B

x
x
A

5: Logical Effort

CMOS VLSI Design

y
45
y

45

Slide 28

Example: 3-stage path

x
x
A

y
45
y

Logical Effort
Electrical Effort
Branching Effort
Path Effort
Best Stage Effort
Parasitic Delay
Delay
5: Logical Effort

45

G=
H=
B=
F=

f =

P=
D=
CMOS VLSI Design

Slide 29

Example: 3-stage path

x
x
A

y
45
y

Logical Effort
Electrical Effort
Branching Effort
Path Effort
Best Stage Effort
Parasitic Delay
Delay
5: Logical Effort

45

G = (4/3)*(5/3)*(5/3) = 100/27
H = 45/8
B=3*2=6
F = GBH = 125

f = 3 F = 5

P=2+3+2=7
D = 3*5 + 7 = 22 = 4.4 FO4
CMOS VLSI Design

Slide 30

Example: 3-stage path

q Work backward for sizes
y=
x=
x
x
A

5: Logical Effort

y
45
y

CMOS VLSI Design

45

Slide 31

Example: 3-stage path

q Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
N: 4

5: Logical Effort

P: 4
N: 6

CMOS VLSI Design

P: 12
N: 3

45

Slide 32

Best Number of Stages

q How many stages should a path use?
Minimizing number of stages is not always fastest
q Example: drive 64-bit datapath with unit inverter
InitialDriver

D =

DatapathLoad
N:
f:
D:

5: Logical Effort

CMOS VLSI Design

64
1

64
2

64
3

64
4

Slide 33

Best Number of Stages

q How many stages should a path use?
Minimizing number of stages is not always fastest
q Example: drive 64-bit datapath with unit inverter
InitialDriver

2.8

16

D = NF1/N + P
= N(64)1/N + N

23
DatapathLoad
N:
f:
D:

5: Logical Effort

CMOS VLSI Design

64
1
64
65

64
2
8
18

64
3
4
15

64

4
2.8
15.3
Fastest

Slide 34

Derivation
q Consider adding inverters to end of path
How many give least delay?
Logic Block:
n1Stages
Path Effort F

n1

D = NF + pi + ( N n1 ) pinv
1
N

N - n 1 ExtraInverters

i =1

1
1
1
D
= F N ln F N + F N + pinv = 0
N

q Define best stage effort

=F

1
N

pinv + (1 ln ) = 0
5: Logical Effort

CMOS VLSI Design

Slide 35

Best Stage Effort

q

pinv + (1 ln ) = 0 has no closed-form solution

q Neglecting parasitics (pinv = 0), we find = 2.718 (e)

q For pinv = 1, solve numerically for = 3.59

5: Logical Effort

CMOS VLSI Design

Slide 36

Sensitivity Analysis
D(N) / D(N)

q How sensitive is delay to using exactly the best

1.6
number of stages?
1.51
1.4

1.26

1.2

1.15

1.0
( =2.4)

( =6)

0.0
0.5

0.7

1.0

1.4

2.0

N/N

q 2.4 < < 6 gives delay within 15% of optimal

We can be sloppy!
I like = 4
5: Logical Effort

CMOS VLSI Design

Slide 37

Example, Revisited
q Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file.
A[3:0] A[3:0]

32 bits

5: Logical Effort

CMOS VLSI Design

16

Register File

Slide 38

16 words

4:16 Decoder

q Decoder specifications:
16 word register file
Each word is 32 bits wide
Each bit presents load of 3 unit-sized transistors
True and complementary address inputs A[3:0]
Each input may drive 10 unit-sized transistors
q Ben needs to decide:
How many stages to use?
How large should each gate be?
How fast can decoder operate?

Number of Stages
q Decoder effort is mainly electrical and branching
Electrical Effort:
H=
Branching Effort:
B=
q If we neglect logical effort (assume G = 1)
Path Effort:
F=
Number of Stages:

5: Logical Effort

N=

CMOS VLSI Design

Slide 39

Number of Stages
q Decoder effort is mainly electrical and branching
Electrical Effort:
H = (32*3) / 10 = 9.6
Branching Effort:
B=8
q If we neglect logical effort (assume G = 1)
Path Effort:
F = GBH = 76.8
Number of Stages:

N = log4F = 3.1

q Try a 3-stage design

5: Logical Effort

CMOS VLSI Design

Slide 40

Gate Sizes & Delay

Logical Effort:
Path Effort:
Stage Effort:
Path Delay:
Gate sizes:
A[3] A[3]
10

10

A[2] A[2]
10

10

A[1] A[1]
10

10

G=
F=

f =
D=
z=

y=

A[0] A[0]
10

10

word[0]
96 units of wordline capacitance

5: Logical Effort

word[15]

CMOS VLSI Design

Slide 41

Gate Sizes & Delay

Logical Effort:
Path Effort:
Stage Effort:
Path Delay:
Gate sizes:
A[3] A[3]
10

10

A[2] A[2]
10

10

A[1] A[1]
10

10

G = 1 * 6/3 * 1 = 2
F = GBH = 154

f = F 1 / 3 = 5.36
D = 3 f + 1 + 4 + 1 = 22.1

z = 96*1/5.36 = 18

y = 18*2/5.36 = 6.7

A[0] A[0]
10

10

word[0]
96 units of wordline capacitance

5: Logical Effort

word[15]

CMOS VLSI Design

Slide 42

Comparison
q Compare many alternatives with a spreadsheet
Design

NAND4-INV

29.8

NAND2-NOR2

20/9

30.1

INV-NAND4-INV

22.1

NAND4-INV-INV-INV

21.1

NAND2-NOR2-INV-INV

20/9

20.5

NAND2-INV-NAND2-INV

16/9

19.7

INV-NAND2-INV-NAND2-INV

16/9

20.4

NAND2-INV-NAND2-INV-INV-INV 6

16/9

21.6

5: Logical Effort

CMOS VLSI Design

Slide 43

Review of Definitions
Term

Stage

Path

number of stages

logical effort

G = gi

electrical effort

h=

Cout
Cin

H=

branching effort

b=

C on-path + Coff-path
C on-path

B = bi

effort

f = gh

F = GBH

effort delay

DF = f i

parasitic delay

P = pi

delay

d= f +p

5: Logical Effort

CMOS VLSI Design

Cout-path
Cin-path

D = d i = DF + P

Slide 44

Method of Logical Effort

1)
2)
3)
4)
5)

Compute path effort

Estimate best number of stages
Sketch path with N stages
Estimate least delay
Determine best stage effort

N = log 4 F
1
N

D = NF + P
f = F N1

gi Couti
Cini =
f

6) Find gate sizes

5: Logical Effort

F = GBH

CMOS VLSI Design

Slide 45

Limits of Logical Effort

q Chicken and egg problem
Need path to compute G
But dont know number of stages without G
q Simplistic delay model
Neglects input rise time effects
q Interconnect
Iteration required in designs with wire
q Maximum speed only
Not minimum area/power for constrained delay

5: Logical Effort

CMOS VLSI Design

Slide 46

Summary
q Logical effort is useful for thinking of delay in circuits
Numeric logical effort characterizes gates
NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ~4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesnt mean faster paths
Delay of path is about log4F FO4 inverter delays
Inverters and NAND2 best for driving large caps
q Provides language for discussing fast circuits
But requires practice to master
5: Logical Effort

CMOS VLSI Design

Slide 47