PART I: SOLUTIONS CHAPTER L (Components of a computer: ALU and Control Unit (CPU), Memory, Input, and Output. Functions of various components: CPU: It processes and stores binary data, wansfers data from and to memory and VO devices, and provides timing to all the operations. It includes ALU, register arrays, and control unit. ‘The ALU perfonns the arithmetic and logic operations, and the control unit provides timing. ‘Input - provides binary data as an input to the CPU. Output - accepts binary data from the CPU. A microprocessor functions as the CPU of a microcomputer, and includes the ALU, register arrays, and the control unit on one chip; itis manufactured using the LSL technology. On the other hand, the CPU is designed with various discret boards, Functionally, beth are similay however, technology and processes used for designing is different A microprocessor is one component of a microcomputer, and the microcomputer is ‘complete computer consists of a microprocessor, memory, input, and output ‘See Summary: Scale oF Totagration Four bytes. ‘The machine language of the 8085 are the comamands to the microprocessor given in binary. ‘These are the binary instructions the processor can understand and execute. ‘The assembly language comprise of mnemonics (group of letiers to represent commands) assigned by the ‘manufacturer for the convenience of the users, 9, 10, 11, See Summary: Computer Languages 2. ‘The assembly language mnemonics represent instructions to the microprocessor: therefore. when they are wanslated into machine language, there is one-to-one correspondences between the mnemonics and the machine code. The assembly language programs are compact, require less memory space, and are efficient. ‘The high level languages arc written, in English- like statements, and when these statements are translated in machine language, the ‘object code tends to be large. and requires large memory. ‘The execution of the programs ‘written in high level languages is less efficient than that of assembly language programs13, 14. See Summary: Computer Languages 15. 16, ASCII codes in Hex: A= a1, 5A, and m=6D s Summary: Computer Languages CHAPTER? 1 2 10 12, Memory Read, Memory Write, VO Read, and U0 Wate, A bus is group of ines (wires or conductors) which cary digital informasion, “The function ofthe address busi to camy’a binary address of'a memory jcation or an YO device. ‘The address bus is unidirectional, and dhe information flows from the MPU t9 ‘peripherals and memory _A microprocessor with 14addreas lines is capable of addressing 16K (2) memory locations 21 adress tines. ‘Data bytes are transferred in both dizetions between the MPU and memory/perpheral. TOR (VO Read), 1OW (VO Write), MEMR (Memory Read), end MEMW (Memory Writ). In memory write operation, the control siznal required is MEMW, and the dirotion of the data flow is fom the MPU to memory. ‘The accumulators an 8-bitregister and itiea partof the ALU. All8-bt arithmetic and logic ‘operations are performed in relation to the accumulator content, and theresult i storedin the steurnulator (with a few exceptions) A fing i the output of a given Mip-flop to indieate certain data conditions. ‘The program counter and the stack pointer store memory sddresses of 16 bits. ‘The program counter always points to the next memory Tocation; therefore, the content of the program counter will be 2055H. 128 registers and 128 X4 = 512 memory cells. 1024 bits are can be stored by this chip; however, it can not be specified as 2 128-byte _memary chip because the byte indicates § bit memory registers; this chip has 4-bit registers.15, 16. v7. 18. 18. 21 2, 2 2, 2s. 26 21, 28, 29, 30, 3 32. 33. 34 .bit wort size, 8 chips. 4 chips 32 chips ‘The WR signal enables the input buffer of a memory chip co that information can be stored (orien) in the selected memory register 1 address tines, ‘The staring address is FBOOH, and the memory map is FSO0H to FBFFH. “The staring adress ie: BOOOH. ‘The address ranges fom FFOOH to FFFFH. “The address ofthe selected register: 1000 0000 0100 0111 = $0474 ‘The memory map ranges fora 2000H to 23FFH. “The address of the selected register: 0010 0000 1111 1000 = 20F8H4 8 address lines are required for a peripheral UO port, aad 16 address lines are required fr a memory-mapped VO por ‘Tri-state devices ae logie devices with tee states; the third state is high impedance, In a ‘bus-orlented system, devices are connected in parallel, and the buses are capable of diving fone TTL logic device. The MPU communicates with one peripheral at a time, snd other peripherals are placed in high impedance to avoid bus loading High impedance state. From B10 A. None. The decoder is not enabled: all output lines will be hi “The line 6 (00, 001 (Complement of 1 10)35, ‘A transparent latch ga flip-flop; its ouput changes according to input when the lock signal is high, and it latches the input when the elock goes low. The latch is necessary for output devices to rotain the result, otherwise, the resule will disappear. 36. The high-order address lines: A12-A1S, the low-order address lines: AO-A10, and the don't care line: ALL 37. ‘This answer assumes the memory chips are 2048 X 4: AIS AI4AI3 AZ ALL ALO AS AS A7 AG AS A4.A3 AZ. AL AG 1 1 1 1 0 000000000 0 o=F00oH 1 | borot ab aad ad abd tad PRE 38. The memory occupics the memory space ftom FOOOH to FFFFEL The don't care line ALL ‘gencrates additional address range. This is a 2K memory chip that oceupies 4K of memory Space in the map, thus wasting 2K of memory space. IF A1 is assured to be at logic O as in @. 27, the address range is: FOOOH to F7FEH and if tis assumed to be at logic 1, the [adress range (also called foldback memory space) is: F800H to FFFFH. CHAPTER 3 “The ALE signal goes high at the boginning of each machine cycle indicating the availability ‘of an address on the address bus, and the signal is used to latch the low-order address bus. ‘The 1O/M signal ie a satus signal indicating whether the machine cycle is VO or memory ‘operation. ‘The TO/M signal is combined with the RD and WR control signals to generate TOR, 1OW, MEMR and MEMW control signals. ‘The low-order bus AD7-ADO is used for two purposes. In the carlcr part of a machine ceyele, the bus is used forthe low order address of a memory location the 808S is accessing. fad in the latter part of the cycle the bus ie used for data. By demultiplexing the bus, he ‘Madress and the data are kept separate. 1n Fig. 3.2, the input signal RD ané WR cannot be low atthe same time. Therefore, the ‘valid combinations ofthe input signals ae:u 2. 13. M4. JOM RD WR Output Signat © 9 0 Oy nvalid. «RD sn WR cannot be active simultaneously © 9 1G) MEM Mond RD ctive © 1 0) MEMW Mand WR active © 1 1G, relevant Both RD and WR are inactive 10 6 Invalid RD and WR cannot be active imultancously 1 0 Lt oO TOR IO and RD active 1 1 0 & TOW 10 and WR active 2 1 1G) eelevant Both RD and WR are inactive See the answer of 03. {In Fig, 323, the 7415139 is enabled when 1O/M is low, Therefore, the following memory ‘contol signale cat be generate. RD WR Decoder Output © 0 Oy-tnvaid © 1 0) MEM 10 O.-MEMW 11 O,-No operation ‘The cutput of the latch will be OSH; however, it will be mot be latched until the ALE goet low. ‘The output of the latch is OSH. At T2, the ALE i low; therefore, the latch will ot be enabled, and it will continue te hold the previously latched byte (OSE). ‘The crystal frequency should be ~ 2.2 MHz because the oscillator logic divides the input requency by tw. See the steps on page 66/67, Exsenple 3.1 ‘The sum of 87H + 79H = 10GH. Therefore, the accumulszor will have OOH. and the as willbeS=0,C¥=1.2=1 2060H. The program counter always points to the next machine code tobe fetched. IST X 2 micro-tec = 2.6 miero-see (ALS.A8)= 20H, (AD?-ADO)= 47H, (PC) = 2076 RD and JOM are asserted low. as19. 20. 2 23, 25, 26. 28. ‘The second machine eycle is Memory Read; the processor reads the contents of memory in register B, and the control signal is RD, “The fourch machine eyele is Memory Read; the processor reads the contents of memory in the accuanlator. (A15-A0) = 2050, (AD7-ADO) as data bus = Contents of location 205014 (Refer to Instruction Sot on pages 696-659) SUB BOF (Opeode Fetch) ADI 47H = OF, MR (Memory Read) ‘STA 20501 ~ OF, MR, MR, MW (Memory Write) PUSHB = OF, MW, MW. ‘Memory map: 6000H to 6FFFH. ‘Memory map: S000H to 8FFFH OR gate Connect RD to OF of the memory chip and IO/M to F2 of the decoder. AISAISAISAIZ Al A109 ABA7 AGAS ASA A2 AL AO 0 0 1 6 1 6 60 6 00 00000 =2800% 1 H Bobb aaa aaa aren ‘Total range 16K. Map = S000H to BFFFEL A data byte entered at location 2100H will be accepted and stored at location 2000H. The ‘adavees lines 410, AO, and AS aronotbeing used for memory addressing: therefore, they can ‘assume 0 of 1 (dont care) logie state wich results into multiple addresses forthe same ‘memory locations ‘Memory address: 0800H-OSFFH, and the foldback memory ranges from 0900 to OF FFE. ‘Memory map: 3800H - 3FFFEL {In Figure 3.19, tree lines are dant care which can have (2) eight combinations. This the ‘memory chip Will occupy the memory space equal to oight times is size ROMI: 0000H - LFFFH, ROM2: E0001 - FFFFH, R/WMI: 8000# - S3FFH