SEMICON Solutions

Thit k mch tun t

Trnh by: ng Tng Dng

Mch t hp

Th no l my bin trng thi

M hnh Mealy
Output da vo
trng thi v input
hin ti

s(t+1)
C1
x(t)

trng thi
k tip

State Register

init

input
hin ti

clk

s(t)
trng thi
hin ti

z(t)

C2

M hnh Moore
Output ch da vo
trng thi

s(t+1)
C1
x(t)
Input
hin ti

trng thi
k tip

State Register

init

clk

z(t)
s(t)
trng thi
hin ti

C2

V d v mch tun t

Output

V d v mch tun t
A(t+1)
=DA = AX + BX
B(t+1)
=DB = AX
Y = (A + B)X

Bng trng thi

2 chiu

S trng thi

S dng s trng thi

Thit k my trng thi dng

J-K Flip Flop

Using J-K Flip Flops

JA = B
JB = X

KA = BX
KB = AX + AX

Thit k mch tun t

Thc hin s trng thi ca bng trng thi t yu cu ca mch trng thi.

Nu ch c 1 biu trng thi sn sng, th thc hin bng trng thi.

Dng m nh phn cho cc trng thi.
Phng trnh input Flip-Flop bt ngun trong mc trng thi k tip trong bng m
ha trng thi.
Phng trnh output Flip-Flop bt ngun t mc output trong bng m ha trng
thi.
n gin ha phng input v output .

V s logic vi DFF v cc cng , c th ha cc input v output trong DFF.

VD: sp xp tun t
Chng ta cn nhng bit ng vo ln lt 1101.

Nu u vo l A = 1 trng thi A chuyn sang trng thi B v output ca A l 0

(khng pht hin c bit 1101)

bit u tin
L A l 1

Nu chng ta ang trng thi B

(iu ny c ngha l rng chng ta
c a = '1 ngay lp tc trc v
input k tip l a = 1 Sau chng
ta tm cch lm cho c thnh cng
bit 1101 sau chuyn sang trng
thi C

Bit tip theo, chng ta c chui 1101 tip theo l

chui 0 nu chng ta c l 0 th chuyn sang
trng thi D --nu bo rng vn bng 0 , chng ta
cha c c chui

Sau trng thi D, chng ta thnh cng

nu A = 1 c c v tin hnh. u
ra s l mc cao hoc 1.

Chng ta t output
mc cao sau
chuyn sang trng thi B

Chng ta khng cn tin hnh sang trng thi E, cho d, nu

chng ta nhn ra 1101, chng ta khng nhng pht hin
1 chui bit m cn bit cch pht hin chui 1101 khc.
dng nh 1101101.
2 chui

S trng thi

Coding my trng thi

Hng dn

Tch ri din t my trng

thi thnh 2 quy trnh
Mch t hp
Mch tun t

Dng din t `define

nh ngha vector trng thi.

Gi logic FSM v logic

non-FSM trong nhng
module tch ri.

Gn gi tr mc nh
cho my trng thi.

bt u 0

bit th 2 l 0

bit th 3 l 1
ngha l
Chng ta
c chui
111
. iu ny ch
i
chng ta t 1
bit 0
A 0 l bit cui cng ( A 0 is the last bit (1100) v tr li ban u

Chng ta cn phi t trng thi tht bi, khi khng c c bit 1101

Bi Tp

Thit k s mch s dng DFF

Vit Verilog cho mch va thit k

Cu Hi & Tr Li