SOC System on Chip

Verification with System Verilog

8/17/15

VLSI/Chip Design Flow

Design Specifications
Design Entry (Schematic/HDL)

Floor
Planning

Static
Timing
Analysis

Functional Verification & Power Analysis

Logic & Test Synthesis
Gate
Level
Simulation

Formal
Verification

Technology
Library
Power
Estimation

Floor Planning & CTS

Layout Design
Placement & Routing
SDF &
Parasitics

Front End
Back End

Physical Verification
8/17/15

Tapeout

Tapeout
Verification
2
with System Verilog

Verification Signoff

 Now lets start our learning

towards the actual objective of

our course.

Verification with System Verilog

8/17/15