Contents

Assignment 1-A ......................................................................................................................................2

(A) 1) Simulate n bit ripple carry adder using Modelsim/NCSim/QestaSim simulator for n=8, 16, 32, 64...2
Simulation for n=8 bit ripple carry adder.............................................................................................. 3
Simulation for n=16 bit ripple carry adder ............................................................................................ 3
Simulation for n=32 bit ripple carry adder ............................................................................................ 3
Simulation for n=64 bit ripple carry adder ............................................................................................ 3
(A) 2) Simulate n bit ripple carry adder using Modelsim/NCSim/QestaSim simulator for n=8, 16,32, 64 .......4
Simulation for n=8 bit carry select adder.............................................................................................. 5
Simulation for n=16 bit carry select adder ............................................................................................ 6
Simulation for n=32 bit carry select adder ............................................................................................ 6
Simulation for n=64 bit carry select adder ............................................................................................ 6

Assignment 1-A
(A) 1) Simulate n bit ripple carry adder using Modelsim/NCSim/QestaSim
simulator for n=8, 16, 32, 64

//nBit Ripple Carry Adder with with parameter 8,16,32,64

module nRipple(a,b,s,0_flag );
parameter n = 8;
//generalized parameter 'n' for n bit adder
input
input

[n-1:0] a;
[n-1:0] b;

output [n-1:0] s;
output 0_flag;
wire [n-1:0] a;
wire [n-1:0] b;
wire [n-1:0] s;
wire 0_flag;
wire [n:0]c;
assign
c[0] = 1'b0;//Assign C input of first FA to zero.
//Using generate function to create instances of FA
generate
genvar i;
for(i=0;i<n;i=i+1)
begin : nbit
FA FAn(a[i],b[i],c[i],s[i],c[i+1]);//FA module instantiation
end
endgenerate
assign 0_flag = c[n]; //assign overflow value to 0_flag variable
endmodule
module FA(a,b,c,s,co );
input a;
input b;
input c;
output s;
output co;
wire y1,y2,y3;
xor a1(y1,a,b);
xor a2(s,y1,c);
and a3(y2,a,b);
and a4(y3,y1,c);
or a5(co,y2,y3);
endmodule

Simulation for n=8 bit ripple carry adder

Simulation for n=16 bit ripple carry adder

Simulation for n=32 bit ripple carry adder

Simulation for n=64 bit ripple carry adder

(A) 2) Simulate n bit ripple carry adder using Modelsim/NCSim/QestaSim

simulator for n=8, 16,32, 64
module CSA(a,b,c,s,c_out);
parameter n = 8;
input [n-1:0] a;
input [n-1:0] b;
output[n-1:0] s;
input c;
output
c_out;
wire
wire
wire
wire
wire

[n-1:0] s_0;
[n-1:0] s_1;
[n/4:0]carry_0;
[n/4:0]carry_1;
[((n/4)-1):0]c_sel;

//assign c_sel = c;
Ripple4 RA1(a[3:0],b[3:0],c,s[3:0],c_sel[0]);
//n bit adder generator with 4bit ripple carry blocks
generate
genvar i;
for(i=1;i<(n/4);i=i+1)
begin : nbit_carry_select
Ripple4
RA_C0(a[((4*i)+3):(4*i)],b[((4*i)+3):(4*i)],1'b0,s_0[((4*i)+3):(4*i)],ca
rry_0[i]);
Ripple4
RA_C1(a[((4*i)+3):(4*i)],b[((4*i)+3):(4*i)],1'b1,s_1[((4*i)+3):(4*i)],ca
rry_1[i]);
mux21_4bit
mux({carry_1[i],s_1[((4*i)+3):(4*i)]},{carry_0[i],s_0[((4*i)+3):(4*i)]},
c_sel[i-1],{c_sel[i],s[((4*i)+3):(4*i)]});
end
endgenerate
assign 0_flag = c_sel[(n/4)-1];
endmodule
module Ripple4(a,b,c,s,c_out);
//inputs
input [3:0] a;
input [3:0] b;
input c;
//outputs
output [3:0] s; // Sum of 'n' bits
output 0_flag; //Final overflow carry flag
wire
wire
wire
wire
wire

[3:0] a;
[3:0] b;
c;
[3:0] s;
c_out;

wire [2:0]ca;
FA FA1(a[0],b[0],c,s[0],ca[0]);
FA FA2(a[1],b[1],ca[0],s[1],ca[1]);
FA FA3(a[2],b[2],ca[1],s[2],ca[2]);

endmodule
module mux21_4bit(x,y,s,o);
input [4:0] x;
input [4:0] y;
input s;
output [4:0] o;
assign o = s?x:y;
endmodule

module FA(a,b,c,s,co);
input a;
input b;
input c;
output s;
output co;
wire y1,y2,y3;
xor a1(y1,a,b);
xor a2(s,y1,c);
and a3(y2,a,b);
and a4(y3,y1,c);
or a5(co,y2,y3);
endmodule

OUTPUT
Simulation for n=8 bit carry select adder

Simulation for n=16 bit carry select adder

Simulation for n=32 bit carry select adder

Simulation for n=64 bit carry select adder