MEMORY DESIGNING (26 hours) 2 credits

Unit 1:

6 Hours

Introduction: Overview of semiconductor memory types, Memory array organization.

Static Random Access Memory: SRAM Cell structure, various configurations of the SRAM
Cell. Read data path - Pre-charge circuitry, Isolation circuitry, Sense Amplifier.
Write driver circuit, Decoder circuitry.
Unit 2: Dynamic Random Access Memory:

5 Hours

DRAM types and operation: The 1K DRAM (First Generation), the 4K 64M DRAM (2nd
Generation), Synchronous DRAM (3rd Generation).

Unit 3: DRAM basics:

5 Hours

Access and sense operations, Write operation, Opening a row. DRAM Array Architectures:
Folded array, Open digitline array.

Unit 4:

5 Hours

Non-volatile memories: ROM, EEPROM, Flash, FeRAM, NVRAM, MRAM.

Content Addressable Memory: CAM topology, Binary CAM, Ternary CAM-static and
dynamic. Multiport memories.

Unit 5: Memory Faults:

5 Hours

Genaral Fault Modeling, Read Disturb Fault Model, Precharge Faults, False Write Through, Data
Retention Faults, Decoder Faults.

Reference Books:
1. R.Dean Adams, High Performance Memory Testing: Design Principles, Fault Modeling
and Self Test, Kluwer Academic Publishers, 2003.
2. Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin, DRAM Circuit Design:
Fundamental and High-Speed Topics, 2E, Wiley - IEEE press, 2007.

3. Sung-Mo Kang, Yusuf Leblebicii, CMOS Digital Integrated Circuits- Analysis and

Design 3rd Edition Tata McGraw-Hill.