ENEE 302H

Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.

ENEE 302H
Digital Electronics

SLIDE 1

Transistor Sizing I
Prof. Bruce Jacob
blj@ece.umd.edu

Credit where credit is due:

Slides contain original artwork ( Jacob 2004) as well as material taken liberally
from Irwin & Vijays CSE477 slides (PSU), Schmit & Strojwass 18-322 slides
(CMU), Dallys EE273 slides (Stanford), Wolfs slides for Modern VLSI Design,
and/or Rabaeys slides (UCB).
UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Overview

Bruce Jacob
University of
Maryland
ECE Dept.

Sizing of transistors to balance

performance of single inverter

More on RC time constant, first-order

approximation of time delays

Sizing in complex gates, examples

Sizing of inverter chains for driving high

capacitance loads (off-chip wires)

SLIDE 2

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ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing I

Bruce Jacob
University of
Maryland
ECE Dept.

Resistance of MOSFET:
1
L

R n = ---------------------------------------------- ---- n C ox ( V GS V Tn ) W

SLIDE 3

Increasing W decreases the resistance;

allows more current to flow

Oxide capacitance C ox = ox t ox [F/cm2]

Gate capacitance C G = C ox WL [F]
W
W
Transconductance n = n C ox ----- = k' n -----
L
L
(units [A/V2])
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ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing I

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 4

nFET vs. pFET

1
R n = ------------------------------------ n ( V DD V Tn )
1
R p = --------------------------------------- p ( V DD V Tp )
n
----- = r
p

n = n C ox ---- Ln
W
p = p C ox -----
Lp
Typically
(2 .. 3)

( is the carrier mobility through device)

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ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing I

Bruce Jacob
University of
Maryland
ECE Dept.

WOULD LIKE BALANCED NETWORKS:

VDD

SLIDE 5

Dual networks
Pull-up
Network
(pFET network)

INPUT/S

OUTPUT

Pull-down
Network
(nFET network)

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ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing I

Bruce Jacob
University of
Maryland
ECE Dept.

SIMPLE CASE: Inverter

VDD

VDD

SLIDE 6

Rp
CL

VOUT

VOUT

CL

CL

Rn
Charging: Vout rising

Discharging: Vout falling

If (W/L)p = r(W/L)n then n = p

(and Rn = Rp)
symmetric inverter
Make pFET bigger (wider) by factor of r
UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing I

Bruce Jacob
University of
Maryland
ECE Dept.

SIMPLE CASE: Inverter

VDD

VDD

SLIDE 7

Rp
CL

VOUT

VOUT

CL

CL

Rn
Charging: Vout rising

Discharging: Vout falling

tpLH = ln(2) Rp CL = 0.69 Rp CL

tpHL = ln(2) Rn CL = 0.69 Rn CL
tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2
(note: the ln(2)RC term comes from first-order analysis of simple
RC circuits respose to step input ... time for output to reach 50% value)
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ENEE 302H
Lecture/s 9
Transistor Sizing I

Wire Resistance

Bruce Jacob

University of
Maryland
ECE Dept.

w
r

SLIDE 8

UNIVERSITY OF MARYLAND

R = l/A = l/(wh) for rectangular wires

(on-chip wires & vias, PCB traces)
r2) for circular wires
R = l/A = l/(
(off-chip, off-PCB)
Material

-m)
Resistivity (

Silver (Ag)

1.6 x 10-8

Copper (Cu)

1.7 x 10-8

Gold (Au)

2.2 x 10-8

Aluminum (Al)

2.7 x 10-8

Tungsten (W)

5.5 x 10-8

ENEE 302H
Lecture/s 9
Transistor Sizing I

Sheet Resistance

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 9

/h for rectangular wires

R = l/(wh) = l/w
Sheet resistance Rsq = /h

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Material

/sq)
Sheet resistance Rsq (

n, p well diffusion

1000 to 1500

n+, p+ diffusion

50 to 150

polysilicon

150 to 200

polysilicon with silicide

4 to 5

Aluminum

0.05 to 0.1

ENEE 302H
Lecture/s 9
Transistor Sizing I

More on Resistance

Bruce Jacob
University of
Maryland
ECE Dept.

Sheet resistance Rsq

SLIDE 10

12 squares

6 squares

= 1sq + 1sq + 0.56sq

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= 1sq + 1sq + 0.2sq

ENEE 302H
Lecture/s 9
Transistor Sizing I

More on Resistance

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 11

(its not just the channel that counts)

UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Thats Reff, But What is CL?

Bruce Jacob
University of
Maryland
ECE Dept.

Vin

Vout
Vin

Vout2

CL

SLIDE 12

M2

Vin

Vin

CGD12

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M4

CDB2

Vout2

Vout

pdrain
ndrain

M1

CG4

Cw
CDB1

M3

CG3

intrinsic MOS transistor capacitances

extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance

ENEE 302H
Lecture/s 9
Transistor Sizing I

Two Chained Inverters

Bruce Jacob
University of
Maryland
ECE Dept.

VDD

PMOS
1.125/0.25

SLIDE 13

1.2m

=2
In

Out
Metal1

Polysilicon
0.125 spacing

NMOS
0.375/0.25

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GND
0.5 width

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 14

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CW, a Large Example

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 15

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CW, a Large Example

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.

Gate-Drain Capacitance CGD

VDD

PMOS
1.125/0.25

SLIDE 16

1.2m

=2
Out

In

Metal1

Polysilicon

NMOS
0.375/0.25

poly
0.125 spacing
SiO2

Scales with transistor width W

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GND
0.5 width

Overlaps

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob

Diffusion Capacitance CDB

VDD

University of
Maryland
ECE Dept.

PMOS
1.125/0.25

SLIDE 17

1.2m

=2
Out

In

Metal1

Polysilicon

NMOS
0.375/0.25

UNIVERSITY OF MARYLAND

Reverse-Biased
P/N Junction

p+

GND
n-doped substrate or well

Drain is reverse-biased diode, non-linear C dependent

on drain voltage (approx. nonlinearity with linear eqn,
using K terms for bottom plate and sidewalls)

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.

Gate/Fan-out Capacitance CG
VDD

PMOS
1.125/0.25

SLIDE 18

1.2m

=2
Out

In

Metal1

Polysilicon
poly
SiO
2
NMOS

0.125 spacing

0.375/0.25
0.5 widthPlate
Overlaps + Parallel

Scales with both W and L

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GND

ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 19

Two Chained Inverters: CL

C Term Expression

Value (fF) Value (fF)

HL
LH

CGD1

2 Con Wn

0.23

0.23

CGD2

2 Cop Wp

0.61

0.61

CDB1

KeqbpnADnCj + KeqswnPDnCjsw 0.66

0.90

CDB2

KeqbppADpCj + KeqswpPDpCjsw 1.50

1.15

CG3

2 Con Wn + Cox Wn Ln

0.76

0.76

CG4

2 Cop Wp + Cox Wp Lp

2.28

2.28

CW

From extraction

0.12

0.12

CL

Sum

6.1

6.0

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Terms in red: under control of designer

CL split between intrinsic and extrinsic/wire sources

ENEE 302H
Lecture/s 9
Transistor Sizing I

RC Delay, Two Inverters

Bruce Jacob

3
2.5

SLIDE 20

Vout (V)

University of
Maryland
ECE Dept.

Vin

1.5

tpHL

tf

tr

tpLH

0.5
0
-0.5
0

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0.5

VDD=2.5V, 0.25mm
W/Ln = 1.5, W/Lp = 4.5
( 1.5)
Reqn= 13 k
( 4.5)
Reqp= 31 k

t (sec)

1.5

2.5x 10

-10

tpHL = 0.69 RnC = 36 ps

tpLH = 0.69 RpC = 29 ps
From SPICE simulation:
tpHL = 39.9 ps, tpLH = 31.7 ps

ENEE 302H
Lecture/s 9
Transistor Sizing I

Transistor Sizing II

Bruce Jacob
University of
Maryland
ECE Dept.

SLIDE 21

Source

2W
L

L
Drain

The electrical characteristics of transistors

determine the switching speed of a circuit

Need to select the aspect ratios (W/L)n and (W/L)p of

every FET in the circuit

Define Unit Transistor (R1, C1)

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L/Wmin-> highest resistance (needs scaling)

R2= R1 2 and C2= 2 C1
Separate nFET and pFET unit transistors
Unit devices are not restricted to individual transistors

ENEE 302H
Lecture/s 9
Transistor Sizing I

Sizing II: Complex Gates

Bruce Jacob
University of
Maryland
ECE Dept.

Critical transistors: those in series

VDD

SLIDE 22

2 nets in series:
scale each by 2x
C
D

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Two devices
in series: scale
each by 2x
OUT

N FETs in series => scale each by factor of N

Ignore FETs in parallel (assume worst case: only 1 on)
Ultimate goal: total resistance of net = 1 square

ENEE 302H
Lecture/s 9
Transistor Sizing I

Sizing II: Complex Gates

Bruce Jacob
University of
Maryland
ECE Dept.

Critical transistors: those in series

VDD

SLIDE 23

2x1

2x1

2 nets in series:
scale each by 2x

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4x1

4x1

2x1

Two devices
in series: scale
each by 2x
OUT

N FETs in series => scale each by factor of N

Ignore FETs in parallel (assume worst case: only 1 on)
Ultimate goal: total resistance of net = 1 square

ENEE 302H
Lecture/s 9
Transistor Sizing I

Examples

Bruce Jacob

VDD

University of
Maryland
ECE Dept.
SLIDE 24

D
OUT
A
B

UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Examples

Bruce Jacob

VDD

University of
Maryland
ECE Dept.
SLIDE 25

A
C
D

VDD

OUT

UNIVERSITY OF MARYLAND

2
C

12 6

12

2
C

Assuming Wp = 3Wn

OUT

ENEE 302H
Lecture/s 9
Transistor Sizing I

Examples

Bruce Jacob

VDD
A

University of
Maryland
ECE Dept.

SLIDE 26

D
B
C
OUT
A

B
A

UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Examples

Bruce Jacob

VDD
A

University of
Maryland
ECE Dept.

SLIDE 27

18 6

18

18

OUT

UNIVERSITY OF MARYLAND

2 3

ENEE 302H
Lecture/s 9
Transistor Sizing I

Gate Delay, Revisited

Bruce Jacob
University of
Maryland
ECE Dept.

So far have sized the PMOS and NMOS so

that the Reqs match (ratio between 2 & 3.5)

SLIDE 28

symmetrical VTC
equal high-to-low and low-to-high propagation delays

If speed is the only concern, reduce the

width of the PMOS device!

widening the PMOS degrades tpHL due to larger

parasitic capacitance (intrinsic capacitance)

B = (W/Lp)/(W/Ln)

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r = Reqp/Reqn (resistance ratio of identically-sized

PMOS and NMOS)
Bopt r if wiring capacitance negligible

ENEE 302H
Lecture/s 9
Transistor Sizing I

Ways to Improve Gate Delay

Bruce Jacob

tp (tpHL + tpLH) [CL (k W/L VDD)]

University of
Maryland
ECE Dept.

Reduce CL

SLIDE 29

internal diffusion capacitance of the gate itself

(keep the drain diffusion as small as possible)
other terms: interconnect capacitance & fanout

Increase W/L ratio of the transistor

the most powerful and effective performance

optimization tool in the hands of the designer
watch out for self-loading! when the intrinsic
capacitance dominates the extrinsic load

Increase VDD

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can trade-off energy for performance

increasing VDD above a certain level yields only very
minimal improvements
reliability concerns enforce a firm upper bound on VDD

ENEE 302H
Lecture/s 9
Transistor Sizing I

Gate Delay, Revisited

Bruce Jacob
VDD

University of
Maryland
ECE Dept.

VDD

Rp
CL

SLIDE 30

VOUT

VOUT

CL

CL

Rn
LH scenario

HL Scenario

tp (tpHL + tpLH)

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widening the PMOS improves tpLH (Rp is lower)

but degrades tpHL (increases intrinsic capacitance
GGD and GDB)

widening the NMOS improves tpHL (Rn is lower)

but degrades tpLH (increases intrinsic capacitance
GGD and GDB)

ENEE 302H
Lecture/s 9
Transistor Sizing I

Gate Delay, Revisited

Bruce Jacob

5 x 10

University of
Maryland
ECE Dept.

tpLH

4.5

tp(sec)

SLIDE 31

-11

tpHL

tp

3.5

3
1

= (W/Lp)/(W/Ln )

UNIVERSITY OF MARYLAND

/13 k
) [what weve looked at]
of 2.4 (Rp/Rn = 31 k
gives symmetric response
of 1.6 to 1.9 gives optimal performance

ENEE 302H
Lecture/s 9
Transistor Sizing I

Sizing III: Big Gates

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 32

Sizing for Large Capacitive Loads

Cin1

A3(Wp1/Wn1)

A1(Wp1/Wn1)

A0(Wp1/Wn1)

A2(Wp1/Wn1)

Cload

Supose Cload large (e.g. off-chip wires)

Scale each inverter (both FETs in the circuit) by a

factor A (input capacitances scale by A)
if input C to last inverter * A = Cload
(i.e., Cload looks like N+1th inverter) then we have:

Input C of last inverter = Cin1 AN = Cload

Rearranging:

A = [Cload Cin1]1/N
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ENEE 302H
Lecture/s 9
Transistor Sizing I

Sizing III: Big Gates

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 33

Sizing for Large Capacitive Loads

Cin1
A0(Wp1/Wn1)

A3(Wp1/Wn1)

A1(Wp1/Wn1)

A2(Wp1/Wn1)

Capacitances increase by factor of A left to right

Resistances decrease by factor of A left to right
Total delay (tpHL + tpLH):

(Rn1+Rp1) (Cout1+ACin1) +
(Rn1+Rp1)/A (ACout1+A2Cin1) +
= N (Rn1+Rp1) (Cout1+ACin1)

Find optimal chain length:

Nopt = ln(Cload Cin1)

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Cload

ENEE 302H
Lecture/s 9
Transistor Sizing I

Sizing III: Big Gates

Bruce Jacob
University of
Maryland
ECE Dept.
SLIDE 34

I/O Pad: large structures are ESD diodes

and inverter chains (scale: pad is ~65 m)

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ENEE 302H
Lecture/s 9
Transistor Sizing I
Bruce Jacob

Example
2/1

University of
Maryland
ECE Dept.
SLIDE 35

Cin = 2.5fF

Cload = 20pF

Load is ~8000x that of single inverters input

capacitance: find optimal solution.

UNIVERSITY OF MARYLAND

ENEE 302H
Lecture/s 9
Transistor Sizing I

Example

Bruce Jacob

.5/.25

1.4/.7

3.6/1.8

9.8/4.9

27/13

72/36

194/97

523/262 1412/706

University of
Maryland
ECE Dept.
SLIDE 36

(sizes in microns)

Cload = 20pF

Nopt = ln(20pF/2.5fF) = 8.98 => 9 stages

Scaling factor A = (20pF/2.5fF)1/9 = 2.7
Total delay = (tpHL + tpLH)
= N (Rn1+Rp1) (Cout1+ACin1)
= N (Rn1+Rp1) (Cout1 + [Cload Cin1]1/N Cin1)
(assume Cin1 = 1.5Cout1 = 2.5 fF)

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= 9 (31/9 + 13/3) (1.85fF + 2.7 2.5fF)

= 602 ps (0.6 ns)