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Cadence Tutorial New
Cadence Tutorial New
Right click on .cshrc file and choose open with Text Editor
Find the code source/usr/local/etc/ALLSET and Delete this line.
Add two lines to the file
source /opt/cds/class/cds_setup
source /opt/cds/class/setup_files/vhdl/.vhdl_setup
Save and close the editor
Open new terminal by right clicking on desktop and choosing Open in Terminal
smpl_circuit.v
module smpl_circuit(A,B,C,x,y);
module smpl_circuit_tb;
input A,B,C;
reg A,B,C;
output x,y;
wire x,y;
wire e;
smpl_circuit sc(A,B,C,x,y);
and g1(e,A,B);
initial
not g2(y,C);
begin
#25 A=0; B=0; C=0;
or g3(x,e,y);
endmodule
NCLaunch
Once the initial settings are over, further processing can be started from here.
Open the terminal and type the following commands
cd $home/cadence/vhdl
cp $NCVHDL/cds.lib $CDSVHDL
cp $NCVHDL/hdl.var $CDSVHDL
nclaunch &
Select your verilog source file from the file browser area
Compile the selected file either by double clicking the file or choosing Tools -> Verilog
Compiler and press OK in the Compile Verilog window without changing anything.
After compilation the file will appear on the right hand side of the window in the folder name
either worklib or vhdl. You can see the file by clicking the plus sign of the corresponding
folder.
Repeat the same for test bench (Ex: smpl_circuit_tb.v) file also.
Select the compiled test bench file (Ex: smpl_circuit_tb.v) from the worklib or vhdl folder.
Either right click the file and select NCElab... or select Tools -> Elaborator
Select the test bench:module (Ex: vhdl.smpl_circuit_tb:module) file from the Snapshots and
either right click on the file and select NCSim... or select Tools -> Simulator to run the
simulation
Two new windows (Design Browser 1 -SimVision, Console - SimVision) will appear on
clicking OK in the simulate window
ENCOUNTER
1. Setting up the Encounter
Open cadence/vhdl/cds.lib file and add the following line
DEFINE NCSU_TechLib_ami06 /opt/cds/class/local/lib/oa/NCSU_TechLib_ami06
The cadence/VHDL/cds.lib file will look like
include $CDS_INST_DIR/tools/inca/files/cds.lib
#DEFINE ieee /opt/cds/ldv/tools/inca/files/IEEE
#DEFINE std /opt/cds/ldv/tools/inca/files/STD
DEFINE vhdl ~/cadence/vhdl
DEFINE NCSU_TechLib_ami06 /opt/cds/class/local/lib/oa/NCSU_TechLib_ami06
2. Type these commands in you terminal
cd $CDSVHDL
mkdir fe
cd fe
cp $DSMSE/ece753.conf ece753.conf
Go the folder in which you have the verilog file.
3. Open terminal and type encounter
4. Type bgx_shell inside the encounter terminal and create a netlist using the following commands
read_tlf ami06.tlf
set_global hdl_vhdl_environment synopsys
read_verilog smpl_circuit.v
do_build_generic
do_optimize
write_verilog -hier smpl_circuit_net.v
exit
(After entering all these commands a netlist is created with name smpl_circuit_net.v in the folder)
5. Now go to the GUI of encounter
6. Select File -> Import Design
Encounter window
Importing Configuration
7. Click OK
8. Click on Files under verilog in the design import window (By clicking ... on the right side of the
screen)
11. Click OK
12. After clicking the OK button the Encounter window will look like this
Setting Floorplan
14. Click OK without changing anything in the window.
15. Select Power -> Power Planning -> Add Rings
16. Change Top and Bottom to metal3H
17. Change all Width to 4
18. Click OK
22. After these operations the Encounter window will look like this:
26. Click OK, the encounter window will appear as filled and shaded inside
Saving as GDS/OASIS
29. Enter desired verilog name and give extension .gds2 (In this example smpl_circuit_enc.gds2) and
check Structure Name and then press OK
VIRTUOSO
1. Go to terminal and type virtuoso and press enter
2. Often during the process, a license upgrade screen may pop up. Simply press Yes
3. Close all the screens except Library Manager and Log Window
4. Library window select: File -> New -> Library to create a new library.
5. Give a name to the library and click OK (In this example we are giving a name CadenceLibrary)
Note: After creating the library once, you can use the same library again. Hence this step is required
only in the first time use. If you want to create a library at any time you can follow the above
procedure.
XStream In Window