READ ME

Software & Design Kit Version Used

Cadence Version : IC 610
Spectre Version: MMSIM61
Design kit: NCSU design kit, ncsu-cdk-1.6.0.beta from
http://www.eda.ncsu.edu/wiki/NCSU_CDK
STEPS TO LOAD DESIGN:
1. Unzip ChX_cadence to your design directory.
2. Add the following line in your cds.lib file to refer the schematic in the library manager.
DEFINE CMOSedu_ChX_scale <path>/ CMOSedu_ChX_scale
Ex:
DEFINE CMOSedu_Ch9_1u /home/mbalasub/CMOSedu/Ch9_Cadence/CMOSedu_Ch9_1u
3. Start Cadence and click CMOSedu_ChX_scale in your library manager, library.

4. Click on the figX from cell and double click on the schematic from view to open in
SchematicL

5. To start simulation click Launch-> ADE L

6. In Virtuoso Analog Design Environment, Click on Session-> Load state.

7. Set the library to CMOSedu_chX_scale, browse to state folder in ChX_cadence and click ok.

8. The available states for the given fig in the library are displayed in the State Name test box.
Select the required state and press ok.

8. The state gets loaded in the Analog Design Environment.

9. Select the model file from the ChX_cadence directory by selecting Setup->Model Libraries in
ADE L .

10. Make any required changes in ADE L and simulate the design for the required plot.

11. If the simulation demands multiple sweep (ex. DC sweep with variable temperature),
parametric analysis is used. After loading the state, if there is a design variable declared in the
Design variable sub window starting with parameter (parameterTemp in the below screen shot)
use menu option Tools->Parametric Analysis to run the simulation.

12. Enter the design variable information and select the following options from menu to run the
simulation, Analysis->Start